coreboot-gerrit August 2020

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Change in coreboot[master]: src: Use PCI_BASE_ADDRESS_* macro
by HAOUAS Elyes (Code Review) 12 Aug '20

12 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44373 ) Change subject: src: Use PCI_BASE_ADDRESS_* macro ...................................................................... src: Use PCI_BASE_ADDRESS_* macro Change-Id: I1b541aed31bc12b177d2315ec4bf06924d5596c8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/aspeed/common/ast_main.c M src/drivers/aspeed/common/ast_mode_corebootfb.c M src/drivers/uart/oxpcie.c M src/northbridge/intel/pineview/gma.c 4 files changed, 10 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44373/1 diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 5143e6d..8ed1eaa 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -4,6 +4,7 @@ */ #include <delay.h> +#include <device/pci_def.h> #include "ast_drv.h" #include "ast_dram_tables.h" @@ -329,7 +330,7 @@ ast->dev = dev; /* PCI BAR 1 */ - res = find_resource(dev->pdev, 0x14); + res = find_resource(dev->pdev, PCI_BASE_ADDRESS_1); if (!res) { dev_err(dev->pdev, "BAR1 resource not found.\n"); ret = -EIO; @@ -343,7 +344,7 @@ /* PCI BAR 2 */ ast->io_space_uses_mmap = false; - res = find_resource(dev->pdev, 0x18); + res = find_resource(dev->pdev, PCI_BASE_ADDRESS_2); if (!res) { dev_err(dev->pdev, "BAR2 resource not found.\n"); ret = -EIO; diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c index 2a033a0..8418b01 100644 --- a/src/drivers/aspeed/common/ast_mode_corebootfb.c +++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c @@ -3,6 +3,7 @@ * Copied from Linux drivers/gpu/drm/ast/ast_mode.c */ #include <edid.h> +#include <device/pci_def.h> #include "ast_drv.h" @@ -18,7 +19,7 @@ struct drm_framebuffer *fb = crtc->primary->fb; /* PCI BAR 0 */ - struct resource *res = find_resource(crtc->dev->pdev, 0x10); + struct resource *res = find_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0); if (!res) { printk(BIOS_ERR, "BAR0 resource not found.\n"); return -EIO; diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c index d8a8b91..17e0d26 100644 --- a/src/drivers/uart/oxpcie.c +++ b/src/drivers/uart/oxpcie.c @@ -12,7 +12,7 @@ { printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n"); - struct resource *res = find_resource(dev, 0x10); + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) { printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n"); return; diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c index e46bd7c..e0ed0f0 100644 --- a/src/northbridge/intel/pineview/gma.c +++ b/src/northbridge/intel/pineview/gma.c @@ -6,6 +6,7 @@ #include <delay.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_def.h> #include <device/pci_ids.h> #include <device/pci_ops.h> #include <drivers/intel/gma/i915_reg.h> @@ -234,9 +235,9 @@ int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1; /* Find base addresses */ - mmio_res = find_resource(dev, 0x10); - gtt_res = find_resource(dev, 0x1c); - pio_res = find_resource(dev, 0x14); + mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0); + gtt_res = find_resource(dev, PCI_BASE_ADDRESS_3); + pio_res = find_resource(dev, PCI_BASE_ADDRESS_1); physbase = pci_read_config32(dev, 0x5c) & ~0xf; if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44373 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1b541aed31bc12b177d2315ec4bf06924d5596c8 Gerrit-Change-Number: 44373 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Damien Zammit Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: cpu/intel: Core 2 Duo E8200 is not model_6fx
by Angel Pons (Code Review) 11 Aug '20

11 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44247 ) Change subject: cpu/intel: Core 2 Duo E8200 is not model_6fx ...................................................................... cpu/intel: Core 2 Duo E8200 is not model_6fx With a CPUID of 10676, it is clearly model_1067x... Wait, it's already there, but the comment is wrong. There isn't any CPU called Core 2 Solo. Change-Id: Ia4b73537805e2a8fa9e28bde76aa20a524f8f873 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_1067x/model_1067x_init.c M src/cpu/intel/model_6fx/model_6fx_init.c 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/44247/1 diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index cd774d3..ecdb8cf 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -292,7 +292,7 @@ }; static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_INTEL, 0x10676 }, /* Intel Core 2 Solo/Core Duo */ + { X86_VENDOR_INTEL, 0x10676 }, /* Core 2 Duo E8200 */ { X86_VENDOR_INTEL, 0x10677 }, { X86_VENDOR_INTEL, 0x1067A }, { 0, 0 }, diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index e2755f8..d0987b4 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -146,7 +146,6 @@ { X86_VENDOR_INTEL, 0x06fb }, /* Intel Core 2 Solo/Core Duo */ { X86_VENDOR_INTEL, 0x06fd }, /* Intel Core 2 Solo/Core Duo */ { X86_VENDOR_INTEL, 0x10661 }, /* Intel Core 2 Celeron Conroe-L */ - { X86_VENDOR_INTEL, 0x10676 }, /* Core2 Duo E8200 */ { 0, 0 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/44247 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia4b73537805e2a8fa9e28bde76aa20a524f8f873 Gerrit-Change-Number: 44247 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

4 17

Change in coreboot[master]: soc/intel/common/block/gspi: Recalculate BAR after resource allocation
by Jes Klinke (Code Review) 11 Aug '20

11 Aug '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44084 to review the following change. Change subject: soc/intel/common/block/gspi: Recalculate BAR after resource allocation ...................................................................... soc/intel/common/block/gspi: Recalculate BAR after resource allocation The base address of the memory mapped I/O registers should not be cached across resource allocation. This CL will evict the cached value upon exiting the BS_DEV_RESOURCES stage. Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821 Signed-off-by: jbk(a)chromium.org --- M src/soc/intel/common/block/gspi/gspi.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/44084/1 diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 599ab7e..6337226 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -2,6 +2,7 @@ #include <device/mmio.h> #include <assert.h> +#include <bootstate.h> #include <console/console.h> #include <delay.h> #include <device/device.h> @@ -257,6 +258,12 @@ return gspi_base[gspi_bus]; } +static void gspi_clear_base_stash(void *unused) +{ + memset(gspi_base, 0, sizeof(gspi_base)); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, gspi_clear_base_stash, NULL); + /* Parameters for GSPI controller operation. */ struct gspi_ctrlr_params { uintptr_t mmio_base; -- To view, visit https://review.coreboot.org/c/coreboot/+/44084 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I81f2b5bfadbf1aaa3b38cca2bcc44ce521666821 Gerrit-Change-Number: 44084 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

6 15

Change in coreboot[master]: vendorcode/intel/fsp/fsp2_0/CPX-SP: remove non-existing PSTACKs
by Jonathan Zhang (Code Review) 11 Aug '20

11 Aug '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44279 ) Change subject: vendorcode/intel/fsp/fsp2_0/CPX-SP: remove non-existing PSTACKs ...................................................................... vendorcode/intel/fsp/fsp2_0/CPX-SP: remove non-existing PSTACKs CPX-SP has a CSTACK and 3 PSTACKs. Clean up the HOB header file to remove reference to non-existing PSTACKs. Adjust mainboard code accordingly. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ic52b01cd89fb5b3fce64686d91f017f405566acd --- M src/mainboard/ocp/deltalake/ramstage.c M src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h 2 files changed, 13 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44279/1 diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 69d739f..89d466b 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -54,17 +54,17 @@ {CSTACK, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0xE8, "DL on board M.2 #1 - boot"}, {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "DL on board M.2 #2"}, {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "Mezz Card"}, - {PSTACK3, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "1ou expansion M.2 #1"}, - {PSTACK3, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "1ou expansion M.2 #2"}, - {PSTACK3, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "1ou expansion M.2 #3"}, - {PSTACK3, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "1ou expansion M.2 #4"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "1ou expansion M.2 #1"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "1ou expansion M.2 #2"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "1ou expansion M.2 #3"}, + {PSTACK2, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "1ou expansion M.2 #4"}, {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "2ou expansion M.2 #1"}, {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "2ou expansion M.2 #2"}, {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x10, "2ou expansion M.2 #3"}, {PSTACK0, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x18, "2ou expansion M.2 #4"}, {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x00, "2ou expansion M.2 #5"}, {PSTACK1, SlotTypePciExpressGen3X4, SlotDataBusWidth4X, 0x08, "2ou expansion M.2 #6"}, - {PSTACK3, SlotTypePciExpressGen3X16, SlotDataBusWidth16X, 0x00, "Mezz Card(Class-2)"}, + {PSTACK2, SlotTypePciExpressGen3X16, SlotDataBusWidth16X, 0x00, "Mezz Card(Class-2)"}, }; static void dl_oem_smbios_strings(struct device *dev, struct smbios_type11 *t) diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h index a9465e1..5bf36e1 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -90,32 +90,23 @@ IIO PCIe Ports **/ typedef enum { + // IOU0, CSTACK PORT_0 = 0, - // IOU0 + // IOU1, PSTACK0 PORT_1A, PORT_1B, PORT_1C, PORT_1D, - // IOU1 + // IOU2, PASTACK1 PORT_2A, PORT_2B, PORT_2C, PORT_2D, - // IOU2 - PORT_4A, - PORT_4B, - PORT_4C, - PORT_4D, - // MCP0 - PORT_5A, - PORT_5B, - PORT_5C, - PORT_5D, - // MCP1 - PORT_6A, - PORT_6B, - PORT_6C, - PORT_6D, + // IOU3, PSTACK2 + PORT_3A, + PORT_3B, + PORT_3C, + PORT_3D, MAX_PORTS } PCIE_PORTS; @@ -127,8 +118,6 @@ PSTACK0, PSTACK1, PSTACK2, - PSTACK3, - PSTACK4, MAX_STACKS } IIO_STACKS; -- To view, visit https://review.coreboot.org/c/coreboot/+/44279 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic52b01cd89fb5b3fce64686d91f017f405566acd Gerrit-Change-Number: 44279 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

3 7

Change in coreboot[master]: mb/ocp/deltalake: Enable PCH thermal sensor via FSP
by Johnny Lin (Code Review) 11 Aug '20

11 Aug '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44075 ) Change subject: mb/ocp/deltalake: Enable PCH thermal sensor via FSP ...................................................................... mb/ocp/deltalake: Enable PCH thermal sensor via FSP Tested=On OCP Delta Lake, oBMC sensor-util can see PCH Temp readings. Change-Id: I39d0d0a982476f9fece51cfa19dcbd0da5dea690 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/mainboard/ocp/deltalake/romstage.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/44075/1 diff --git a/src/mainboard/ocp/deltalake/romstage.c b/src/mainboard/ocp/deltalake/romstage.c index f69ec60..40ac494 100644 --- a/src/mainboard/ocp/deltalake/romstage.c +++ b/src/mainboard/ocp/deltalake/romstage.c @@ -49,6 +49,8 @@ mupd->FspmConfig.DebugPrintLevel = FSP_LOG_LEVEL_DEFAULT; } } + /* Enable PCH Thermal sensor */ + mupd->FspmConfig.ThermalDeviceEnable = 1; } /* Update bifurcation settings according to different Configs */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44075 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I39d0d0a982476f9fece51cfa19dcbd0da5dea690 Gerrit-Change-Number: 44075 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

4 20

Change in coreboot[master]: /soc/amd/picasso Correct processor scope for picasso
by Jason Glenesk (Code Review) 11 Aug '20

11 Aug '20

Hello Jason Glenesk, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44325 to review the following change. Change subject: /soc/amd/picasso Correct processor scope for picasso ...................................................................... /soc/amd/picasso Correct processor scope for picasso Change namespace from _PR to _SB. Cq-Depend: chrome-internal:3208104 BUG=b:153242529 TEST=Boot a trembyle with change applied and dump SSDTs to ensure processors are in _SB scope. Change-Id: I534f02dc50756759da945cf64d5b3623b0ec9db1 Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/acpi/cpu.asl 2 files changed, 24 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/44325/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 526900a..8001b7a 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -321,7 +321,7 @@ config ACPI_CPU_STRING string - default "\\_PR.C%03d" + default "\\_SB.C%03d" config ACPI_BERT bool "Build ACPI BERT Table" diff --git a/src/soc/amd/picasso/acpi/cpu.asl b/src/soc/amd/picasso/acpi/cpu.asl index 8b61b8f..eb646de 100644 --- a/src/soc/amd/picasso/acpi/cpu.asl +++ b/src/soc/amd/picasso/acpi/cpu.asl @@ -36,14 +36,14 @@ * Processor Object */ /* These devices are created at runtime */ -External (\_PR.C000, DeviceObj) -External (\_PR.C001, DeviceObj) -External (\_PR.C002, DeviceObj) -External (\_PR.C003, DeviceObj) -External (\_PR.C004, DeviceObj) -External (\_PR.C005, DeviceObj) -External (\_PR.C006, DeviceObj) -External (\_PR.C007, DeviceObj) +External (\_SB.C000, DeviceObj) +External (\_SB.C001, DeviceObj) +External (\_SB.C002, DeviceObj) +External (\_SB.C003, DeviceObj) +External (\_SB.C004, DeviceObj) +External (\_SB.C005, DeviceObj) +External (\_SB.C006, DeviceObj) +External (\_SB.C007, DeviceObj) /* Return a package containing enabled processor entries */ Method (PPKG) @@ -51,33 +51,33 @@ If (LGreaterEqual (\PCNT, 8)) { Return (Package () { - \_PR.C000, - \_PR.C001, - \_PR.C002, - \_PR.C003, - \_PR.C004, - \_PR.C005, - \_PR.C006, - \_PR.C007 + \_SB.C000, + \_SB.C001, + \_SB.C002, + \_SB.C003, + \_SB.C004, + \_SB.C005, + \_SB.C006, + \_SB.C007 }) } ElseIf (LGreaterEqual (\PCNT, 4)) { Return (Package () { - \_PR.C000, - \_PR.C001, - \_PR.C002, - \_PR.C003 + \_SB.C000, + \_SB.C001, + \_SB.C002, + \_SB.C003 }) } ElseIf (LGreaterEqual (\PCNT, 2)) { Return (Package () { - \_PR.C000, - \_PR.C001 + \_SB.C000, + \_SB.C001 }) } Else { Return (Package () { - \_PR.C000 + \_SB.C000 }) } } -- To view, visit https://review.coreboot.org/c/coreboot/+/44325 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I534f02dc50756759da945cf64d5b3623b0ec9db1 Gerrit-Change-Number: 44325 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Tim Wawrzynczak (Code Review) 11 Aug '20

11 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > > Patch Set 4: > > > > > > > Patch Set 4: > > > > > > > > > Patch Set 4: > > > > > > > > > > > Patch Set 4: > > > > > > > > > > > > FYI I was able to boot my Volteer with this patch & adding COS_MAPPED_TO_MSB and USE_CAR_NEM_ENHANCED_V1 to the Kconfig. > > > > > > > > > > Thanks for checking Tim :-) > > > > > TGL can select USE_CAR_NEM_ENHANCED_V2. > > > > > > > > Oops, yeah that was a typo in Gerrit not in the code, I did use V2 in my Kconfig 😄 > > > > > > Hi Tim, did you use Volteer QS / Volteer EVT? Because on Volteer ES2, we would see that these 2 MSRs are not accessible. > > > > I just thought about that, no it was on proto2. I just received my other board, I will try it out soon. > > Ok. Thanks the info. I can confirm my volteer2 (should be QS) boots with this patch and the 2 Kconfigs selected. I am not aware of any other mechanism to verify the CQOS is set up correctly -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 11 Aug 2020 19:31:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Define stop_gpio for goodix touch screen
by Tim Wawrzynczak (Code Review) 11 Aug '20

11 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44356 ) Change subject: mb/google/volteer: Define stop_gpio for goodix touch screen ...................................................................... Patch Set 1: (3 comments) https://review.coreboot.org/c/coreboot/+/44356/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44356/1//COMMIT_MSG@11 PS1, Line 11: defins defines https://review.coreboot.org/c/coreboot/+/44356/1/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/volteer/overridetree.cb: https://review.coreboot.org/c/coreboot/+/44356/1/src/mainboard/google/volte… PS1, Line 93: 120 have you tried 10ms here? https://review.coreboot.org/c/coreboot/+/44356/1/src/mainboard/google/volte… PS1, Line 98: 12 same, have you tried 10 here? -- To view, visit https://review.coreboot.org/c/coreboot/+/44356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b Gerrit-Change-Number: 44356 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Mice Lin <mice_lin(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Aug 2020 19:27:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/espi_util: espi_send_command: improve error message
by Felix Held (Code Review) 11 Aug '20

11 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44352 ) Change subject: soc/amd/common/espi_util: espi_send_command: improve error message ...................................................................... soc/amd/common/espi_util: espi_send_command: improve error message It's only an error if bits other than ESPI_STATUS_DNCMD_COMPLETE are set in the status register. If ESPI_STATUS_DNCMD_COMPLETE isn't set, the command failed, so we expect that one to be set. Change-Id: I6f1fb5a59b1ecadd6724a07212626f21fb90e7e7 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/44352/1 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 4415615..c1145d0 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -470,7 +470,7 @@ } if (status & ~ESPI_STATUS_DNCMD_COMPLETE) { - espi_show_failure(cmd, "Error: eSPI status register bits set", status); + espi_show_failure(cmd, "Error: unexpected eSPI status register bits set", status); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44352 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f1fb5a59b1ecadd6724a07212626f21fb90e7e7 Gerrit-Change-Number: 44352 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug
by Felix Held (Code Review) 11 Aug '20

11 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44351 ) Change subject: soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug ...................................................................... soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug When address and data register for the SIO control register access is passed as one I/O region with a size of 2, the corresponding special decode enable register should be used instead of a generic one to save the rather limited generic ones for other decode ranges. Change-Id: Ie54ff6afa2bd2156f7b3a3cf83091f1f932b6993 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/44351/1 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 3f26a29..4415615 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -104,6 +104,9 @@ */ static int espi_std_io_decode(uint16_t base, size_t size) { + if (size == 2 && base == 0x2e) + return ESPI_DECODE_IO_0X2E_0X2F_EN; + if (size != 1) return -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/44351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie54ff6afa2bd2156f7b3a3cf83091f1f932b6993 Gerrit-Change-Number: 44351 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020