Change in coreboot[master]: src: Use PCI_BASE_ADDRESS_* macro

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44373 )

Change subject: src: Use PCI_BASE_ADDRESS_* macro
......................................................................

src: Use PCI_BASE_ADDRESS_* macro

Change-Id: I1b541aed31bc12b177d2315ec4bf06924d5596c8
Signed-off-by: Elyes HAOUAS 
---
M src/drivers/aspeed/common/ast_main.c
M src/drivers/aspeed/common/ast_mode_corebootfb.c
M src/drivers/uart/oxpcie.c
M src/northbridge/intel/pineview/gma.c
4 files changed, 10 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/44373/1

diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c
index 5143e6d..8ed1eaa 100644
--- a/src/drivers/aspeed/common/ast_main.c
+++ b/src/drivers/aspeed/common/ast_main.c
@@ -4,6 +4,7 @@
  */

#include <delay.h>
+#include <device/pci_def.h>

#include "ast_drv.h"
 #include "ast_dram_tables.h"
@@ -329,7 +330,7 @@
    ast->dev = dev;

/* PCI BAR 1 */
-	res = find_resource(dev->pdev, 0x14);
+	res = find_resource(dev->pdev, PCI_BASE_ADDRESS_1);
    if (!res) {
    	dev_err(dev->pdev, "BAR1 resource not found.\n");
    	ret = -EIO;
@@ -343,7 +344,7 @@

/* PCI BAR 2 */
    ast->io_space_uses_mmap = false;
-	res = find_resource(dev->pdev, 0x18);
+	res = find_resource(dev->pdev, PCI_BASE_ADDRESS_2);
    if (!res) {
    	dev_err(dev->pdev, "BAR2 resource not found.\n");
    	ret = -EIO;
diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c
index 2a033a0..8418b01 100644
--- a/src/drivers/aspeed/common/ast_mode_corebootfb.c
+++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c
@@ -3,6 +3,7 @@
  * Copied from Linux drivers/gpu/drm/ast/ast_mode.c
  */
 #include <edid.h>
+#include <device/pci_def.h>

#include "ast_drv.h"

@@ -18,7 +19,7 @@
    struct drm_framebuffer *fb = crtc->primary->fb;

/* PCI BAR 0 */
-	struct resource *res = find_resource(crtc->dev->pdev, 0x10);
+	struct resource *res = find_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0);
    if (!res) {
    	printk(BIOS_ERR, "BAR0 resource not found.\n");
    	return -EIO;
diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c
index d8a8b91..17e0d26 100644
--- a/src/drivers/uart/oxpcie.c
+++ b/src/drivers/uart/oxpcie.c
@@ -12,7 +12,7 @@
 {
    printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n");

-	struct resource *res = find_resource(dev, 0x10);
+	struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
    if (!res) {
    	printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
    	return;
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index e46bd7c..e0ed0f0 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -6,6 +6,7 @@
 #include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <drivers/intel/gma/i915_reg.h>
@@ -234,9 +235,9 @@
    	int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;

/* Find base addresses */
-		mmio_res = find_resource(dev, 0x10);
-		gtt_res  = find_resource(dev, 0x1c);
-		pio_res  = find_resource(dev, 0x14);
+		mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+		gtt_res  = find_resource(dev, PCI_BASE_ADDRESS_3);
+		pio_res  = find_resource(dev, PCI_BASE_ADDRESS_1);
    	physbase = pci_read_config32(dev, 0x5c) & ~0xf;

if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) {

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44373 )

Change subject: src: Use PCI_BASE_ADDRESS_* macro
......................................................................

Abandoned

see 44371