coreboot-gerrit August 2020

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Change in coreboot[master]: soc/mediatek/mt8183: Transfer ddr geometry type to dram blob
by Duan huayang (Code Review) 12 Aug '20

12 Aug '20

Duan huayang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43796 ) Change subject: soc/mediatek/mt8183: Transfer ddr geometry type to dram blob ...................................................................... soc/mediatek/mt8183: Transfer ddr geometry type to dram blob BUG=none BRANCH=kukui TEST=Boots correctly on Kukui Change-Id: I3a677195f5036321939c60c8f9f1bace7c4a2e3f Signed-off-by: Huayang Duan <huayang.duan(a)mediatek.com> --- M src/soc/mediatek/mt8183/memory.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/43796/1 diff --git a/src/soc/mediatek/mt8183/memory.c b/src/soc/mediatek/mt8183/memory.c index ff30f67..395a885 100644 --- a/src/soc/mediatek/mt8183/memory.c +++ b/src/soc/mediatek/mt8183/memory.c @@ -99,6 +99,7 @@ static int dram_run_full_calibration(struct dramc_param *dparam, u16 config) { + const struct sdram_params * sdram_cfg = get_sdram_config(); initialize_dramc_param(dparam, config); /* Load and run the provided blob for full-calibration if available */ @@ -111,6 +112,8 @@ return -2; dparam->do_putc = do_putchar; + dparam->freq_params[0].ddr_geometry = sdram_cfg->ddr_geometry; + printk(BIOS_INFO, "ddr_geometry:%d\n", sdram_cfg->ddr_geometry); prog_set_entry(&dram, prog_entry(&dram), dparam); prog_run(&dram); -- To view, visit https://review.coreboot.org/c/coreboot/+/43796 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a677195f5036321939c60c8f9f1bace7c4a2e3f Gerrit-Change-Number: 43796 Gerrit-PatchSet: 1 Gerrit-Owner: Duan huayang <huayang.duan(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: enable JSL USB3 dbc
by Kane Chen (Code Review) 12 Aug '20

12 Aug '20

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44407 ) Change subject: enable JSL USB3 dbc ...................................................................... enable JSL USB3 dbc Signed-off-by: Kane Chen <kane.chen(a)intel.com> Change-Id: I2c6d84270431049947800d6598d596010414795e --- M src/soc/intel/jasperlake/romstage/fsp_params.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/44407/1 diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 809ae80..0639408 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -123,6 +123,7 @@ soc_memory_init_params(m_cfg, config); mainboard_memory_init_params(mupd); + m_cfg->PlatformDebugConsent = 3; } __weak void mainboard_memory_init_params(FSPM_UPD *mupd) -- To view, visit https://review.coreboot.org/c/coreboot/+/44407 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c6d84270431049947800d6598d596010414795e Gerrit-Change-Number: 44407 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: crossgcc: Enable GCC to get asan shadow offset at runtime
by Harshit Sharma (Code Review) 12 Aug '20

12 Aug '20

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42794 ) Change subject: crossgcc: Enable GCC to get asan shadow offset at runtime ...................................................................... Patch Set 20: Sorry. I had forgotten to update the commit message in the actual patch file. -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 20 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Wed, 12 Aug 2020 01:54:55 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: crossgcc: Enable GCC to get asan shadow offset at runtime
by Harshit Sharma (Code Review) 12 Aug '20

12 Aug '20

Hello build bot (Jenkins), Patrick Georgi, Paul Menzel, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42794 to look at the new patch set (#20). Change subject: crossgcc: Enable GCC to get asan shadow offset at runtime ...................................................................... crossgcc: Enable GCC to get asan shadow offset at runtime Unlike Linux kernel which has a static shadow region layout, we have multiple stages in coreboot and thus require a different shadow offset address. Unfortunately, GCC currently only supports adding a static shadow offset at compile time using -fasan-shadow-offset flag. For this reason, we enable GCC to determine asan shadow offset address at runtime using a callback function named __asan_shadow_offset(). This supersedes the need to specify this address at compile time. GCC then makes use of this shadow offset to protect stack buffers by inserting red zones around them. Some other benefits of having this GCC patch are: a. We can place the shadow region in a separate linker section with all its advantages like automatic fit insurance. This ensures if a platform doesn't have enough memory space to hold shadow region, the build will fail. (However, if we use a fixed shadow offset on a platform that actually doesn't have enough memory, it may still build without any errors.) b. We don't modify the memory layout compared to the current one, as we are placing the shadow region at the end of the space already occupied by the program. c. We can be much more flexible later if needed (thinking of other stages like bootblock). d. Since we are appending the shadow buffer to the region already occupied, we make efficient use of the limited memory available which is highly beneficial when using cache as ram. Further, we have made sure that if you compile you tree with ASan enabled but missed this patch, it will end up in the following compilation error: "invalid --param name 'asan-use-shadow-offset-callback'" So, you cannot accidentally enable the feature without having your compiler patched. Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- A util/crossgcc/patches/gcc-8.3.0_asan_shadow_offset_callback.patch 1 file changed, 109 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/42794/20 -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 20 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: crossgcc: Enable GCC to get asan shadow offset at runtime
by Harshit Sharma (Code Review) 12 Aug '20

12 Aug '20

Hello build bot (Jenkins), Patrick Georgi, Paul Menzel, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42794 to look at the new patch set (#19). Change subject: crossgcc: Enable GCC to get asan shadow offset at runtime ...................................................................... crossgcc: Enable GCC to get asan shadow offset at runtime Unlike Linux kernel which has a static shadow region layout, we have multiple stages in coreboot and thus require a different shadow offset address. Unfortunately, GCC currently only supports adding a static shadow offset at compile time using -fasan-shadow-offset flag. For this reason, we enable GCC to determine asan shadow offset address at runtime using a callback function named __asan_shadow_offset(). This supersedes the need to specify this address at compile time. GCC then makes use of this shadow offset to protect stack buffers by inserting red zones around them. Some other benefits of having this GCC patch are: a. We can place the shadow region in a separate linker section with all its advantages like automatic fit insurance. This ensures if a platform doesn't have enough memory space to hold shadow region, the build will fail. (However, if we use a fixed shadow offset on a platform that actually doesn't have enough memory, it may still build without any errors.) b. We don't modify the memory layout compared to the current one, as we are placing the shadow region at the end of the space already occupied by the program. c. We can be much more flexible later if needed (thinking of other stages like bootblock). d. Since we are appending the shadow buffer to the region already occupied, we make efficient use of the limited memory available which is highly beneficial when using cache as ram. Further, we have made sure that if you compile you tree with ASan enabled but missed this patch, it will end up in the following compilation error: "invalid --param name 'asan-use-shadow-offset-callback'" So, you cannot accidentally enable the feature without having your compiler patched. Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- A util/crossgcc/patches/gcc-8.3.0_asan_shadow_offset_callback.patch 1 file changed, 109 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/42794/19 -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 19 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib: Add ASan support to ramstage on x86 arch
by Harshit Sharma (Code Review) 12 Aug '20

12 Aug '20

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42496 ) Change subject: lib: Add ASan support to ramstage on x86 arch ...................................................................... Patch Set 27: (2 comments) https://review.coreboot.org/c/coreboot/+/42496/26/src/include/asan.h File src/include/asan.h: https://review.coreboot.org/c/coreboot/+/42496/26/src/include/asan.h@42 PS26, Line 42: > Would you mind to align this comment properly with the line before? Sure. No problem. https://review.coreboot.org/c/coreboot/+/42496/26/src/include/asan.h@45 PS26, Line 45: > Same here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/42496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Gerrit-Change-Number: 42496 Gerrit-PatchSet: 27 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Wed, 12 Aug 2020 00:44:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add ASan support to ramstage on x86 arch
by Harshit Sharma (Code Review) 12 Aug '20

12 Aug '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Paul Menzel, Julius Werner, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42496 to look at the new patch set (#27). Change subject: lib: Add ASan support to ramstage on x86 arch ...................................................................... lib: Add ASan support to ramstage on x86 arch This patch adds address sanitizer module to the library and reserves a linker section representing the shadow region for ramstage. Also, it adds an instruction to initialize shadow region on x86 architecture when ramstage is loaded. Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- M src/arch/x86/c_start.S A src/include/asan.h M src/include/symbols.h M src/lib/asan.c M src/lib/program.ld 5 files changed, 528 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/42496/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/42496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Gerrit-Change-Number: 42496 Gerrit-PatchSet: 27 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP QS processor
by Jonathan Zhang (Code Review) 11 Aug '20

11 Aug '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44361 ) Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP QS processor ...................................................................... soc/intel/xeon_sp/cpx: add CPUID for CPX-SP QS processor Add CPUID for CPX-SP QS processor. DeltaLake DVT server uses CPX-SP QS processor. TESTED=booted DeltaLake DVT server to target OS. [root@localhost ~]# dmidecode -t 1 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: Wiwynn Product Name: Delta Lake DVT Version: YoDL03 Serial Number: BZA02200122N01A UUID: 000A0A22-2C29-1ED6-8259-000055DA2BFF Wake-up Type: Reserved SKU Number: Not Specified Family: DeltaLake Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ic8975f6bf752fd685b38b2d1f0a4da41983b57f6 temp Change-Id: I9348ac9b3328786d0083bb1f6f8bb6b74c2be21a --- M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/44361/1 diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index cf903b8..f4ed0bb 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -100,6 +100,7 @@ static const struct cpu_device_id cpu_table[] = { {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A0}, + {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_QS}, {0, 0}, }; diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 1458000..220868e 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -7,6 +7,7 @@ #include <cpu/x86/msr.h> #define CPUID_COOPERLAKE_SP_A0 0x05065a +#define CPUID_COOPERLAKE_SP_QS 0x05065b /* CPU bus clock is fixed at 100MHz */ #define CPU_BCLK 100 -- To view, visit https://review.coreboot.org/c/coreboot/+/44361 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9348ac9b3328786d0083bb1f6f8bb6b74c2be21a Gerrit-Change-Number: 44361 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: amd/picasso/acpi: Add power resources for UART0
by Aaron Durbin (Code Review) 11 Aug '20

11 Aug '20

Aaron Durbin has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44266 ) Change subject: amd/picasso/acpi: Add power resources for UART0 ...................................................................... amd/picasso/acpi: Add power resources for UART0 Follow-up for a31a769 - "amd/picasso/acpi: Add power resources for I2C and UART". Now PSP properly handles UART0 D3, we can shutdown UART0. BUG=b:158772504 TEST=suspend_stress_test for 50 cycles, * echo 1 > /sys/module/acpi/parameters/aml_debug_output * dmesg | grep FUR to check on&off for FUR0 [ 2413.647500] ACPI Debug: "AOAC.FUR0._OFF" [ 2413.736265] ACPI Debug: "AOAC.FUR0._ON" Change-Id: I25457e18b69d28a83e42c2fe02b45a3979ad58cd Signed-off-by: Kangheui Won <khwon(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44266 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Raul Rangel <rrangel(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/soc/amd/picasso/acpi/aoac.asl M src/soc/amd/picasso/acpi/sb_fch.asl 2 files changed, 13 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Aaron Durbin: Looks good to me, approved Raul Rangel: Looks good to me, approved diff --git a/src/soc/amd/picasso/acpi/aoac.asl b/src/soc/amd/picasso/acpi/aoac.asl index 727b9bb..ffdfcd4 100644 --- a/src/soc/amd/picasso/acpi/aoac.asl +++ b/src/soc/amd/picasso/acpi/aoac.asl @@ -139,6 +139,7 @@ AOAC_DEVICE(I2C2, 7, 0) AOAC_DEVICE(I2C3, 8, 0) + AOAC_DEVICE(FUR0, 11, 0) AOAC_DEVICE(FUR1, 12, 0) AOAC_DEVICE(FUR2, 16, 0) AOAC_DEVICE(FUR3, 26, 0) diff --git a/src/soc/amd/picasso/acpi/sb_fch.asl b/src/soc/amd/picasso/acpi/sb_fch.asl index 4eca52c..6cbfc5f 100644 --- a/src/soc/amd/picasso/acpi/sb_fch.asl +++ b/src/soc/amd/picasso/acpi/sb_fch.asl @@ -122,6 +122,18 @@ Return (Local0) } } + + Name (_PR0, Package () { \_SB.AOAC.FUR0 }) + Name (_PR2, Package () { \_SB.AOAC.FUR0 }) + Name (_PR3, Package () { \_SB.AOAC.FUR0 }) + Method (_PS0, 0, Serialized) { + Printf("FUR0._PS0") + \_SB.AOAC.FUR0.TDS = 1 + } + Method (_PS3, 0, Serialized) { + Printf("FUR0._PS3") + \_SB.AOAC.FUR0.TDS = 3 + } } Device (FUR1) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44266 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25457e18b69d28a83e42c2fe02b45a3979ad58cd Gerrit-Change-Number: 44266 Gerrit-PatchSet: 3 Gerrit-Owner: Kangheui Won <khwon(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: (test)lz4/lib: use 'std=c17'
by HAOUAS Elyes (Code Review) 11 Aug '20

11 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44194 ) Change subject: (test)lz4/lib: use 'std=c17' ...................................................................... (test)lz4/lib: use 'std=c17' Change-Id: Ib7f464f31198155feb2a7c249cc2a0a8ab60e3ba Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/cbfstool/lz4/lib/Makefile 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/44194/1 diff --git a/util/cbfstool/lz4/lib/Makefile b/util/cbfstool/lz4/lib/Makefile index 12a741d..28e6963 100644 --- a/util/cbfstool/lz4/lib/Makefile +++ b/util/cbfstool/lz4/lib/Makefile @@ -41,7 +41,7 @@ PREFIX ?= /usr/local CPPFLAGS= -DXXH_NAMESPACE=LZ4_ CFLAGS ?= -O3 -CFLAGS += -std=c99 -Wall -Wextra -Wundef -Wshadow -Wcast-align -Wcast-qual -Wstrict-prototypes -pedantic +CFLAGS += -std=c17 -Wall -Wextra -Wundef -Wshadow -Wcast-align -Wcast-qual -Wstrict-prototypes -pedantic FLAGS = $(CPPFLAGS) $(CFLAGS) $(LDFLAGS) LIBDIR?= $(PREFIX)/lib -- To view, visit https://review.coreboot.org/c/coreboot/+/44194 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib7f464f31198155feb2a7c249cc2a0a8ab60e3ba Gerrit-Change-Number: 44194 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020