coreboot-gerrit August 2020

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Change in coreboot[master]: lib: Add ASan support to ramstage on x86 arch
by Werner Zeh (Code Review) 12 Aug '20

12 Aug '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42496 ) Change subject: lib: Add ASan support to ramstage on x86 arch ...................................................................... Patch Set 27: Code-Review+2 This patchset was tested on mc_apl1 without issues, it boots up fine. -- To view, visit https://review.coreboot.org/c/coreboot/+/42496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Gerrit-Change-Number: 42496 Gerrit-PatchSet: 27 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Wed, 12 Aug 2020 16:18:06 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: crossgcc: Enable GCC to get asan shadow offset at runtime
by Werner Zeh (Code Review) 12 Aug '20

12 Aug '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42794 ) Change subject: crossgcc: Enable GCC to get asan shadow offset at runtime ...................................................................... Patch Set 20: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 20 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Wed, 12 Aug 2020 16:14:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common/espi_util: rename espi_check_status
by Felix Held (Code Review) 12 Aug '20

12 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44354 ) Change subject: soc/amd/common/espi_util: rename espi_check_status ...................................................................... soc/amd/common/espi_util: rename espi_check_status espi_poll_status describes better what the function actually does, since it polls the status register instead of just doing a single read to check. Change-Id: I0feeef5504bd911e1fb0a00d4f4c546df3548db2 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/44354/1 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index f1afbdb..5fbd7a3 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -406,7 +406,7 @@ * Wait up to ESPI_CMD_TIMEOUT_US for interrupt status register to update after sending a * command. */ -static int espi_check_status(uint32_t *status) +static int espi_poll_status(uint32_t *status) { struct stopwatch sw; @@ -457,7 +457,7 @@ return -1; } - if (espi_check_status(&status) == -1) { + if (espi_poll_status(&status) == -1) { espi_show_failure(cmd, "Error: eSPI check status failed", 0); return -1; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44354 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0feeef5504bd911e1fb0a00d4f4c546df3548db2 Gerrit-Change-Number: 44354 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: trogdor: SoC makefile blob support
by Ravi Kumar Bokka (Code Review) 12 Aug '20

12 Aug '20

Ravi Kumar Bokka has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35508 ) Change subject: trogdor: SoC makefile blob support ...................................................................... Patch Set 88: addressed review comments -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 88 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Wed, 12 Aug 2020 11:32:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/bd82x6x: Make `pch_silicon_supported` static
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44339 ) Change subject: sb/intel/bd82x6x: Make `pch_silicon_supported` static ...................................................................... sb/intel/bd82x6x: Make `pch_silicon_supported` static It's not needed anywhere else. Change-Id: Ibc02e432bbc669b3fcfcb8add3c7b0c2a9f77d77 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pch.c M src/southbridge/intel/bd82x6x/pch.h 2 files changed, 1 insertion(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44339/1 diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 7b0662b..82b95f6 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -41,7 +41,7 @@ return pch_type; } -int pch_silicon_supported(int type, int rev) +static int pch_silicon_supported(int type, int rev) { int cur_type = pch_silicon_type(); int cur_rev = pch_silicon_revision(); diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 68f599d..eff0858 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -42,7 +42,6 @@ int pch_silicon_revision(void); int pch_silicon_type(void); -int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void enable_usb_bar(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/44339 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibc02e432bbc669b3fcfcb8add3c7b0c2a9f77d77 Gerrit-Change-Number: 44339 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Factor out IOBP API
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41946 ) Change subject: sb/intel/lynxpoint: Factor out IOBP API ...................................................................... sb/intel/lynxpoint: Factor out IOBP API Change-Id: Icb6114302cebe19bc3c1971929ea4fc085b454be Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/Makefile.inc A src/southbridge/intel/lynxpoint/iobp.c A src/southbridge/intel/lynxpoint/iobp.h M src/southbridge/intel/lynxpoint/lpc.c M src/southbridge/intel/lynxpoint/pch.c M src/southbridge/intel/lynxpoint/pch.h M src/southbridge/intel/lynxpoint/pcie.c M src/southbridge/intel/lynxpoint/sata.c M src/southbridge/intel/lynxpoint/serialio.c M src/southbridge/intel/lynxpoint/usb_ehci.c M src/southbridge/intel/lynxpoint/usb_xhci.c 11 files changed, 131 insertions(+), 107 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/41946/1 diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index fa0ef0b..b887586 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -5,6 +5,7 @@ bootblock-y += bootblock.c ramstage-y += pch.c +ramstage-y += iobp.c ramstage-y += azalia.c ramstage-y += lpc.c ramstage-y += pcie.c diff --git a/src/southbridge/intel/lynxpoint/iobp.c b/src/southbridge/intel/lynxpoint/iobp.c new file mode 100644 index 0000000..3df6940 --- /dev/null +++ b/src/southbridge/intel/lynxpoint/iobp.c @@ -0,0 +1,111 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <delay.h> +#include "pch.h" +#include "iobp.h" + +#define IOBP_RETRY 1000 + +static inline int iobp_poll(void) +{ + unsigned int try; + + for (try = IOBP_RETRY; try > 0; try--) { + u16 status = RCBA16(IOBPS); + if ((status & IOBPS_READY) == 0) + return 1; + udelay(10); + } + + printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n"); + return 0; +} + +u32 pch_iobp_read(u32 address) +{ + u16 status; + + if (!iobp_poll()) + return 0; + + /* Set the address */ + RCBA32(IOBPIRI) = address; + + /* READ OPCODE */ + status = RCBA16(IOBPS); + status &= ~IOBPS_MASK; + status |= IOBPS_READ; + RCBA16(IOBPS) = status; + + /* Undocumented magic */ + RCBA16(IOBPU) = IOBPU_MAGIC; + + /* Set ready bit */ + status = RCBA16(IOBPS); + status |= IOBPS_READY; + RCBA16(IOBPS) = status; + + if (!iobp_poll()) + return 0; + + /* Check for successful transaction */ + status = RCBA16(IOBPS); + if (status & IOBPS_TX_MASK) { + printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address); + return 0; + } + + /* Read IOBP data */ + return RCBA32(IOBPD); +} + +void pch_iobp_write(u32 address, u32 data) +{ + u16 status; + + if (!iobp_poll()) + return; + + /* Set the address */ + RCBA32(IOBPIRI) = address; + + /* WRITE OPCODE */ + status = RCBA16(IOBPS); + status &= ~IOBPS_MASK; + status |= IOBPS_WRITE; + RCBA16(IOBPS) = status; + + RCBA32(IOBPD) = data; + + /* Undocumented magic */ + RCBA16(IOBPU) = IOBPU_MAGIC; + + /* Set ready bit */ + status = RCBA16(IOBPS); + status |= IOBPS_READY; + RCBA16(IOBPS) = status; + + if (!iobp_poll()) + return; + + /* Check for successful transaction */ + status = RCBA16(IOBPS); + if (status & IOBPS_TX_MASK) { + printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address); + return; + } + + printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); +} + +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) +{ + u32 data = pch_iobp_read(address); + + /* Update the data */ + data &= andvalue; + data |= orvalue; + + pch_iobp_write(address, data); +} diff --git a/src/southbridge/intel/lynxpoint/iobp.h b/src/southbridge/intel/lynxpoint/iobp.h new file mode 100644 index 0000000..c8669ba --- /dev/null +++ b/src/southbridge/intel/lynxpoint/iobp.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOUTHBRIDGE_INTEL_LYNXPOINT_IOBP_H +#define SOUTHBRIDGE_INTEL_LYNXPOINT_IOBP_H + +#include <stdint.h> + +u32 pch_iobp_read(u32 address); +void pch_iobp_write(u32 address, u32 data); +void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); + +#endif diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index 02ea34c..53bcc25 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -15,6 +15,7 @@ #include <cbmem.h> #include <string.h> #include "chip.h" +#include "iobp.h" #include "nvs.h" #include "pch.h" #include <acpi/acpigen.h> diff --git a/src/southbridge/intel/lynxpoint/pch.c b/src/southbridge/intel/lynxpoint/pch.c index 9564b76..d04eec7 100644 --- a/src/southbridge/intel/lynxpoint/pch.c +++ b/src/southbridge/intel/lynxpoint/pch.c @@ -6,6 +6,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_def.h> +#include "iobp.h" #include "pch.h" #ifdef __SIMPLE_DEVICE__ @@ -175,110 +176,6 @@ } } -#define IOBP_RETRY 1000 -static inline int iobp_poll(void) -{ - unsigned int try; - - for (try = IOBP_RETRY; try > 0; try--) { - u16 status = RCBA16(IOBPS); - if ((status & IOBPS_READY) == 0) - return 1; - udelay(10); - } - - printk(BIOS_ERR, "IOBP: timeout waiting for transaction to complete\n"); - return 0; -} - -u32 pch_iobp_read(u32 address) -{ - u16 status; - - if (!iobp_poll()) - return 0; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* READ OPCODE */ - status = RCBA16(IOBPS); - status &= ~IOBPS_MASK; - status |= IOBPS_READ; - RCBA16(IOBPS) = status; - - /* Undocumented magic */ - RCBA16(IOBPU) = IOBPU_MAGIC; - - /* Set ready bit */ - status = RCBA16(IOBPS); - status |= IOBPS_READY; - RCBA16(IOBPS) = status; - - if (!iobp_poll()) - return 0; - - /* Check for successful transaction */ - status = RCBA16(IOBPS); - if (status & IOBPS_TX_MASK) { - printk(BIOS_ERR, "IOBP: read 0x%08x failed\n", address); - return 0; - } - - /* Read IOBP data */ - return RCBA32(IOBPD); -} - -void pch_iobp_write(u32 address, u32 data) -{ - u16 status; - - if (!iobp_poll()) - return; - - /* Set the address */ - RCBA32(IOBPIRI) = address; - - /* WRITE OPCODE */ - status = RCBA16(IOBPS); - status &= ~IOBPS_MASK; - status |= IOBPS_WRITE; - RCBA16(IOBPS) = status; - - RCBA32(IOBPD) = data; - - /* Undocumented magic */ - RCBA16(IOBPU) = IOBPU_MAGIC; - - /* Set ready bit */ - status = RCBA16(IOBPS); - status |= IOBPS_READY; - RCBA16(IOBPS) = status; - - if (!iobp_poll()) - return; - - /* Check for successful transaction */ - status = RCBA16(IOBPS); - if (status & IOBPS_TX_MASK) { - printk(BIOS_ERR, "IOBP: write 0x%08x failed\n", address); - return; - } - - printk(BIOS_INFO, "IOBP: set 0x%08x to 0x%08x\n", address, data); -} - -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue) -{ - u32 data = pch_iobp_read(address); - - /* Update the data */ - data &= andvalue; - data |= orvalue; - - pch_iobp_write(address, data); -} - void pch_enable(struct device *dev) { u16 reg16; diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 6e2bd24..674f20f 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -153,9 +153,6 @@ void pch_enable(struct device *dev); void pch_disable_devfn(struct device *dev); -u32 pch_iobp_read(u32 address); -void pch_iobp_write(u32 address, u32 data); -void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void pch_log_state(void); void acpi_create_intel_hpet(acpi_hpet_t * hpet); void acpi_create_serialio_ssdt(acpi_header_t *ssdt); diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 79b9517..0d0b7a6 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -9,6 +9,7 @@ #include <device/pciexp.h> #include <device/pci_ids.h> #include <device/pci_ops.h> +#include "iobp.h" #include "pch.h" #include <southbridge/intel/common/gpio.h> #include <stddef.h> diff --git a/src/southbridge/intel/lynxpoint/sata.c b/src/southbridge/intel/lynxpoint/sata.c index 9515473..4ad41fe 100644 --- a/src/southbridge/intel/lynxpoint/sata.c +++ b/src/southbridge/intel/lynxpoint/sata.c @@ -8,6 +8,7 @@ #include <device/pci_ids.h> #include <delay.h> #include "chip.h" +#include "iobp.h" #include "pch.h" typedef struct southbridge_intel_lynxpoint_config config_t; diff --git a/src/southbridge/intel/lynxpoint/serialio.c b/src/southbridge/intel/lynxpoint/serialio.c index a75cea0..78ac253 100644 --- a/src/southbridge/intel/lynxpoint/serialio.c +++ b/src/southbridge/intel/lynxpoint/serialio.c @@ -8,6 +8,7 @@ #include <device/pci.h> #include <device/pci_ids.h> #include "chip.h" +#include "iobp.h" #include "pch.h" #include "nvs.h" diff --git a/src/southbridge/intel/lynxpoint/usb_ehci.c b/src/southbridge/intel/lynxpoint/usb_ehci.c index 74ef021..8bb7532 100644 --- a/src/southbridge/intel/lynxpoint/usb_ehci.c +++ b/src/southbridge/intel/lynxpoint/usb_ehci.c @@ -8,6 +8,7 @@ #include <device/pci_ehci.h> #include <device/mmio.h> #include <device/pci_ops.h> +#include "iobp.h" #include "pch.h" #ifdef __SIMPLE_DEVICE__ diff --git a/src/southbridge/intel/lynxpoint/usb_xhci.c b/src/southbridge/intel/lynxpoint/usb_xhci.c index 5ab5a2c..fe72ebf 100644 --- a/src/southbridge/intel/lynxpoint/usb_xhci.c +++ b/src/southbridge/intel/lynxpoint/usb_xhci.c @@ -8,6 +8,7 @@ #include <device/mmio.h> #include <device/pci_ops.h> #include "chip.h" +#include "iobp.h" #include "pch.h" typedef struct southbridge_intel_lynxpoint_config config_t; -- To view, visit https://review.coreboot.org/c/coreboot/+/41946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb6114302cebe19bc3c1971929ea4fc085b454be Gerrit-Change-Number: 41946 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/sandybridge: Add comments to `struct iosav_ssq`
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44338 ) Change subject: nb/intel/sandybridge: Add comments to `struct iosav_ssq` ...................................................................... nb/intel/sandybridge: Add comments to `struct iosav_ssq` Add the ranges of bitfields as comments on the struct. Change-Id: Ib20a233806bfbdc9a81a77f4ef10f67a3cd2dc0e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit_common.h 1 file changed, 18 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/44338/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 3f31950..32f2b44 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -45,8 +45,8 @@ /* IOSAV_n_SP_CMD_CTRL */ union { struct { - u32 command : 16; - u32 ranksel_ap : 2; + u32 command : 16; /* [15.. 0] */ + u32 ranksel_ap : 2; /* [17..16] */ u32 : 14; }; u32 raw; @@ -55,13 +55,13 @@ /* IOSAV_n_SUBSEQ_CTRL */ union { struct { - u32 cmd_executions : 9; + u32 cmd_executions : 9; /* [ 8.. 0] */ u32 : 1; - u32 cmd_delay_gap : 5; + u32 cmd_delay_gap : 5; /* [14..10] */ u32 : 1; - u32 post_ssq_wait : 9; + u32 post_ssq_wait : 9; /* [24..16] */ u32 : 1; - u32 data_direction : 2; + u32 data_direction : 2; /* [27..26] */ u32 : 4; }; u32 raw; @@ -70,12 +70,12 @@ /* IOSAV_n_SP_CMD_ADDR */ union { struct { - u32 address : 16; - u32 rowbits : 3; + u32 address : 16; /* [15.. 0] */ + u32 rowbits : 3; /* [18..16] */ u32 : 1; - u32 bank : 3; + u32 bank : 3; /* [22..20] */ u32 : 1; - u32 rank : 2; + u32 rank : 2; /* [25..24] */ u32 : 6; }; u32 raw; @@ -84,14 +84,14 @@ /* IOSAV_n_ADDR_UPDATE */ union { struct { - u32 inc_addr_1 : 1; - u32 inc_addr_8 : 1; - u32 inc_bank : 1; - u32 inc_rank : 2; - u32 addr_wrap : 5; - u32 lfsr_upd : 2; - u32 upd_rate : 4; - u32 lfsr_xors : 2; + u32 inc_addr_1 : 1; /* [ 0.. 0] */ + u32 inc_addr_8 : 1; /* [ 1.. 1] */ + u32 inc_bank : 1; /* [ 2.. 2] */ + u32 inc_rank : 2; /* [ 4.. 3] */ + u32 addr_wrap : 5; /* [ 9.. 5] */ + u32 lfsr_upd : 2; /* [11..10] */ + u32 upd_rate : 4; /* [15..12] */ + u32 lfsr_xors : 2; /* [17..16] */ u32 : 14; }; u32 raw; -- To view, visit https://review.coreboot.org/c/coreboot/+/44338 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib20a233806bfbdc9a81a77f4ef10f67a3cd2dc0e Gerrit-Change-Number: 44338 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801jx/sata.c: Simplify constant is_mobile parameter
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44337 ) Change subject: sb/intel/i82801jx/sata.c: Simplify constant is_mobile parameter ...................................................................... sb/intel/i82801jx/sata.c: Simplify constant is_mobile parameter Tested with BUILD_TIMELESS=1, Intel DG43GT does not change. Change-Id: I30cdca0240afced2949639193caa2f11aca1c60d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801jx/sata.c 1 file changed, 15 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44337/1 diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index b3bed1e..fa56654 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -15,8 +15,7 @@ typedef struct southbridge_intel_i82801jx_config config_t; -static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map, - const int is_mobile) +static void sata_enable_ahci_mmap(struct device *const dev, const u8 port_map) { int i; u32 reg32; @@ -56,14 +55,12 @@ /* Lock R/WO bits in Port command registers. */ for (i = 0; i < 6; ++i) { - if (((i == 2) || (i == 3)) && is_mobile) - continue; u8 *addr = abar + 0x118 + (i * 0x80); write32(addr, read32(addr)); } } -static void sata_program_indexed(struct device *const dev, const int is_mobile) +static void sata_program_indexed(struct device *const dev) { u32 reg32; @@ -82,31 +79,25 @@ pci_write_config8(dev, D31F2_SIDX, 0x78); pci_write_config8(dev, D31F2_SDAT + 2, 0x22); - if (!is_mobile) { - pci_write_config8(dev, D31F2_SIDX, 0x84); - reg32 = pci_read_config32(dev, D31F2_SDAT); - reg32 &= ~((7 << 3) | (7 << 0)); - reg32 |= (3 << 3) | (3 << 0); - pci_write_config32(dev, D31F2_SDAT, reg32); - } + pci_write_config8(dev, D31F2_SIDX, 0x84); + reg32 = pci_read_config32(dev, D31F2_SDAT); + reg32 &= ~((7 << 3) | (7 << 0)); + reg32 |= (3 << 3) | (3 << 0); + pci_write_config32(dev, D31F2_SDAT, reg32); pci_write_config8(dev, D31F2_SIDX, 0x88); reg32 = pci_read_config32(dev, D31F2_SDAT); - if (!is_mobile) - reg32 &= ~((7 << 27) | (7 << 24) | (7 << 11) | (7 << 8)); - reg32 &= ~((7 << 19) | (7 << 16) | (7 << 3) | (7 << 0)); - if (!is_mobile) - reg32 |= (4 << 27) | (4 << 24) | (2 << 11) | (2 << 8); - reg32 |= (4 << 19) | (4 << 16) | (2 << 3) | (2 << 0); + reg32 &= ~((7 << 27) | (7 << 24) | (7 << 11) | (7 << 8)); + reg32 &= ~((7 << 19) | (7 << 16) | (7 << 3) | (7 << 0)); + reg32 |= (4 << 27) | (4 << 24) | (2 << 11) | (2 << 8); + reg32 |= (4 << 19) | (4 << 16) | (2 << 3) | (2 << 0); pci_write_config32(dev, D31F2_SDAT, reg32); pci_write_config8(dev, D31F2_SIDX, 0x8c); reg32 = pci_read_config32(dev, D31F2_SDAT); - if (!is_mobile) - reg32 &= ~((7 << 27) | (7 << 24)); + reg32 &= ~((7 << 27) | (7 << 24)); reg32 &= ~((7 << 19) | (7 << 16) | 0xffff); - if (!is_mobile) - reg32 |= (2 << 27) | (2 << 24); + reg32 |= (2 << 27) | (2 << 24); reg32 |= (2 << 19) | (2 << 16) | 0x00aa; pci_write_config32(dev, D31F2_SDAT, reg32); @@ -200,9 +191,9 @@ pci_write_config32(dev, 0x94, sclkcg); if (sata_mode == 0) - sata_enable_ahci_mmap(dev, config->sata_port_map, 0); + sata_enable_ahci_mmap(dev, config->sata_port_map); - sata_program_indexed(dev, 0); + sata_program_indexed(dev); } static void sata_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/44337 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I30cdca0240afced2949639193caa2f11aca1c60d Gerrit-Change-Number: 44337 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801jx/sata.c: Drop always-false is_mobile check
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44336 ) Change subject: sb/intel/i82801jx/sata.c: Drop always-false is_mobile check ...................................................................... sb/intel/i82801jx/sata.c: Drop always-false is_mobile check Also remove the meaningless `sata_traffic_monitor` devicetree option. Function parameters will be removed in a reproducible follow-up. Change-Id: I70cf1e06cc8ace504a22be9f9c4441e3070f9e29 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/dg43gt/devicetree.cb M src/southbridge/intel/i82801jx/chip.h M src/southbridge/intel/i82801jx/sata.c 3 files changed, 2 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/44336/1 diff --git a/src/mainboard/intel/dg43gt/devicetree.cb b/src/mainboard/intel/dg43gt/devicetree.cb index de2d71d..bb2456f 100644 --- a/src/mainboard/intel/dg43gt/devicetree.cb +++ b/src/mainboard/intel/dg43gt/devicetree.cb @@ -22,7 +22,6 @@ # Set AHCI mode. register "sata_port_map" = "0x1f" register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" # Enable PCIe ports 0,2,3 as slots. register "pcie_slot_implemented" = "0xb" diff --git a/src/southbridge/intel/i82801jx/chip.h b/src/southbridge/intel/i82801jx/chip.h index cdc1cc5..e9632d2 100644 --- a/src/southbridge/intel/i82801jx/chip.h +++ b/src/southbridge/intel/i82801jx/chip.h @@ -43,7 +43,6 @@ /* IDE configuration */ uint8_t sata_port_map : 6; int sata_clock_request : 1; - int sata_traffic_monitor : 1; int c4onc3_enable:1; int c5_enable : 1; diff --git a/src/southbridge/intel/i82801jx/sata.c b/src/southbridge/intel/i82801jx/sata.c index 0372460..b3bed1e 100644 --- a/src/southbridge/intel/i82801jx/sata.c +++ b/src/southbridge/intel/i82801jx/sata.c @@ -138,9 +138,6 @@ /* Get the chip configuration */ const config_t *const config = dev->chip_info; - - const u16 devid = pci_read_config16(dev, PCI_DEVICE_ID); - const int is_mobile = (devid == 0x2928) || (devid == 0x2929); u8 sata_mode; printk(BIOS_DEBUG, "i82801jx_sata: initializing...\n"); @@ -202,20 +199,10 @@ sclkcg |= 0x193; pci_write_config32(dev, 0x94, sclkcg); - if (is_mobile && config->sata_traffic_monitor) { - struct device *const lpc_dev = pcidev_on_root(0x1f, 0); - if (((pci_read_config8(lpc_dev, D31F0_CxSTATE_CNF) >> 3) & 3) == 3) { - u8 reg8 = pci_read_config8(dev, 0x9c); - reg8 &= ~(0x1f << 2); - reg8 |= 3 << 2; - pci_write_config8(dev, 0x9c, reg8); - } - } - if (sata_mode == 0) - sata_enable_ahci_mmap(dev, config->sata_port_map, is_mobile); + sata_enable_ahci_mmap(dev, config->sata_port_map, 0); - sata_program_indexed(dev, is_mobile); + sata_program_indexed(dev, 0); } static void sata_enable(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/44336 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I70cf1e06cc8ace504a22be9f9c4441e3070f9e29 Gerrit-Change-Number: 44336 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801jx: Drop is-mobile checks
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44335 ) Change subject: sb/intel/i82801jx: Drop is-mobile checks ...................................................................... sb/intel/i82801jx: Drop is-mobile checks There's no mobile ICH10 variant. This was copied from i82801ix. Change-Id: I141da407e336f6fbbf84d0e2cee55b0c12931c7b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801jx/i82801jx.c M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/i82801jx/lpc.c M src/southbridge/intel/i82801jx/thermal.c 4 files changed, 0 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/44335/1 diff --git a/src/southbridge/intel/i82801jx/i82801jx.c b/src/southbridge/intel/i82801jx/i82801jx.c index a332ec0..6f90301 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.c +++ b/src/southbridge/intel/i82801jx/i82801jx.c @@ -46,14 +46,6 @@ pci_write_config8(pciePort[i], 0x324, 0x40); } - if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) { - for (i = 0; i < 6; ++i) { - if (pciePort[i]->enabled) { - pci_or_config32(pciePort[i], 0xe8, 1); - } - } - } - for (i = 5; (i >= 0) && !pciePort[i]->enabled; --i) { /* Only for the top disabled ports. */ pci_or_config32(pciePort[i], 0x300, 0x3 << 16); diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 0a353de..b3cab91 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -169,12 +169,6 @@ #include <device/pci_ops.h> -static inline int lpc_is_mobile(const u16 devid) -{ - return (devid == 0x2917) || (devid == 0x2919); -} -#define LPC_IS_MOBILE(dev) lpc_is_mobile(pci_read_config16(dev, PCI_DEVICE_ID)) - void i82801jx_lpc_setup(void); void i82801jx_setup_bars(void); void i82801jx_early_init(void); diff --git a/src/southbridge/intel/i82801jx/lpc.c b/src/southbridge/intel/i82801jx/lpc.c index a8b5370..3bed5dd 100644 --- a/src/southbridge/intel/i82801jx/lpc.c +++ b/src/southbridge/intel/i82801jx/lpc.c @@ -276,19 +276,6 @@ outl(reg32, pmbase + 0x10); } -static void i82801jx_configure_cstates(struct device *dev) -{ - // Enable Popup & Popdown - pci_or_config8(dev, D31F0_CxSTATE_CNF, (1 << 4) | (1 << 3) | (1 << 2)); - - // Set Deeper Sleep configuration to recommended values - // Deeper Sleep to Stop CPU: 34-40us - // Deeper Sleep to Sleep: 15us - pci_update_config8(dev, D31F0_C4TIMING_CNT, ~0x0f, (2 << 2) | (2 << 0)); - - /* We could enable slow-C4 exit here, if someone needs it? */ -} - static void i82801jx_rtc_init(struct device *dev) { u8 reg8; @@ -376,10 +363,6 @@ /* Setup power options. */ i82801jx_power_options(dev); - /* Configure Cx state registers */ - if (LPC_IS_MOBILE(dev)) - i82801jx_configure_cstates(dev); - /* Initialize the real time clock. */ i82801jx_rtc_init(dev); diff --git a/src/southbridge/intel/i82801jx/thermal.c b/src/southbridge/intel/i82801jx/thermal.c index 41013a3..5fc9548 100644 --- a/src/southbridge/intel/i82801jx/thermal.c +++ b/src/southbridge/intel/i82801jx/thermal.c @@ -10,9 +10,6 @@ static void thermal_init(struct device *dev) { - if (LPC_IS_MOBILE(pcidev_on_root(0x1f, 0))) - return; - u8 reg8; pci_write_config32(dev, 0x10, (uintptr_t)DEFAULT_TBAR); -- To view, visit https://review.coreboot.org/c/coreboot/+/44335 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I141da407e336f6fbbf84d0e2cee55b0c12931c7b Gerrit-Change-Number: 44335 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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