coreboot-gerrit August 2020

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback.
by Caveh Jalali (Code Review) 13 Aug '20

13 Aug '20

Hello Shelley Chen, build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44430 to look at the new patch set (#2). Change subject: cse_lite: Move global reset after MRC writeback. ...................................................................... cse_lite: Move global reset after MRC writeback. With CSE-lite enabled, we were going through the lengthy memory training procedure twice on the initial power-on boot. This moves the global reset performed to achieve the CSE-lite RO to RW reboot to a later boot phase so that it happens after the memory training data has been written to the MRC cache. Now, the 2nd (and subsequent) reboot can utilize the memory training data established during the 1st boot. This reduces the first boot time by about 20s on a 16GB system. BUG=b:162021048 TEST=Booted on volteer, confirmed 20s faster boot time. Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44430/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: lib: Add ASan support to romstage on x86 arch
by Werner Zeh (Code Review) 13 Aug '20

13 Aug '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43604 ) Change subject: lib: Add ASan support to romstage on x86 arch ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/43604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381 Gerrit-Change-Number: 43604 Gerrit-PatchSet: 10 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 13 Aug 2020 08:18:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/clevo/n141cu: Add new Comet Lake mainboard
by Michael Niewöhner (Code Review) 13 Aug '20

13 Aug '20

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Change in coreboot[master]: mb/clevo/n141cu: Add new Comet Lake mainboard
by Michael Niewöhner (Code Review) 13 Aug '20

13 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40581 ) Change subject: mb/clevo/n141cu: Add new Comet Lake mainboard ...................................................................... Patch Set 36: (8 comments) https://review.coreboot.org/c/coreboot/+/40581/36/src/mainboard/clevo/cml-u… File src/mainboard/clevo/cml-u/variants/n141cu/devicetree.cb: https://review.coreboot.org/c/coreboot/+/40581/36/src/mainboard/clevo/cml-u… PS36, Line 3: todo: - i2c soc config (mainly touchpad) - touchpad - https://review.coreboot.org/c/coreboot/+/40581/36/src/mainboard/clevo/cml-u… PS36, Line 19: ptf_enable" = "0" : register "PmTimerDisabled" = "0" : register "s0ix_enable" = "0" disabled -> drop https://review.coreboot.org/c/coreboot/+/40581/36/src/mainboard/clevo/cml-u… PS36, Line 26: register "Device4Enable" = "0" should be enabled; we're still missing the devtree patches for cnl, so this can be dropped, when they have been added https://review.coreboot.org/c/coreboot/+/40581/36/src/mainboard/clevo/cml-u… PS36, Line 42: register "tcc_offset" = "12" woops.. really that much? https://review.coreboot.org/c/coreboot/+/40581/36/src/mainboard/clevo/cml-u… PS36, Line 79: register "SataMode" = "Sata_AHCI" could be dropped, since Sata_AHCI == 0 https://review.coreboot.org/c/coreboot/+/40581/36/src/mainboard/clevo/cml-u… PS36, Line 80: register "SataSalpSupport" = "0" drop if 0; but this could be enabled as well https://review.coreboot.org/c/coreboot/+/40581/36/src/mainboard/clevo/cml-u… PS36, Line 157: register "PchPmSlpS3MinAssert" = "3" # 50ms : register "PchPmSlpS4MinAssert" = "1" # 1s : register "PchPmSlpSusMinAssert" = "2" # 500ms : register "PchPmSlpAMinAssert" = "4" # 2s : use the right macros here https://review.coreboot.org/c/coreboot/+/40581/36/src/mainboard/clevo/cml-u… PS36, Line 167: register "AcousticNoiseMitigation" = "1" AcousticNoiseMitigation is not for HDA iirc -- To view, visit https://review.coreboot.org/c/coreboot/+/40581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 Gerrit-Change-Number: 40581 Gerrit-PatchSet: 36 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-Comment-Date: Thu, 13 Aug 2020 07:09:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/bd82x6x/me_8.x.c: Relocate `mkhi_end_of_post`
by Angel Pons (Code Review) 13 Aug '20

13 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44340 ) Change subject: sb/intel/bd82x6x/me_8.x.c: Relocate `mkhi_end_of_post` ...................................................................... sb/intel/bd82x6x/me_8.x.c: Relocate `mkhi_end_of_post` This reduces the differences between both ME source code files. Tested with BUILD_TIMELESS=1, Asus P8Z77-V LX2 does not change. Change-Id: I08e07ca2691bb854682692476153a98967bf05da Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/me_8.x.c 1 file changed, 27 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/44340/1 diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index ff94a88..73faa24 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -327,6 +327,33 @@ return 0; } +/* Send END OF POST message to the ME */ +static int __unused mkhi_end_of_post(void) +{ + struct mkhi_header mkhi = { + .group_id = MKHI_GROUP_ID_GEN, + .command = MKHI_END_OF_POST, + }; + struct mei_header mei = { + .is_complete = 1, + .host_address = MEI_HOST_ADDRESS, + .client_address = MEI_ADDRESS_MKHI, + .length = sizeof(mkhi), + }; + + u32 eop_ack; + + /* Send request and wait for response */ + printk(BIOS_NOTICE, "ME: %s\n", __func__); + if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { + printk(BIOS_ERR, "ME: END OF POST message failed\n"); + return -1; + } + + printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); + return 0; +} + static inline void print_cap(const char *name, int state) { printk(BIOS_DEBUG, "ME Capability: %-41s : %sabled\n", @@ -398,33 +425,6 @@ print_cap("Wireless LAN (WLAN)", cap->wlan); } -/* Send END OF POST message to the ME */ -static int __unused mkhi_end_of_post(void) -{ - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_GEN, - .command = MKHI_END_OF_POST, - }; - struct mei_header mei = { - .is_complete = 1, - .host_address = MEI_HOST_ADDRESS, - .client_address = MEI_ADDRESS_MKHI, - .length = sizeof(mkhi), - }; - - u32 eop_ack; - - /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __func__); - if (mei_sendrecv(&mei, &mkhi, NULL, &eop_ack, sizeof(eop_ack)) < 0) { - printk(BIOS_ERR, "ME: END OF POST message failed\n"); - return -1; - } - - printk(BIOS_INFO, "ME: END OF POST message successful (%d)\n", eop_ack); - return 0; -} - #ifdef __SIMPLE_DEVICE__ void intel_me8_finalize_smm(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/44340 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I08e07ca2691bb854682692476153a98967bf05da Gerrit-Change-Number: 44340 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: device/pci_rom: Fix rom_header structure
by Benjamin Doron (Code Review) 13 Aug '20

13 Aug '20

Benjamin Doron has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43071 ) Change subject: device/pci_rom: Fix rom_header structure ...................................................................... Abandoned Specification had changed -- To view, visit https://review.coreboot.org/c/coreboot/+/43071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad02da554cb249ccec78dbb2ff57f72ec6b98584 Gerrit-Change-Number: 43071 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: device/pci_rom: Fix rom_header structure
by Benjamin Doron (Code Review) 13 Aug '20

13 Aug '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43071 ) Change subject: device/pci_rom: Fix rom_header structure ...................................................................... Patch Set 4: > The latest PCI specification shows different values: http://fpga-faq.narod.ru/PCI_Rev_30.pdf Acknowledged, thanks. I didn't realise that the PCI(e) specifications were publically available. -- To view, visit https://review.coreboot.org/c/coreboot/+/43071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad02da554cb249ccec78dbb2ff57f72ec6b98584 Gerrit-Change-Number: 43071 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 13 Aug 2020 06:34:13 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: device/pci_rom: Fix rom_header structure
by Patrick Rudolph (Code Review) 13 Aug '20

13 Aug '20

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43071 ) Change subject: device/pci_rom: Fix rom_header structure ...................................................................... Patch Set 4: The latest PCI specification shows different values: http://fpga-faq.narod.ru/PCI_Rev_30.pdf -- To view, visit https://review.coreboot.org/c/coreboot/+/43071 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iad02da554cb249ccec78dbb2ff57f72ec6b98584 Gerrit-Change-Number: 43071 Gerrit-PatchSet: 4 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Thu, 13 Aug 2020 06:24:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/var/magalor: Generate SPD ID for supported parts
by Karthik Ramasubramanian (Code Review) 13 Aug '20

13 Aug '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43989 ) Change subject: mb/google/dedede/var/magalor: Generate SPD ID for supported parts ...................................................................... mb/google/dedede/var/magalor: Generate SPD ID for supported parts Add supported memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory part being added is: MT53E512M32D2NP-046 WT:E K4U6E3S4AA-MGCR H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A K4UBE3D4AA-MGCR BUG=None TEST=Build the magalor board. Change-Id: I7bb19d6d4a66e66fed0564592c803c2af1045b0c Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- A src/mainboard/google/dedede/variants/magalor/memory/Makefile.inc A src/mainboard/google/dedede/variants/magalor/memory/dram_id.generated.txt A src/mainboard/google/dedede/variants/magalor/memory/mem_list_variant.txt 3 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/43989/1 diff --git a/src/mainboard/google/dedede/variants/magalor/memory/Makefile.inc b/src/mainboard/google/dedede/variants/magalor/memory/Makefile.inc new file mode 100644 index 0000000..bab4f2a --- /dev/null +++ b/src/mainboard/google/dedede/variants/magalor/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE +SPD_SOURCES += spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A +SPD_SOURCES += spd-3.hex # ID = 2(0b0010) Parts = K4UBE3D4AA-MGCR diff --git a/src/mainboard/google/dedede/variants/magalor/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/magalor/memory/dram_id.generated.txt new file mode 100644 index 0000000..100c322 --- /dev/null +++ b/src/mainboard/google/dedede/variants/magalor/memory/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +MT53E512M32D2NP-046 WT:E 0 (0000) +K4U6E3S4AA-MGCR 0 (0000) +H9HCNNNBKMMLXR-NEE 0 (0000) +MT53E1G32D2NP-046 WT:A 1 (0001) +K4UBE3D4AA-MGCR 2 (0010) diff --git a/src/mainboard/google/dedede/variants/magalor/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/magalor/memory/mem_list_variant.txt new file mode 100644 index 0000000..f05a5af --- /dev/null +++ b/src/mainboard/google/dedede/variants/magalor/memory/mem_list_variant.txt @@ -0,0 +1,5 @@ +MT53E512M32D2NP-046 WT:E +K4U6E3S4AA-MGCR +H9HCNNNBKMMLXR-NEE +MT53E1G32D2NP-046 WT:A +K4UBE3D4AA-MGCR -- To view, visit https://review.coreboot.org/c/coreboot/+/43989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7bb19d6d4a66e66fed0564592c803c2af1045b0c Gerrit-Change-Number: 43989 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block: Stitch CSE blobs into FW_MAIN_X partitions
by Subrata Banik (Code Review) 13 Aug '20

13 Aug '20

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35406 ) Change subject: soc/intel/common/block: Stitch CSE blobs into FW_MAIN_X partitions ...................................................................... soc/intel/common/block: Stitch CSE blobs into FW_MAIN_X partitions Add Kconfig option for CSE me_rw blob path and stitch the me_rw blob into FW_MAIN_X partitions. BUG=b:145796136 Change-Id: I1d2908e9e16858c5f333e1b10b19d18b7ca27765 Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35406 Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/common/block/cse/Makefile.inc 2 files changed, 15 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Furquan Shaikh: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index b6f49c6..1cb7d35 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -31,3 +31,9 @@ default "me_rw" help CBFS entry name for Intel CSE CBFS RW blob + +config SOC_INTEL_CSE_RW_FILE + string "Intel CSE CBFS RW path and filename" + default "" + help + Intel CSE CBFS RW blob path and file name diff --git a/src/soc/intel/common/block/cse/Makefile.inc b/src/soc/intel/common/block/cse/Makefile.inc index 30ff66b..11cc3c2 100644 --- a/src/soc/intel/common/block/cse/Makefile.inc +++ b/src/soc/intel/common/block/cse/Makefile.inc @@ -3,3 +3,12 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_CSE) += cse.c ramstage-$(CONFIG_SOC_INTEL_CSE_LITE_SKU) += cse_lite.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HECI_DISABLE_IN_SMM) += disable_heci.c + +ifneq ($(CONFIG_SOC_INTEL_CSE_RW_FILE),"") +CSE_LITE_ME_RW = $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_CBFS_NAME)) +regions-for-file-$(CSE_LITE_ME_RW) = FW_MAIN_A,FW_MAIN_B +cbfs-files-y += $(CSE_LITE_ME_RW) +$(CSE_LITE_ME_RW)-file := $(call strip_quotes,$(CONFIG_SOC_INTEL_CSE_RW_FILE)) +$(CSE_LITE_ME_RW)-name := $(CSE_LITE_ME_RW) +$(CSE_LITE_ME_RW)-type := raw +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/35406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d2908e9e16858c5f333e1b10b19d18b7ca27765 Gerrit-Change-Number: 35406 Gerrit-PatchSet: 79 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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coreboot-gerrit August 2020