Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43604 )
Change subject: lib: Add ASan support to romstage on x86 arch
......................................................................
Patch Set 10: Code-Review+2
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Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40581 )
Change subject: mb/clevo/n141cu: Add new Comet Lake mainboard
......................................................................
Patch Set 36:
(1 comment)
https://review.coreboot.org/c/coreboot/+/40581/36//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/40581/36//COMMIT_MSG@36
PS36, Line 36: - Everything works as expected.
well, everything that has been tested ;) what about thunderbolt for example?
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Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43071 )
Change subject: device/pci_rom: Fix rom_header structure
......................................................................
Patch Set 4:
> The latest PCI specification shows different values: http://fpga-faq.narod.ru/PCI_Rev_30.pdf
Acknowledged, thanks. I didn't realise that the PCI(e) specifications were publically available.
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Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43071 )
Change subject: device/pci_rom: Fix rom_header structure
......................................................................
Patch Set 4:
The latest PCI specification shows different values: http://fpga-faq.narod.ru/PCI_Rev_30.pdf
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Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43989 )
Change subject: mb/google/dedede/var/magalor: Generate SPD ID for supported parts
......................................................................
mb/google/dedede/var/magalor: Generate SPD ID for supported parts
Add supported memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory part being added is:
MT53E512M32D2NP-046 WT:E
K4U6E3S4AA-MGCR
H9HCNNNBKMMLXR-NEE
MT53E1G32D2NP-046 WT:A
K4UBE3D4AA-MGCR
BUG=None
TEST=Build the magalor board.
Change-Id: I7bb19d6d4a66e66fed0564592c803c2af1045b0c
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
A src/mainboard/google/dedede/variants/magalor/memory/Makefile.inc
A src/mainboard/google/dedede/variants/magalor/memory/dram_id.generated.txt
A src/mainboard/google/dedede/variants/magalor/memory/mem_list_variant.txt
3 files changed, 18 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/43989/1
diff --git a/src/mainboard/google/dedede/variants/magalor/memory/Makefile.inc b/src/mainboard/google/dedede/variants/magalor/memory/Makefile.inc
new file mode 100644
index 0000000..bab4f2a
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/magalor/memory/Makefile.inc
@@ -0,0 +1,7 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+## This is an auto-generated file. Do not edit!!
+
+SPD_SOURCES =
+SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = MT53E512M32D2NP-046 WT:E, K4U6E3S4AA-MGCR, H9HCNNNBKMMLXR-NEE
+SPD_SOURCES += spd-4.hex # ID = 1(0b0001) Parts = MT53E1G32D2NP-046 WT:A
+SPD_SOURCES += spd-3.hex # ID = 2(0b0010) Parts = K4UBE3D4AA-MGCR
diff --git a/src/mainboard/google/dedede/variants/magalor/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/magalor/memory/dram_id.generated.txt
new file mode 100644
index 0000000..100c322
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/magalor/memory/dram_id.generated.txt
@@ -0,0 +1,6 @@
+DRAM Part Name ID to assign
+MT53E512M32D2NP-046 WT:E 0 (0000)
+K4U6E3S4AA-MGCR 0 (0000)
+H9HCNNNBKMMLXR-NEE 0 (0000)
+MT53E1G32D2NP-046 WT:A 1 (0001)
+K4UBE3D4AA-MGCR 2 (0010)
diff --git a/src/mainboard/google/dedede/variants/magalor/memory/mem_list_variant.txt b/src/mainboard/google/dedede/variants/magalor/memory/mem_list_variant.txt
new file mode 100644
index 0000000..f05a5af
--- /dev/null
+++ b/src/mainboard/google/dedede/variants/magalor/memory/mem_list_variant.txt
@@ -0,0 +1,5 @@
+MT53E512M32D2NP-046 WT:E
+K4U6E3S4AA-MGCR
+H9HCNNNBKMMLXR-NEE
+MT53E1G32D2NP-046 WT:A
+K4UBE3D4AA-MGCR
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Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43766 )
Change subject: security/vboot/Makefile.inc: Update regions-for-file function
......................................................................
security/vboot/Makefile.inc: Update regions-for-file function
This patch updates regions-for-file function in the
security/vboot/Makefile.inc to support addition of a CBFS file into
required FMAP REGIONs in a flexible manner. The file that needs to be
added to specific REGIONs, those regions list should be specified in the
regions-for-file-{CBFS_FILE_TO_BE_ADDED} variable.
For example, if a file foo.bin needs to be added in FW_MAIN_B and COREBOOT,
then below code needs to be added in a Makefile.inc.
regions-for-file-foo := FW_MAIN_B,COREBOOT
cbfs-file-y := foo
foo-file := foo.bin
foo-type := raw
TEST=Verified on hatch
Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com>
Change-Id: I1f5c22b3d9558ee3c5daa2781a115964f8d2d83b
---
M src/security/vboot/Makefile.inc
1 file changed, 3 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/43766/1
diff --git a/src/security/vboot/Makefile.inc b/src/security/vboot/Makefile.inc
index 90b2756..fe8e90b 100644
--- a/src/security/vboot/Makefile.inc
+++ b/src/security/vboot/Makefile.inc
@@ -171,6 +171,8 @@
# All other files will be installed into RO and RW regions
# Use $(sort) to cut down on extra spaces that would be translated to commas
regions-for-file = $(subst $(spc),$(comma),$(sort \
+ $(if $(value regions-for-file-$(1)), \
+ $(regions-for-file-$(1)), \
$(if $(filter \
$(if $(filter y,$(CONFIG_VBOOT_STARTS_IN_ROMSTAGE)), \
%/romstage,) \
@@ -194,7 +196,7 @@
$(if $(filter \
$(call strip_quotes,$(CONFIG_RW_REGION_ONLY)) \
,$(1)), $(RW_PARTITIONS), $(VBOOT_PARTITIONS) ) \
- )))))
+ ))))))
CONFIG_GBB_HWID := $(call strip_quotes,$(CONFIG_GBB_HWID))
CONFIG_GBB_BMPFV_FILE := $(call strip_quotes,$(CONFIG_GBB_BMPFV_FILE))
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