coreboot-gerrit August 2020

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Change in coreboot[master]: lib: Add ASan support to romstage on x86 arch
by Harshit Sharma (Code Review) 13 Aug '20

13 Aug '20

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43604 ) Change subject: lib: Add ASan support to romstage on x86 arch ...................................................................... Patch Set 10: (5 comments) https://review.coreboot.org/c/coreboot/+/43604/9/src/lib/asan.c File src/lib/asan.c: https://review.coreboot.org/c/coreboot/+/43604/9/src/lib/asan.c@27 PS9, Line 27: #else > This else means that every other stage beside romstage (not just the ramstage but verstage, bootbloc […] Done https://review.coreboot.org/c/coreboot/+/43604/9/src/lib/asan.c@38 PS9, Line 38: #else > Same here. Done https://review.coreboot.org/c/coreboot/+/43604/9/src/lib/asan.c@249 PS9, Line 249: #else > And here. Done https://review.coreboot.org/c/coreboot/+/43604/9/src/lib/asan.c@280 PS9, Line 280: #else > And here. Done https://review.coreboot.org/c/coreboot/+/43604/9/src/lib/asan.c@334 PS9, Line 334: #else > And here. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/43604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381 Gerrit-Change-Number: 43604 Gerrit-PatchSet: 10 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 13 Aug 2020 05:36:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add ASan support to romstage on x86 arch
by Harshit Sharma (Code Review) 13 Aug '20

13 Aug '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, Julius Werner, Werner Zeh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43604 to look at the new patch set (#10). Change subject: lib: Add ASan support to romstage on x86 arch ...................................................................... lib: Add ASan support to romstage on x86 arch This patch adds ASan support to romstage on x86 architecture. A Kconfig option is added to enable ASan in romstage. Compiler flags are updated. A memory space representing the shadow region is reserved in linker section. And a function call to asan_init() is added to initialize shadow region when romstage loads. Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381 Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> --- M src/Kconfig M src/arch/x86/assembly_entry.S M src/arch/x86/car.ld M src/include/symbols.h M src/lib/Makefile.inc M src/lib/asan.c 6 files changed, 66 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/43604/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/43604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381 Gerrit-Change-Number: 43604 Gerrit-PatchSet: 10 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/mediatek/mt8192: Add a stub implementation of the MT8192 SoC
by CK HU (Code Review) 13 Aug '20

13 Aug '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43962 ) Change subject: soc/mediatek/mt8192: Add a stub implementation of the MT8192 SoC ...................................................................... soc/mediatek/mt8192: Add a stub implementation of the MT8192 SoC Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: I2cf68805532f70f072b4e9a21ee61e2ebe4ebd9d --- A src/soc/mediatek/mt8192/Makefile.inc 1 file changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/43962/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc new file mode 100644 index 0000000..25574c9 --- /dev/null +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -0,0 +1,31 @@ +ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y) + +bootblock-y += ../common/gpio.c gpio.c +bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +bootblock-y += ../common/timer.c +bootblock-y += ../common/uart.c + +verstage-y += ../common/gpio.c gpio.c +verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +verstage-y += ../common/timer.c +verstage-y += ../common/uart.c + +romstage-y += ../common/cbmem.c +romstage-y += emi.c +romstage-y += ../common/gpio.c gpio.c +romstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +romstage-y += ../common/timer.c +romstage-y += ../common/uart.c + +ramstage-y += ../common/gpio.c gpio.c +ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += ../common/timer.c +ramstage-y += ../common/uart.c + +CPPFLAGS_common += -Isrc/soc/mediatek/mt8192/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/include + +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin + ./util/mtkheader/gen-bl-img.py mt8183 sf $< $@ + +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43962 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cf68805532f70f072b4e9a21ee61e2ebe4ebd9d Gerrit-Change-Number: 43962 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Add a dummy EMI driver
by CK HU (Code Review) 13 Aug '20

13 Aug '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43961 ) Change subject: soc/mediatek/mt8192: Add a dummy EMI driver ...................................................................... soc/mediatek/mt8192: Add a dummy EMI driver Add minimal function to report SDRAM size. Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: If74b6b52dd6e91d1ff40cf8460b6a03b2f3bb6f6 --- A src/soc/mediatek/mt8192/emi.c A src/soc/mediatek/mt8192/include/soc/emi.h 2 files changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/43961/1 diff --git a/src/soc/mediatek/mt8192/emi.c b/src/soc/mediatek/mt8192/emi.c new file mode 100644 index 0000000..7b1d3c2 --- /dev/null +++ b/src/soc/mediatek/mt8192/emi.c @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/emi.h> + +size_t sdram_size(void) +{ + size_t dram_size = 0x100000000; + + return dram_size; +} diff --git a/src/soc/mediatek/mt8192/include/soc/emi.h b/src/soc/mediatek/mt8192/include/soc/emi.h new file mode 100644 index 0000000..0348573 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/emi.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8192_EMI_H +#define SOC_MEDIATEK_MT8192_EMI_H + +#include <types.h> + +size_t sdram_size(void); + +#endif /* SOC_MEDIATEK_MT8192_EMI_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43961 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If74b6b52dd6e91d1ff40cf8460b6a03b2f3bb6f6 Gerrit-Change-Number: 43961 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Update PICASSO_FW_*_POSITION to match new layout
by Furquan Shaikh (Code Review) 13 Aug '20

13 Aug '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44425 ) Change subject: mb/google/zork: Update PICASSO_FW_*_POSITION to match new layout ...................................................................... mb/google/zork: Update PICASSO_FW_*_POSITION to match new layout CB:44362 ("mb/google/zork: Reorganize chromeos.fmd to increase WP_RO to 8MiB") updated the flash layout which moved RW_SECTION_A and RW_SECTION_B to different addresses than before. PICASSO_FW_A_POSITION and PICASSO_FW_B_POSITION configs need to be updated accordingly to retain the same behavior as before i.e. amdfw_a/b are placed at the start of FW_MAIN_A/B by placing them right after the CBFS header. This change fixes the value of PICASSO_FW_A_POSITION and PICASSO_FW_B_POSITION to maintain amdfw at the start of RW-A/B CBFS. BUG=b:161949925 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I177fb38af6380c36397d2a72d5ec00965087d528 --- M src/mainboard/google/zork/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/44425/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index bf2fe2e..1e1b790 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -129,7 +129,7 @@ config PICASSO_FW_A_POSITION hex - default 0xFF031040 + default 0xFF012040 depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK help Location of the AMD firmware in the RW_A region. This is the @@ -137,7 +137,7 @@ config PICASSO_FW_B_POSITION hex - default 0xFF3CF040 + default 0xFF312040 depends on VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK help Location of the AMD firmware in the RW_B region. This is the -- To view, visit https://review.coreboot.org/c/coreboot/+/44425 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I177fb38af6380c36397d2a72d5ec00965087d528 Gerrit-Change-Number: 44425 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback.
by Furquan Shaikh (Code Review) 13 Aug '20

13 Aug '20

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback. ...................................................................... Patch Set 1: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/44430/1/src/soc/intel/common/block… File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/44430/1/src/soc/intel/common/block… PS1, Line 657: #if CONFIG(SOC_INTEL_TIGERLAKE) It would be helpful to have a comment here explaining why this particular phase was chosen for Tigerlake. Once the MRC cache write is moved to happen early, this can be revisited. -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Aug 2020 03:32:46 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork: Disable ACP I2S wake for schematic version 3.6+
by Furquan Shaikh (Code Review) 13 Aug '20

13 Aug '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44403 ) Change subject: mb/google/zork: Disable ACP I2S wake for schematic version 3.6+ ...................................................................... mb/google/zork: Disable ACP I2S wake for schematic version 3.6+ Starting with v3.6 of reference schematics, headphone jack interrupt is moved to a standard GPIO instead of using CODEC_GPI. Thus, we no longer need I2S wake to be enabled in the ACP for boards using v3.6+ version of schematics. This change sets `acp_i2s_wake_enable` and `acp_pme_enable` to default 0 in baseboard devicetrees and overrides to 1 in update_hp_int_odl() if the board is still using older version of reference schematics. BUG=b:159934887 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I44b40db95b5148fe483c7340c5bd0d58627970a7 --- M src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb M src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb M src/mainboard/google/zork/variants/baseboard/ramstage_common.c 3 files changed, 12 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/44403/1 diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb index c60373b..dbb9266 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_dalboz.cb @@ -13,8 +13,8 @@ ACPI_FADT_REMOTE_POWER_ON" register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" - register "acp_i2s_wake_enable" = "1" - register "acpi_pme_enable" = "1" + register "acp_i2s_wake_enable" = "0" + register "acpi_pme_enable" = "0" # Start : OPN Performance Configuration # (Configuratin that is common for all variants) diff --git a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb index 6d26179..cb5c87a 100644 --- a/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb +++ b/src/mainboard/google/zork/variants/baseboard/devicetree_trembyle.cb @@ -13,8 +13,8 @@ ACPI_FADT_REMOTE_POWER_ON" register "acp_pin_cfg" = "I2S_PINS_I2S_TDM" - register "acp_i2s_wake_enable" = "1" - register "acpi_pme_enable" = "1" + register "acp_i2s_wake_enable" = "0" + register "acpi_pme_enable" = "0" # Start : OPN Performance Configuration # (Configuratin that is common for all variants) diff --git a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c index 1604588..679f98c 100644 --- a/src/mainboard/google/zork/variants/baseboard/ramstage_common.c +++ b/src/mainboard/google/zork/variants/baseboard/ramstage_common.c @@ -19,7 +19,6 @@ static void update_hp_int_odl(void) { - static const struct device_path rt5682_path[] = { { .type = DEVICE_PATH_PCI, @@ -44,6 +43,7 @@ const struct device *rt5682_dev; struct drivers_i2c_generic_config *cfg; struct acpi_gpio *gpio; + struct soc_amd_picasso_config *soc_cfg; if (!variant_uses_codec_gpi()) return; @@ -65,6 +65,13 @@ gpio = &cfg->irq_gpio; gpio->pins[0] = 62; + /* + * When using CODEC_GPI for headphone jack interrupt, ACP_PME_EN and ACP_I2S_WAKE_EN + * need to be set to trigger I2S_WAKE event for headphone jack. + */ + soc_cfg = config_of_soc(); + soc_cfg->acp_i2s_wake_enable = 1; + soc_cfg->acpi_pme_enable = 1; } static void update_dmic_gpio(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/44403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44b40db95b5148fe483c7340c5bd0d58627970a7 Gerrit-Change-Number: 44403 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0/ppi: Fill EFI_CPU_PHYSICAL_LOCATION structure in...
by Subrata Banik (Code Review) 13 Aug '20

13 Aug '20

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44390 ) Change subject: drivers/intel/fsp2_0/ppi: Fill EFI_CPU_PHYSICAL_LOCATION structure information ...................................................................... drivers/intel/fsp2_0/ppi: Fill EFI_CPU_PHYSICAL_LOCATION structure information Latest EDK2 code inside "UefiCpuPkg\Library\RegisterCpuFeaturesLib\CpuFeaturesInitialize.c" is now looking for EFI_CPU_PHYSICAL_LOCATION structure variables hence coreboot need to fill required informations (package, core and thread count). TEST=Able to see package, core and thread information as part of FSP debug log. Change-Id: Ieccf20a116d59aaafbbec3fe0adad9a48931cb59 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c 1 file changed, 11 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/44390/1 diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index 5b964d5..03184e1 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -10,6 +10,7 @@ #include <intelblocks/mp_init.h> #define BSP_CPU_SLOT 0 +#define SINGLE_CHIP_PACKAGE 0 static efi_return_status_t mp_get_number_of_processors(const efi_pei_services **ignored1, efi_pei_mp_services_ppi *ignored2, @@ -31,6 +32,8 @@ efi_uintn_t processor_number, efi_processor_information *processor_info_buffer) { + unsigned int num_virt_cores, num_phys_cores; + if (cpu_index() < 0) return FSP_DEVICE_ERROR; @@ -48,7 +51,14 @@ if (processor_number == BSP_CPU_SLOT) processor_info_buffer->StatusFlag |= PROCESSOR_AS_BSP_BIT; - /* TODO: Fill EFI_CPU_PHYSICAL_LOCATION structure information */ + /* Fill EFI_CPU_PHYSICAL_LOCATION structure information */ + cpu_read_topology(&num_phys_cores, &num_virt_cores); + + /* FSP will add one to the value in this Package field */ + processor_info_buffer->Location.Package = SINGLE_CHIP_PACKAGE; + processor_info_buffer->Location.Core = num_phys_cores; + processor_info_buffer->Location.Thread = num_virt_cores; + return FSP_SUCCESS; } -- To view, visit https://review.coreboot.org/c/coreboot/+/44390 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ieccf20a116d59aaafbbec3fe0adad9a48931cb59 Gerrit-Change-Number: 44390 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: add generic DDR4 SPDs for Eldrid
by Nick Vaccaro (Code Review) 13 Aug '20

13 Aug '20

Nick Vaccaro has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44432 ) Change subject: mb/google/volteer: add generic DDR4 SPDs for Eldrid ...................................................................... mb/google/volteer: add generic DDR4 SPDs for Eldrid Add Makefile.inc to include three generic DDR4 SPDs for the following parts for Eldrid: - H5AN8G6NDJR-XNC - MT40A512M16TB-062E:J - H5ANAG6NCMR-XNC Add mem_list_variant.txt as a manifest of eldrid's DRAM parts for use by gen_spd, the generic DD4 SPD generation tool. Add dram_id_generated.txt to specify DRAM ID strap settings. BUG=b:161772961 TEST=none Change-Id: I2c41052436c713b1c064af2356ccc19fdf83633d Signed-off-by: Nick Vaccaro <nvaccaro(a)google.com> --- A src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc A src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt A src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt 3 files changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/44432/1 diff --git a/src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc b/src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc new file mode 100644 index 0000000..a173d0f --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += spd-1.hex # ID = 0(0b0000) Parts = H5AN8G6NDJR-XNC +SPD_SOURCES += spd-2.hex # ID = 1(0b0001) Parts = MT40A512M16TB-062E:J +SPD_SOURCES += spd-3.hex # ID = 2(0b0010) Parts = H5ANAG6NCMR-XN diff --git a/src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt new file mode 100644 index 0000000..18e4232 --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/memory/dram_id.generated.txt @@ -0,0 +1,4 @@ +DRAM Part Name ID to assign +H5AN8G6NDJR-XNC 0 (0000) +MT40A512M16TB-062E:J 1 (0001) +H5ANAG6NCMR-XN 2 (0010) diff --git a/src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt new file mode 100644 index 0000000..ff0982d --- /dev/null +++ b/src/mainboard/google/volteer/variants/eldrid/memory/mem_list_variant.txt @@ -0,0 +1,4 @@ +H5AN8G6NDJR-XNC +MT40A512M16TB-062E:J +H5ANAG6NCMR-XN + -- To view, visit https://review.coreboot.org/c/coreboot/+/44432 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2c41052436c713b1c064af2356ccc19fdf83633d Gerrit-Change-Number: 44432 Gerrit-PatchSet: 1 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback.
by Caveh Jalali (Code Review) 13 Aug '20

13 Aug '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback. ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 13 Aug 2020 01:37:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2020