coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback.
by Caveh Jalali (Code Review) 13 Aug '20

13 Aug '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback. ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Comment-Date: Thu, 13 Aug 2020 01:37:25 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: trogdor: SoC makefile blob support
by Julius Werner (Code Review) 13 Aug '20

13 Aug '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35508 ) Change subject: trogdor: SoC makefile blob support ...................................................................... Patch Set 88: (1 comment) I guess this isn't going to compile until we uprev qc_blobs.git and we probably want to wait for CB:43204 to land before we do that. https://review.coreboot.org/c/coreboot/+/35508/86/src/soc/qualcomm/sc7180/M… File src/soc/qualcomm/sc7180/Makefile.inc: https://review.coreboot.org/c/coreboot/+/35508/86/src/soc/qualcomm/sc7180/M… PS86, Line 68: BL31_MAKEARGS += PLAT=sc7180 > Sorry we also need a […] *ping* What about this one? -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 88 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-Comment-Date: Thu, 13 Aug 2020 01:09:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer/*/gpio.c: add GPP_D16 to early_gpio_table
by Tim Wawrzynczak (Code Review) 12 Aug '20

12 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44117 ) Change subject: mb/google/volteer/*/gpio.c: add GPP_D16 to early_gpio_table ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf5e770f540e5d1e27b40f270bb004f4196bc7be Gerrit-Change-Number: 44117 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 12 Aug 2020 19:43:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/intel/tglrvp: Enable EC sync interrupt
by John Zhao (Code Review) 12 Aug '20

12 Aug '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44103 ) Change subject: mb/intel/tglrvp: Enable EC sync interrupt ...................................................................... mb/intel/tglrvp: Enable EC sync interrupt TGLRVP U/Y has GPP_A15 assigned to EC_HPD as EC_SYNC_IRQ. Configure this GPP_A15 gpio as active low and level interruptible. Enable EC sync interrupt configuration. BUG=None TEST=Booted to kernel and verified EC_SYNC_IRQ in the scope of CREC current resource settings. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: Idfe4d4e800866805ee8d758028ac7ddf4b259faa --- M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 4 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/44103/1 diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h index c018299..4303faf 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h @@ -56,6 +56,9 @@ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h index de0adf6..b61276c 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h @@ -12,4 +12,7 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_A15_IRQ + #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 4457506..9a4f0f7 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -54,6 +54,9 @@ /* CNVi */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */ + + /* EC_HPD */ + PAD_CFG_GPI_APIC(GPP_A15, NONE, PLTRST, LEVEL, INVERT), /* I2S4_SCLK */ }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 679933a..4e95d7f 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -51,6 +51,8 @@ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2S_MCLK2 */ + /* EC_HPD */ + PAD_CFG_GPI_APIC(GPP_A15, NONE, PLTRST, LEVEL, INVERT), /* I2S4_SCLK */ }; /* Early pad configuration in bootblock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idfe4d4e800866805ee8d758028ac7ddf4b259faa Gerrit-Change-Number: 44103 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/halvor: Update settings for WiFi/BT functions
by Frank Wu (Code Review) 12 Aug '20

12 Aug '20

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44372 ) Change subject: mb/google/volteer/halvor: Update settings for WiFi/BT functions ...................................................................... mb/google/volteer/halvor: Update settings for WiFi/BT functions Configure gpio/overridetree settings for WiFi/BT functions. Then WiFi/BT functions are enable on Halvor. BUG=b:153680359, b:163004808 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Verify that WiFi/BT can scan devices successfully. Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I085b192bb768c2c1238f3f857d315502ac10857e --- M src/mainboard/google/volteer/variants/halvor/gpio.c M src/mainboard/google/volteer/variants/halvor/overridetree.cb 2 files changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/44372/1 diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c index 2a98688..1cbe62d 100644 --- a/src/mainboard/google/volteer/variants/halvor/gpio.c +++ b/src/mainboard/google/volteer/variants/halvor/gpio.c @@ -23,6 +23,8 @@ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* A10 : I2S2_RXD ==> I2S1_RXD */ PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), /* A18 : DDSP_HPDB ==> NC */ PAD_NC(GPP_A18, NONE), /* A22 : DDPC_CTRLDATA ==> NC */ @@ -96,6 +98,8 @@ PAD_NC(GPP_F11, NONE), /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), /* F14 : GSXDIN ==> NC */ PAD_NC(GPP_F14, NONE), /* F15 : GSXSRESET# ==> NC */ diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index 12e059c..ef4ebb6 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -8,7 +8,7 @@ register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used register "usb2_ports[8]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used - register "usb2_ports[9]" = "USB2_PORT_EMPTY" # Type-A / Type-C Not Used + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Type-A / Type-C Not Used register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A / Type-C Port 0 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A / Type-C Port 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44372 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I085b192bb768c2c1238f3f857d315502ac10857e Gerrit-Change-Number: 44372 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: expose stop gpio for trembyle
by Aaron Durbin (Code Review) 12 Aug '20

12 Aug '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44254 ) Change subject: mb/google/zork: expose stop gpio for trembyle ...................................................................... mb/google/zork: expose stop gpio for trembyle In CB:43701 the trembyle touchscreen parameters were not updated to expose the stop gpio properly. BUG=b:162973325 Change-Id: I6f5da1c556ba1c6ccabf699491d3b635aa79f7c0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/mainboard/google/zork/variants/trembyle/overridetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/44254/1 diff --git a/src/mainboard/google/zork/variants/trembyle/overridetree.cb b/src/mainboard/google/zork/variants/trembyle/overridetree.cb index 26d9a3e..de038ac 100644 --- a/src/mainboard/google/zork/variants/trembyle/overridetree.cb +++ b/src/mainboard/google/zork/variants/trembyle/overridetree.cb @@ -75,6 +75,8 @@ # 32ms: Rise time of the reset line # 20ms: Firmware ready time register "reset_delay_ms" = "32 + 20" + register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_144)" + register "stop_off_delay_ms" = "1" register "has_power_resource" = "1" register "disable_gpio_export_in_crs" = "1" device i2c 39 on end -- To view, visit https://review.coreboot.org/c/coreboot/+/44254 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6f5da1c556ba1c6ccabf699491d3b635aa79f7c0 Gerrit-Change-Number: 44254 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/cannonlake: Modify CSE's PCI BAR address
by Sridhar Siricilla (Code Review) 12 Aug '20

12 Aug '20

Sridhar Siricilla has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44211 ) Change subject: soc/intel/cannonlake: Modify CSE's PCI BAR address ...................................................................... soc/intel/cannonlake: Modify CSE's PCI BAR address The patch modifies CSE's PCI BAR address to 0xfed1a000. Currently coreboot uses 0xfeda2000 as a PCI BAR address for CSE device while FSP-M uses 0xfed1a000. So, after FSP-M call, CSE's BAR address is overridden with 0xfed1a000. This causes HECI command transactions fail between FSP-M call and postcar. TEST=Verified sending HECI commands before and after FSP-M call on hatch. Signed-off-by: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c --- M src/soc/intel/cannonlake/include/soc/iomap.h 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/44211/1 diff --git a/src/soc/intel/cannonlake/include/soc/iomap.h b/src/soc/intel/cannonlake/include/soc/iomap.h index dc07089..9a58c65 100644 --- a/src/soc/intel/cannonlake/include/soc/iomap.h +++ b/src/soc/intel/cannonlake/include/soc/iomap.h @@ -52,7 +52,11 @@ #define GPIO_BASE_SIZE 0x10000 +#if CONFIG(SOC_INTEL_COMETLAKE) +#define HECI1_BASE_ADDRESS 0xfed1a000 +#else #define HECI1_BASE_ADDRESS 0xfeda2000 +#endif /* PTT registers */ #define PTT_TXT_BASE_ADDRESS 0xfed30800 -- To view, visit https://review.coreboot.org/c/coreboot/+/44211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I371cb658a96f5d580faff32ffab013cb6e6c492c Gerrit-Change-Number: 44211 Gerrit-PatchSet: 1 Gerrit-Owner: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Define stop_gpio for goodix touch screen
by Tim Wawrzynczak (Code Review) 12 Aug '20

12 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44356 ) Change subject: mb/google/volteer: Define stop_gpio for goodix touch screen ...................................................................... Patch Set 2: Code-Review+2 (1 comment) https://review.coreboot.org/c/coreboot/+/44356/1/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/volteer/overridetree.cb: https://review.coreboot.org/c/coreboot/+/44356/1/src/mainboard/google/volte… PS1, Line 93: 120 > no, i haven't tried to optimize these values. i'm not even sure […] Yeah, we had some issues with the goodix timing params in hatch... I don't know if it's the same panel or not. -- To view, visit https://review.coreboot.org/c/coreboot/+/44356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b Gerrit-Change-Number: 44356 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Mice Lin <mice_lin(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 12 Aug 2020 17:14:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Caveh Jalali <caveh(a)chromium.org> Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/dedede/variants/drawcia: add DTT support
by Sumeet R Pawnikar (Code Review) 12 Aug '20

12 Aug '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44148 ) Change subject: mb/google/dedede/variants/drawcia: add DTT support ...................................................................... mb/google/dedede/variants/drawcia: add DTT support Add DTT support on jasperlake based drawcia system. Add information on sensors, power limits and tcc_offset for DTT based thermal control. BRANCH=None BUG=None TEST=Built for dedede system Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/drawcia/overridetree.cb 1 file changed, 38 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44148/1 diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 78fec88..d355201 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -39,7 +39,45 @@ }, }" + register "tcc_offset" = "20" # TCC of 80C + device domain 0 on + device pci 04.0 on + chip drivers/intel/dptf + + register "options.tsr[0].desc" = ""Memory"" + register "options.tsr[1].desc" = ""Ambient"" + register "options.tsr[2].desc" = ""5V"" + register "options.tsr[3].desc" = ""Charger"" + + register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 80, 10000)" + register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 70, 60000)" + register "policies.passive[2]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 45, 15000)" + register "policies.passive[3]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 50, 15000)" + register "policies.passive[4]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 50, 15000)" + + register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 119, SHUTDOWN)" + register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 105, SHUTDOWN)" + register "policies.critical[2]" = "DPTF_CRITICAL(TEMP_SENSOR_1, 115, SHUTDOWN)" + register "policies.critical[3]" = "DPTF_CRITICAL(TEMP_SENSOR_2, 115, SHUTDOWN)" + register "policies.critical[4]" = "DPTF_CRITICAL(TEMP_SENSOR_3, 115, SHUTDOWN)" + + register "controls.power_limits.pl1" = "{ + .min_power = 3000, + .max_power = 6000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 200,}" + register "controls.power_limits.pl2" = "{ + .min_power = 6000, + .max_power = 20000, + .time_window_min = 1 * MSECS_PER_SEC, + .time_window_max = 1 * MSECS_PER_SEC, + .granularity = 1000,}" + + device generic 0 on end + end + end # SA Thermal device device pci 14.0 on chip drivers/usb/acpi device usb 0.0 on -- To view, visit https://review.coreboot.org/c/coreboot/+/44148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If50052864fb246a6a8f7d96fa50529e5f55968c0 Gerrit-Change-Number: 44148 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib: Add ASan support to romstage on x86 arch
by Werner Zeh (Code Review) 12 Aug '20

12 Aug '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43604 ) Change subject: lib: Add ASan support to romstage on x86 arch ...................................................................... Patch Set 9: Code-Review+1 (5 comments) https://review.coreboot.org/c/coreboot/+/43604/9/src/lib/asan.c File src/lib/asan.c: https://review.coreboot.org/c/coreboot/+/43604/9/src/lib/asan.c@27 PS9, Line 27: #else This else means that every other stage beside romstage (not just the ramstage but verstage, bootblock, ...) will use this path. I somehow would more like to have an #elif ENV_RAMSTAGE here instead to make sure that this will only be valid for the ramstage as you use linker symbols from the ramstage here. https://review.coreboot.org/c/coreboot/+/43604/9/src/lib/asan.c@38 PS9, Line 38: #else Same here. https://review.coreboot.org/c/coreboot/+/43604/9/src/lib/asan.c@249 PS9, Line 249: #else And here. https://review.coreboot.org/c/coreboot/+/43604/9/src/lib/asan.c@280 PS9, Line 280: #else And here. https://review.coreboot.org/c/coreboot/+/43604/9/src/lib/asan.c@334 PS9, Line 334: #else And here. -- To view, visit https://review.coreboot.org/c/coreboot/+/43604 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I67ebfb5e8d602e865b1f5c874860861ae4e54381 Gerrit-Change-Number: 43604 Gerrit-PatchSet: 9 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 12 Aug 2020 16:24:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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coreboot-gerrit August 2020