coreboot-gerrit August 2020

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Change in coreboot[master]: sb/intel/i82801ix/lpc.c: Align with i82801jx
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44334 ) Change subject: sb/intel/i82801ix/lpc.c: Align with i82801jx ...................................................................... sb/intel/i82801ix/lpc.c: Align with i82801jx Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I9445fac7db0a96b6a28ccf307f5ccedc1f94b8ab Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801ix/lpc.c 1 file changed, 2 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/44334/1 diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 6fe9bb9..ad7141a 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -97,7 +97,7 @@ */ for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { - u8 int_pin=0, int_line=0; + u8 int_pin = 0, int_line = 0; if (!irq_dev->enabled || irq_dev->path.type != DEVICE_PATH_PCI) continue; @@ -160,8 +160,7 @@ int nmi_option; /* BIOS must program... */ - reg32 = pci_read_config32(dev, 0xac); - pci_write_config32(dev, 0xac, reg32 | (1 << 30) | (3 << 8)); + pci_or_config32(dev, 0xac, (1 << 30) | (3 << 8)); /* Which state do we want to goto after g3 (power restored)? * 0 == S0 Full On @@ -477,7 +476,6 @@ } } - static const char *lpc_acpi_name(const struct device *dev) { return "LPCB"; -- To view, visit https://review.coreboot.org/c/coreboot/+/44334 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9445fac7db0a96b6a28ccf307f5ccedc1f94b8ab Gerrit-Change-Number: 44334 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801ix: Use macros for LPC_EN
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44333 ) Change subject: sb/intel/i82801ix: Use macros for LPC_EN ...................................................................... sb/intel/i82801ix: Use macros for LPC_EN Taken directly from i82801jx code. Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I0a5dc274e0058144e6e7f734c848b6b5962cba85 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801ix/early_init.c M src/southbridge/intel/i82801ix/i82801ix.h 2 files changed, 14 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/44333/1 diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 1054712..3c0f3ae 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -27,7 +27,10 @@ * - 0x200-0x207 GAMEL */ pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010); - pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f); + pci_write_config16(d31f0, D31F0_LPC_EN, CNF2_LPC_EN | CNF1_LPC_EN + | MC_LPC_EN | KBC_LPC_EN | GAMEH_LPC_EN + | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN + | COMB_LPC_EN | COMA_LPC_EN); /* Set up generic decode ranges */ if (!dev || !dev->chip_info) diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index ff94809c..3bd1d49 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -55,6 +55,16 @@ #define D31F0_PIRQH_ROUT 0x6b #define D31F0_LPC_IODEC 0x80 #define D31F0_LPC_EN 0x82 +#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */ +#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */ +#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */ +#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */ +#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */ +#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */ +#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */ +#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */ +#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */ +#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[2:0] */ #define D31F0_GEN1_DEC 0x84 #define D31F0_GEN2_DEC 0x88 #define D31F0_GEN3_DEC 0x8c -- To view, visit https://review.coreboot.org/c/coreboot/+/44333 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0a5dc274e0058144e6e7f734c848b6b5962cba85 Gerrit-Change-Number: 44333 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801jx/early_init.c: Drop double blank line
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44332 ) Change subject: sb/intel/i82801jx/early_init.c: Drop double blank line ...................................................................... sb/intel/i82801jx/early_init.c: Drop double blank line Change-Id: Ia37c5feb5a61793c10496a2d9cabb7661aa758b4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801jx/early_init.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/44332/1 diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index bfc5ca9..7714609 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -34,7 +34,6 @@ | GAMEL_LPC_EN | FDD_LPC_EN | LPT_LPC_EN | COMB_LPC_EN | COMA_LPC_EN); - /* Set up generic decode ranges */ if (!dev || !dev->chip_info) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/44332 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia37c5feb5a61793c10496a2d9cabb7661aa758b4 Gerrit-Change-Number: 44332 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801ix/early_init.c: Drop unnecessary initial value
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44331 ) Change subject: sb/intel/i82801ix/early_init.c: Drop unnecessary initial value ...................................................................... sb/intel/i82801ix/early_init.c: Drop unnecessary initial value Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: I17903dfe7b18a9244d0c102768dd153941f125a2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801ix/early_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/44331/1 diff --git a/src/southbridge/intel/i82801ix/early_init.c b/src/southbridge/intel/i82801ix/early_init.c index 86c1a53..1054712 100644 --- a/src/southbridge/intel/i82801ix/early_init.c +++ b/src/southbridge/intel/i82801ix/early_init.c @@ -11,7 +11,7 @@ { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); const struct device *dev = pcidev_on_root(0x1f, 0); - const struct southbridge_intel_i82801ix_config *config = NULL; + const struct southbridge_intel_i82801ix_config *config; /* Configure serial IRQs.*/ pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0); -- To view, visit https://review.coreboot.org/c/coreboot/+/44331 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I17903dfe7b18a9244d0c102768dd153941f125a2 Gerrit-Change-Number: 44331 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801ix/i82801ix.c: Align with i82801jx
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44330 ) Change subject: sb/intel/i82801ix/i82801ix.c: Align with i82801jx ...................................................................... sb/intel/i82801ix/i82801ix.c: Align with i82801jx Tested with BUILD_TIMELESS=1, Roda RK9 does not change. Change-Id: Icbb6cb45155991f9d4b3bcff37e1e9d99483acdc Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801ix/i82801ix.c 1 file changed, 2 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44330/1 diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 16d0520..846c9d8 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -35,7 +35,6 @@ { struct device *pciePort[6]; int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */ - u32 reg32; /* PCIe - BIOS must program... */ for (i = 0; i < 6; ++i) { @@ -44,8 +43,7 @@ printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); die(" is not listed in devicetree.\n"); } - reg32 = pci_read_config32(pciePort[i], 0x300); - pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); + pci_or_config32(pciePort[i], 0x300, 1 << 21); pci_write_config8(pciePort[i], 0x324, 0x40); } @@ -85,9 +83,8 @@ } /* Lock R/WO ASPM support bits. */ - for (i = 0; i < 6; ++i) { + for (i = 0; i < 6; ++i) pci_update_config32(pciePort[i], 0x4c, ~0, 0); - } } static void i82801ix_ehci_init(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/44330 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icbb6cb45155991f9d4b3bcff37e1e9d99483acdc Gerrit-Change-Number: 44330 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/bd82x6x: Remove incorrect RCBA registers
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44329 ) Change subject: sb/intel/bd82x6x: Remove incorrect RCBA registers ...................................................................... sb/intel/bd82x6x: Remove incorrect RCBA registers These were probably copy-pasted from some ICHx southbridge, and then some were corrected because native PCH init uses them. Delete the definitions which are unused and are invalid for this southbridge. Change-Id: I0be72f76c7fcc63316ae8566891e0732456a8c55 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pch.h 1 file changed, 0 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/44329/1 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 7552906..68f599d 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -229,26 +229,6 @@ #define CIR0 0x0050 /* 32bit */ #define TCLOCKDN (1u << 31) -#define RCTCL 0x0100 /* 32bit */ -#define ESD 0x0104 /* 32bit */ -#define ULD 0x0110 /* 32bit */ -#define ULBA 0x0118 /* 64bit */ - -#define RP1D 0x0120 /* 32bit */ -#define RP1BA 0x0128 /* 64bit */ -#define RP2D 0x0130 /* 32bit */ -#define RP2BA 0x0138 /* 64bit */ -#define RP3D 0x0140 /* 32bit */ -#define RP3BA 0x0148 /* 64bit */ -#define RP4D 0x0150 /* 32bit */ -#define RP4BA 0x0158 /* 64bit */ -#define HDD 0x0160 /* 32bit */ -#define HDBA 0x0168 /* 64bit */ -#define RP5D 0x0170 /* 32bit */ -#define RP5BA 0x0178 /* 64bit */ -#define RP6D 0x0180 /* 32bit */ -#define RP6BA 0x0188 /* 64bit */ - #define RPC 0x0400 /* 32bit */ #define RPFN 0x0404 /* 32bit */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0be72f76c7fcc63316ae8566891e0732456a8c55 Gerrit-Change-Number: 44329 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint: Remove incorrect RCBA registers
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44328 ) Change subject: sb/intel/lynxpoint: Remove incorrect RCBA registers ...................................................................... sb/intel/lynxpoint: Remove incorrect RCBA registers These were probably copy-pasted from some ICHx southbridge. However, datasheet shows that some of these are located elsewhere, and some others have disappeared completely. As they aren't in use, drop them. Change-Id: I2d09547bdbfd5f8f72ce3541347d9fec28630c79 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pch.h 1 file changed, 0 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44328/1 diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 893bfde..3d2616c 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -404,40 +404,6 @@ #define PMBASE 0x40 -#define VCH 0x0000 /* 32bit */ -#define VCAP1 0x0004 /* 32bit */ -#define VCAP2 0x0008 /* 32bit */ -#define PVC 0x000c /* 16bit */ -#define PVS 0x000e /* 16bit */ - -#define V0CAP 0x0010 /* 32bit */ -#define V0CTL 0x0014 /* 32bit */ -#define V0STS 0x001a /* 16bit */ - -#define V1CAP 0x001c /* 32bit */ -#define V1CTL 0x0020 /* 32bit */ -#define V1STS 0x0026 /* 16bit */ - -#define RCTCL 0x0100 /* 32bit */ -#define ESD 0x0104 /* 32bit */ -#define ULD 0x0110 /* 32bit */ -#define ULBA 0x0118 /* 64bit */ - -#define RP1D 0x0120 /* 32bit */ -#define RP1BA 0x0128 /* 64bit */ -#define RP2D 0x0130 /* 32bit */ -#define RP2BA 0x0138 /* 64bit */ -#define RP3D 0x0140 /* 32bit */ -#define RP3BA 0x0148 /* 64bit */ -#define RP4D 0x0150 /* 32bit */ -#define RP4BA 0x0158 /* 64bit */ -#define HDD 0x0160 /* 32bit */ -#define HDBA 0x0168 /* 64bit */ -#define RP5D 0x0170 /* 32bit */ -#define RP5BA 0x0178 /* 64bit */ -#define RP6D 0x0180 /* 32bit */ -#define RP6BA 0x0188 /* 64bit */ - #define RPC 0x0400 /* 32bit */ #define RPFN 0x0404 /* 32bit */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d09547bdbfd5f8f72ce3541347d9fec28630c79 Gerrit-Change-Number: 44328 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel: Remove inexistent references to IDE controller
by Angel Pons (Code Review) 12 Aug '20

12 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44327 ) Change subject: sb/intel: Remove inexistent references to IDE controller ...................................................................... sb/intel: Remove inexistent references to IDE controller This device doesn't exist on these southbridges. Change-Id: Ie17427ba044c465adf95300ff7f5610c25ae3373 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/ibexpeak/pch.h M src/southbridge/intel/lynxpoint/pch.h 3 files changed, 3 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/44327/1 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index b7842c0..7552906 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -155,8 +155,7 @@ #define LGMR 0x98 /* LPC Generic Memory Range */ #define BIOS_DEC_EN1 0xd8 /* BIOS Decode Enable */ -/* PCI Configuration Space (D31:F1): IDE */ -#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) +/* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define IDE_TIM_PRI 0x40 /* IDE timings, primary */ diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index 7c2e2a9..76d0ad6 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -148,8 +148,7 @@ #define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ -/* PCI Configuration Space (D31:F1): IDE */ -#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) +/* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 9946944..893bfde 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -212,8 +212,7 @@ #define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */ #define LGMR 0x98 /* LPC Generic Memory Range */ -/* PCI Configuration Space (D31:F1): IDE */ -#define PCH_IDE_DEV PCI_DEV(0, 0x1f, 1) +/* PCI Configuration Space (D31:F2): SATA */ #define PCH_SATA_DEV PCI_DEV(0, 0x1f, 2) #define PCH_SATA2_DEV PCI_DEV(0, 0x1f, 5) #define INTR_LN 0x3c -- To view, visit https://review.coreboot.org/c/coreboot/+/44327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie17427ba044c465adf95300ff7f5610c25ae3373 Gerrit-Change-Number: 44327 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer: Define stop_gpio for goodix touch screen
by Caveh Jalali (Code Review) 12 Aug '20

12 Aug '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44356 ) Change subject: mb/google/volteer: Define stop_gpio for goodix touch screen ...................................................................... Patch Set 2: (3 comments) https://review.coreboot.org/c/coreboot/+/44356/1//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44356/1//COMMIT_MSG@11 PS1, Line 11: defins > defines Done https://review.coreboot.org/c/coreboot/+/44356/1/src/mainboard/google/volte… File src/mainboard/google/volteer/variants/volteer/overridetree.cb: https://review.coreboot.org/c/coreboot/+/44356/1/src/mainboard/google/volte… PS1, Line 93: 120 > have you tried 10ms here? no, i haven't tried to optimize these values. i'm not even sure where they came from other than the likely copy-paste from other projects. i did find an interesting reference here: https://review.coreboot.org/c/coreboot/+/36655 which leads me to believe that we should not lightly tinker with these values. at this point, my touchscreen sample size is 1 and it's a loose panel. we should wait for a stable reference platform to do the tuning. https://review.coreboot.org/c/coreboot/+/44356/1/src/mainboard/google/volte… PS1, Line 98: 12 > same, have you tried 10 here? Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/44356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b Gerrit-Change-Number: 44356 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Mice Lin <mice_lin(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 12 Aug 2020 10:33:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Define stop_gpio for goodix touch screen
by Caveh Jalali (Code Review) 12 Aug '20

12 Aug '20

Hello build bot (Jenkins), Tim Wawrzynczak, Mice Lin, Nick Vaccaro, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44356 to look at the new patch set (#2). Change subject: mb/google/volteer: Define stop_gpio for goodix touch screen ...................................................................... mb/google/volteer: Define stop_gpio for goodix touch screen This applies to the goodix touch screen on both the volteer and volteer2 variants: Define GPP_E3 as the stop_gpio for the touch screen "Report_Switch" signal. Goodix defines a 1ms (minimum) delay after stop off. In addition, no longer drive this GPIO high by default as it is now controlled by the kernel through ACPI. BUG=b:153705232 TEST=touch screen still functional on volteer; confirmed timings with scope (VDD, RESET, REPORT_SWITCH) Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/mainboard/google/volteer/variants/volteer/gpio.c M src/mainboard/google/volteer/variants/volteer/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/gpio.c M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 4 files changed, 14 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/44356/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44356 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3ead9cf79812d08c4917be4585ed273050465a9b Gerrit-Change-Number: 44356 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Mice Lin <mice_lin(a)wistron.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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coreboot-gerrit August 2020