Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44330 )
Change subject: sb/intel/i82801ix/i82801ix.c: Align with i82801jx ......................................................................
sb/intel/i82801ix/i82801ix.c: Align with i82801jx
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Icbb6cb45155991f9d4b3bcff37e1e9d99483acdc Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/southbridge/intel/i82801ix/i82801ix.c 1 file changed, 2 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44330/1
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 16d0520..846c9d8 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -35,7 +35,6 @@ { struct device *pciePort[6]; int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */ - u32 reg32;
/* PCIe - BIOS must program... */ for (i = 0; i < 6; ++i) { @@ -44,8 +43,7 @@ printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); die(" is not listed in devicetree.\n"); } - reg32 = pci_read_config32(pciePort[i], 0x300); - pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); + pci_or_config32(pciePort[i], 0x300, 1 << 21); pci_write_config8(pciePort[i], 0x324, 0x40); }
@@ -85,9 +83,8 @@ }
/* Lock R/WO ASPM support bits. */ - for (i = 0; i < 6; ++i) { + for (i = 0; i < 6; ++i) pci_update_config32(pciePort[i], 0x4c, ~0, 0); - } }
static void i82801ix_ehci_init(void)
Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44330 )
Change subject: sb/intel/i82801ix/i82801ix.c: Align with i82801jx ......................................................................
Patch Set 1: Code-Review+2
Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44330 )
Change subject: sb/intel/i82801ix/i82801ix.c: Align with i82801jx ......................................................................
sb/intel/i82801ix/i82801ix.c: Align with i82801jx
Tested with BUILD_TIMELESS=1, Roda RK9 does not change.
Change-Id: Icbb6cb45155991f9d4b3bcff37e1e9d99483acdc Signed-off-by: Angel Pons th3fanbus@gmail.com Reviewed-on: https://review.coreboot.org/c/coreboot/+/44330 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Arthur Heymans arthur@aheymans.xyz --- M src/southbridge/intel/i82801ix/i82801ix.c 1 file changed, 2 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved
diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 16d0520..846c9d8 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -35,7 +35,6 @@ { struct device *pciePort[6]; int i, slot_number = 1; /* Reserve slot number 0 for nb's PEG. */ - u32 reg32;
/* PCIe - BIOS must program... */ for (i = 0; i < 6; ++i) { @@ -44,8 +43,7 @@ printk(BIOS_EMERG, "PCIe port 00:1c.%x", i); die(" is not listed in devicetree.\n"); } - reg32 = pci_read_config32(pciePort[i], 0x300); - pci_write_config32(pciePort[i], 0x300, reg32 | (1 << 21)); + pci_or_config32(pciePort[i], 0x300, 1 << 21); pci_write_config8(pciePort[i], 0x324, 0x40); }
@@ -85,9 +83,8 @@ }
/* Lock R/WO ASPM support bits. */ - for (i = 0; i < 6; ++i) { + for (i = 0; i < 6; ++i) pci_update_config32(pciePort[i], 0x4c, ~0, 0); - } }
static void i82801ix_ehci_init(void)
-
Angel Pons (Code Review) -
Arthur Heymans (Code Review)