coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/jasperlake: Add new IGD Device ID
by Aamir Bohra (Code Review) 13 Aug '20

13 Aug '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44000 ) Change subject: soc/intel/jasperlake: Add new IGD Device ID ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab3ba286f36afbf9533ac3cc62891fa390ca2441 Gerrit-Change-Number: 44000 Gerrit-PatchSet: 2 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Comment-Date: Thu, 13 Aug 2020 13:35:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/gm45/early_reset.c: Remove unused <types.h>
by HAOUAS Elyes (Code Review) 13 Aug '20

13 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44440 ) Change subject: nb/intel/gm45/early_reset.c: Remove unused <types.h> ...................................................................... nb/intel/gm45/early_reset.c: Remove unused <types.h> Change-Id: I8cadd27bc27239ee41dde5f91814f06d71b13a4a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/gm45/early_reset.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/44440/1 diff --git a/src/northbridge/intel/gm45/early_reset.c b/src/northbridge/intel/gm45/early_reset.c index 1783880..4fd25ad 100644 --- a/src/northbridge/intel/gm45/early_reset.c +++ b/src/northbridge/intel/gm45/early_reset.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <types.h> #include <cf9_reset.h> #include <device/pci_ops.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/44440 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8cadd27bc27239ee41dde5f91814f06d71b13a4a Gerrit-Change-Number: 44440 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP ES processor
by Jonathan Zhang (Code Review) 13 Aug '20

13 Aug '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44357 ) Change subject: soc/intel/xeon_sp/cpx: add CPUID for CPX-SP ES processor ...................................................................... soc/intel/xeon_sp/cpx: add CPUID for CPX-SP ES processor Add CPUID for CPX-SP ES processor. DeltaLake DVT server uses CPX-SP ES processor. TESTED=booted DeltaLake DVT server to target OS. [root@localhost ~]# dmidecode -t 1 Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x0001, DMI type 1, 27 bytes System Information Manufacturer: Wiwynn Product Name: Delta Lake DVT Version: YoDL03 Serial Number: BZA02200122N01A UUID: 000A0A22-2C29-1ED6-8259-000055DA2BFF Wake-up Type: Reserved SKU Number: Not Specified Family: DeltaLake Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ic8975f6bf752fd685b38b2d1f0a4da41983b57f6 --- M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 2 files changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/44357/1 diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index cf903b8..f485b72 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -100,6 +100,7 @@ static const struct cpu_device_id cpu_table[] = { {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_A0}, + {X86_VENDOR_INTEL, CPUID_COOPERLAKE_SP_ES}, {0, 0}, }; diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 1458000..e1c0171 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -7,6 +7,7 @@ #include <cpu/x86/msr.h> #define CPUID_COOPERLAKE_SP_A0 0x05065a +#define CPUID_COOPERLAKE_SP_ES 0x05065b /* CPU bus clock is fixed at 100MHz */ #define CPU_BCLK 100 -- To view, visit https://review.coreboot.org/c/coreboot/+/44357 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic8975f6bf752fd685b38b2d1f0a4da41983b57f6 Gerrit-Change-Number: 44357 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: xeon_sp/cpx: Enable ACPI P-state support
by Angel Pons (Code Review) 13 Aug '20

13 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44404 ) Change subject: xeon_sp/cpx: Enable ACPI P-state support ...................................................................... Patch Set 4: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/44404/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44404/4//COMMIT_MSG@9 PS4, Line 9: Implement ACPI P-state support to enable driver acpi_cpufreq : This patch leverages code from the Skylake project Missing period at the end of these two sentences -- To view, visit https://review.coreboot.org/c/coreboot/+/44404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc Gerrit-Change-Number: 44404 Gerrit-PatchSet: 4 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 13 Aug 2020 11:40:25 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: Revert "mb/google/asurada: Add new MT8192 mainboard "Asurada""
by HAOUAS Elyes (Code Review) 13 Aug '20

13 Aug '20

Hello Hung-Te Lin, build bot (Jenkins), Patrick Georgi, Martin Roth, Julius Werner, CK HU, Yu-Ping Wu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43081 to review the following change. Change subject: Revert "mb/google/asurada: Add new MT8192 mainboard "Asurada"" ...................................................................... Revert "mb/google/asurada: Add new MT8192 mainboard "Asurada"" This reverts commit 02bab4ddcfe09c0cbbc82ece6c9575f573e8d799. Reason for revert: UNSTABLE Change-Id: Ib85c66c995eb82b228443f9513c8e696d2fe7d4c --- D src/mainboard/google/asurada/Kconfig D src/mainboard/google/asurada/Kconfig.name D src/mainboard/google/asurada/Makefile.inc D src/mainboard/google/asurada/board_info.txt D src/mainboard/google/asurada/boardid.c D src/mainboard/google/asurada/bootblock.c D src/mainboard/google/asurada/chromeos.c D src/mainboard/google/asurada/chromeos.fmd D src/mainboard/google/asurada/devicetree.cb D src/mainboard/google/asurada/mainboard.c D src/mainboard/google/asurada/memlayout.ld D src/mainboard/google/asurada/reset.c 12 files changed, 0 insertions(+), 198 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/43081/1 diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig deleted file mode 100644 index e1c96f0..0000000 --- a/src/mainboard/google/asurada/Kconfig +++ /dev/null @@ -1,52 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -# Umbrella option to be selected by variant boards. -config BOARD_GOOGLE_ASURADA_COMMON - def_bool n - -if BOARD_GOOGLE_ASURADA_COMMON - -config VBOOT - select EC_GOOGLE_CHROMEEC_SWITCHES - select VBOOT_VBNV_FLASH - -config BOARD_SPECIFIC_OPTIONS - def_bool y - select BOOTBLOCK_CONSOLE - select SOC_MEDIATEK_MT8192 - select BOARD_ROMSIZE_KB_8192 - select MAINBOARD_HAS_CHROMEOS - select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS - select COMMON_CBFS_SPI_WRAPPER - select SPI_FLASH - select SPI_FLASH_INCLUDE_ALL_DRIVERS - select EC_GOOGLE_CHROMEEC - select EC_GOOGLE_CHROMEEC_BOARDID - select EC_GOOGLE_CHROMEEC_SPI - select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT - select MAINBOARD_HAS_TPM2 if VBOOT - select MAINBOARD_HAS_NATIVE_VGA_INIT - select MAINBOARD_FORCE_NATIVE_VGA_INIT - select HAVE_LINEAR_FRAMEBUFFER - -config MAINBOARD_DIR - string - default "google/asurada" - -config MAINBOARD_PART_NUMBER - string - default "Asurada" if BOARD_GOOGLE_ASURADA - -config DRIVER_TPM_SPI_BUS - hex - default 0x0 - -config BOOT_DEVICE_SPI_FLASH_BUS - int - default 1 - -config EC_GOOGLE_CHROMEEC_SPI_BUS - hex - default 0x2 - -endif diff --git a/src/mainboard/google/asurada/Kconfig.name b/src/mainboard/google/asurada/Kconfig.name deleted file mode 100644 index df3dc24..0000000 --- a/src/mainboard/google/asurada/Kconfig.name +++ /dev/null @@ -1,5 +0,0 @@ -comment "Asurada" - -config BOARD_GOOGLE_ASURADA - bool "-> Asurada" - select BOARD_GOOGLE_ASURADA_COMMON diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc deleted file mode 100644 index 3f5968a..0000000 --- a/src/mainboard/google/asurada/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -bootblock-y += memlayout.ld -bootblock-y += bootblock.c - -verstage-y += memlayout.ld -verstage-y += reset.c - -romstage-y += memlayout.ld -romstage-y += boardid.c - -ramstage-y += memlayout.ld -ramstage-y += boardid.c -ramstage-y += chromeos.c -ramstage-y += mainboard.c -ramstage-y += reset.c diff --git a/src/mainboard/google/asurada/board_info.txt b/src/mainboard/google/asurada/board_info.txt deleted file mode 100644 index b8059ad..0000000 --- a/src/mainboard/google/asurada/board_info.txt +++ /dev/null @@ -1,6 +0,0 @@ -Vendor name: Google -Board name: Asurada MediaTek MT8192 reference board -Category: eval -ROM protocol: SPI -ROM socketed: n -Flashrom support: y diff --git a/src/mainboard/google/asurada/boardid.c b/src/mainboard/google/asurada/boardid.c deleted file mode 100644 index 2c8efcd..0000000 --- a/src/mainboard/google/asurada/boardid.c +++ /dev/null @@ -1,15 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <boardid.h> - -/* board_id is provided by ec/google/chromeec/ec_boardid.c */ - -uint32_t sku_id(void) -{ - return 0; -} - -uint32_t ram_code(void) -{ - return 0; -} diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c deleted file mode 100644 index 5dcae8c..0000000 --- a/src/mainboard/google/asurada/bootblock.c +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootblock_common.h> - -void bootblock_mainboard_init(void) -{ -} diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c deleted file mode 100644 index 8f9fa53..0000000 --- a/src/mainboard/google/asurada/chromeos.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <bootmode.h> -#include <boot/coreboot_tables.h> -#include <gpio.h> -#include <security/tpm/tis.h> - -void fill_lb_gpios(struct lb_gpios *gpios) -{ -} - -int get_write_protect_state(void) -{ - return 0; -} - -int tis_plat_irq_status(void) -{ - return 0; -} diff --git a/src/mainboard/google/asurada/chromeos.fmd b/src/mainboard/google/asurada/chromeos.fmd deleted file mode 100644 index 2635854..0000000 --- a/src/mainboard/google/asurada/chromeos.fmd +++ /dev/null @@ -1,45 +0,0 @@ -# Firmware Layout Description for Chrome OS. -# -# The size and address of every section must be aligned to at least 4K, except: -# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. -# -# 'FMAP' may be found by binary search so its starting address should be better -# aligned to larger values. -# -# For sections to be preserved on update, add (PRESERVE) to individual sections -# instead of a group section; otherwise the preserved data may be wrong if you -# resize or reorder sections inside a group. - -FLASH@0x0 8M { - WP_RO@0x0 4M { - RO_SECTION { - BOOTBLOCK 128K - FMAP 4K - COREBOOT(CBFS) - GBB 0x2f00 - RO_FRID 0x100 - } - RO_VPD(PRESERVE) 32K # At least 16K. - } - RW_SECTION_A 1500K { - VBLOCK_A 8K - FW_MAIN_A(CBFS) - RW_FWID_A 0x100 - } - RW_MISC 36K { - RW_VPD(PRESERVE) 16K # At least 8K. - RW_NVRAM(PRESERVE) 8K - RW_DDR_TRAINING(PRESERVE) 8K - RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. - } - RW_SECTION_B 1500K { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 0x100 - } - RW_SHARED 36K { # Will be force updated on recovery. - SHARED_DATA 4K # 4K or less for netboot params. - RW_UNUSED - } - RW_LEGACY(CBFS) 1M # Minimal 1M. -} diff --git a/src/mainboard/google/asurada/devicetree.cb b/src/mainboard/google/asurada/devicetree.cb deleted file mode 100644 index 0bdeec2..0000000 --- a/src/mainboard/google/asurada/devicetree.cb +++ /dev/null @@ -1,7 +0,0 @@ -## SPDX-License-Identifier: GPL-2.0-only - -chip soc/mediatek/mt8192 - device cpu_cluster 0 on - device cpu 0 on end - end -end diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c deleted file mode 100644 index e6040fa..0000000 --- a/src/mainboard/google/asurada/mainboard.c +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/device.h> - -static void mainboard_init(struct device *dev) -{ -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = &mainboard_init; -} - -struct chip_operations mainboard_ops = { - .name = CONFIG_MAINBOARD_PART_NUMBER, - .enable_dev = mainboard_enable, -}; diff --git a/src/mainboard/google/asurada/memlayout.ld b/src/mainboard/google/asurada/memlayout.ld deleted file mode 100644 index 0f1fcec..0000000 --- a/src/mainboard/google/asurada/memlayout.ld +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <soc/memlayout.ld> diff --git a/src/mainboard/google/asurada/reset.c b/src/mainboard/google/asurada/reset.c deleted file mode 100644 index 3a97ee5..0000000 --- a/src/mainboard/google/asurada/reset.c +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <reset.h> - -void do_board_reset(void) -{ -} -- To view, visit https://review.coreboot.org/c/coreboot/+/43081 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib85c66c995eb82b228443f9513c8e696d2fe7d4c Gerrit-Change-Number: 43081 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/halvor: Update dq/dqs mappings
by Frank Wu (Code Review) 13 Aug '20

13 Aug '20

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44284 ) Change subject: mb/google/volteer/var/halvor: Update dq/dqs mappings ...................................................................... mb/google/volteer/var/halvor: Update dq/dqs mappings Update dq/dqs mappings based on halvor schematics. BUG=b:162892573 BRANCH=none TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Then boot Halvor successfully. Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: Id4ffcbd4f015afe6507ed2b1d562519c5b240409 --- M src/mainboard/google/volteer/variants/halvor/Makefile.inc A src/mainboard/google/volteer/variants/halvor/memory.c 2 files changed, 67 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/44284/1 diff --git a/src/mainboard/google/volteer/variants/halvor/Makefile.inc b/src/mainboard/google/volteer/variants/halvor/Makefile.inc index 13269db..b0bfc56 100644 --- a/src/mainboard/google/volteer/variants/halvor/Makefile.inc +++ b/src/mainboard/google/volteer/variants/halvor/Makefile.inc @@ -2,4 +2,6 @@ bootblock-y += gpio.c +romstage-y += memory.c + ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/halvor/memory.c b/src/mainboard/google/volteer/variants/halvor/memory.c new file mode 100644 index 0000000..edbb681 --- /dev/null +++ b/src/mainboard/google/volteer/variants/halvor/memory.c @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +static const struct lpddr4x_cfg halvor_memcfg = { + /* DQ byte map */ + .dq_map = { + [0] = { + { 10, 12, 13, 9, 11, 8, 15, 14,}, /* DDR0_DQ0[7:0] */ + { 3, 0, 1, 5, 4, 7, 6, 2 }, /* DDR0_DQ1[7:0] */ + }, + [1] = { + { 8, 10, 13, 9, 12, 15, 11, 14, }, /* DDR1_DQ0[7:0] */ + { 3, 5, 7, 2, 1, 0, 4, 6 }, /* DDR1_DQ1[7:0] */ + }, + [2] = { + { 1, 3, 0, 2, 5, 4, 7, 6, }, /* DDR2_DQ0[7:0] */ + { 15, 14, 12, 13, 8, 9, 10, 11 }, /* DDR2_DQ1[7:0] */ + }, + [3] = { + { 8, 9, 10, 11, 14, 12, 15, 13, }, /* DDR3_DQ0[7:0] */ + { 5, 6, 7, 4, 2, 3, 1, 0 }, /* DDR3_DQ1[7:0] */ + }, + [4] = { + { 9, 8, 10, 11, 12, 13, 14, 15, }, /* DDR4_DQ0[7:0] */ + { 6, 7, 4, 5, 0, 2, 1, 3 }, /* DDR4_DQ1[7:0] */ + }, + [5] = { + { 0, 1, 3, 2, 7, 4, 5, 6, }, /* DDR5_DQ0[7:0] */ + { 15, 14, 9, 12, 8, 13, 11, 10 }, /* DDR5_DQ1[7:0] */ + }, + [6] = { + { 7, 5, 3, 6, 1, 0, 4, 2, }, /* DDR6_DQ0[7:0] */ + { 12, 14, 15, 13, 8, 11, 9, 10 }, /* DDR6_DQ1[7:0] */ + }, + [7] = { + { 3, 7, 1, 6, 5, 4, 2, 0, }, /* DDR7_DQ0[7:0] */ + { 12, 11, 8, 14, 10, 9, 15, 13 }, /* DDR7_DQ1[7:0] */ + }, + }, + + /* DQS CPU<>DRAM map */ + .dqs_map = { + [0] = { 1, 0 }, /* DDR0_DQS[1:0] */ + [1] = { 1, 0 }, /* DDR1_DQS[1:0] */ + [2] = { 0, 1 }, /* DDR2_DQS[1:0] */ + [3] = { 1, 0 }, /* DDR3_DQS[1:0] */ + [4] = { 1, 0 }, /* DDR4_DQS[1:0] */ + [5] = { 0, 1 }, /* DDR5_DQS[1:0] */ + [6] = { 0, 1 }, /* DDR6_DQS[1:0] */ + [7] = { 0, 1 }, /* DDR7_DQS[1:0] */ + }, + + .ect = 1, /* Enable Early Command Training */ +}; + +static const struct ddr_memory_cfg board_memcfg = { + .mem_type = MEMTYPE_LPDDR4X, + .lpddr4_cfg = &halvor_memcfg +}; + +const struct ddr_memory_cfg *variant_memory_params(void) +{ + return &board_memcfg; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44284 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id4ffcbd4f015afe6507ed2b1d562519c5b240409 Gerrit-Change-Number: 44284 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/halvor: Enable cardreader function on Halvor
by Frank Wu (Code Review) 13 Aug '20

13 Aug '20

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44169 ) Change subject: mb/google/volteer/halvor: Enable cardreader function on Halvor ...................................................................... mb/google/volteer/halvor: Enable cardreader function on Halvor Configure gpio settings for enabling cardreader function. BUG=b:153680359 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Verify that the sd card is mount on /dev/mmcblk0 successfully. Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: I51752f47bc8d31d3a11da728ce00ca754381fde9 --- M src/mainboard/google/volteer/variants/halvor/gpio.c 1 file changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/44169/1 diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c index 2a98688..50506d0 100644 --- a/src/mainboard/google/volteer/variants/halvor/gpio.c +++ b/src/mainboard/google/volteer/variants/halvor/gpio.c @@ -56,6 +56,8 @@ /* D7 : SRCCLKREQ2# ==> NC */ PAD_NC(GPP_D7, NONE), + /* D8 : SRCCLKREQ3# ==> SD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* D9 : ISH_SPI_CS# ==> TBT_LSX2_TXD */ PAD_CFG_NF(GPP_D9, NONE, DEEP, NF4), /* D10 : ISH_SPI_CLK ==> TBT_LSX2_RXD */ @@ -64,6 +66,8 @@ PAD_NC(GPP_D11, NONE), /* D12 : ISH_SPI_MOSI ==> NC */ PAD_NC(GPP_D12, NONE), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), /* E0 : SATAXPCIE0 ==> NC */ PAD_NC(GPP_E0, NONE), @@ -75,6 +79,8 @@ PAD_NC(GPP_E5, NONE), /* E10 : SPI1_CS# ==> NC */ PAD_NC(GPP_E10, NONE), + /* E11 : SPI1_CLK ==> SD_PE_WAKE_ODL */ + PAD_CFG_GPI(GPP_E11, NONE, DEEP), /* E12 : SPI1_MISO_IO1 ==> NC */ PAD_NC(GPP_E12, NONE), /* E13 : SPI1_MOSI_IO0 ==> NC */ @@ -109,6 +115,8 @@ /* F19 : SRCCLKREQ6# ==> NC */ PAD_NC(GPP_F19, NONE), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), /* H6 : I2C3_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* H7 : I2C3_SCL */ @@ -184,6 +192,9 @@ /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* H11 : SRCCLKREQ5# ==> WLAN_PERST_L */ PAD_CFG_GPO(GPP_H11, 1, DEEP), }; -- To view, visit https://review.coreboot.org/c/coreboot/+/44169 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51752f47bc8d31d3a11da728ce00ca754381fde9 Gerrit-Change-Number: 44169 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

6 10

Change in coreboot[master]: soc/mediatek/mt8192: Add spi driver
by CK HU (Code Review) 13 Aug '20

13 Aug '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43960 ) Change subject: soc/mediatek/mt8192: Add spi driver ...................................................................... soc/mediatek/mt8192: Add spi driver Add driver for MT8192 SPI controller TEST=Boots correctly on MT8192EVB Signed-off-by: Qii Wang <qii.wang(a)mediatek.com> Change-Id: I2094dd2f14ad19b7dbd66a8e694cc71d654a2b4b --- M src/soc/mediatek/mt8192/include/soc/addressmap.h A src/soc/mediatek/mt8192/include/soc/spi.h A src/soc/mediatek/mt8192/spi.c 3 files changed, 195 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43960/1 diff --git a/src/soc/mediatek/mt8192/include/soc/addressmap.h b/src/soc/mediatek/mt8192/include/soc/addressmap.h old mode 100755 new mode 100644 index c4b3047..e0cd536 --- a/src/soc/mediatek/mt8192/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8192/include/soc/addressmap.h @@ -23,6 +23,14 @@ APMIXED_BASE = IO_PHYS + 0x0000C000, PWRAP_BASE = IO_PHYS + 0x0000D000, UART0_BASE = IO_PHYS + 0x01002000, + SPI0_BASE = IO_PHYS + 0x0100A000, + SPI1_BASE = IO_PHYS + 0x01010000, + SPI2_BASE = IO_PHYS + 0x01012000, + SPI3_BASE = IO_PHYS + 0x01013000, + SPI4_BASE = IO_PHYS + 0x01018000, + SPI5_BASE = IO_PHYS + 0x01019000, + SPI6_BASE = IO_PHYS + 0x0101D000, + SPI7_BASE = IO_PHYS + 0x0101E000, SSUSB_IPPC_BASE = IO_PHYS + 0x01203e00, SFLASH_REG_BASE = IO_PHYS + 0x01234000, IOCFG_RM_BASE = IO_PHYS + 0x01C20000, diff --git a/src/soc/mediatek/mt8192/include/soc/spi.h b/src/soc/mediatek/mt8192/include/soc/spi.h new file mode 100644 index 0000000..fa98cf7 --- /dev/null +++ b/src/soc/mediatek/mt8192/include/soc/spi.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MTK_MT8192_SPI_H +#define MTK_MT8192_SPI_H + +#include <soc/spi_common.h> + +#define SPI_BUS_NUMBER 8 + +/* SPI peripheral register map. */ +typedef struct mtk_spi_regs { + uint32_t spi_cfg0_reg; + uint32_t spi_cfg1_reg; + uint32_t spi_tx_src_reg; + uint32_t spi_rx_dst_reg; + uint32_t spi_tx_data_reg; + uint32_t spi_rx_data_reg; + uint32_t spi_cmd_reg; + uint32_t spi_status0_reg; + uint32_t spi_status1_reg; + uint32_t spi_pad_macro_sel_reg; + uint32_t spi_cfg2_reg; + uint32_t spi_tx_src_64_reg; + uint32_t spi_rx_dst_64_reg; +} mtk_spi_regs; + +check_member(mtk_spi_regs, spi_pad_macro_sel_reg, 0x24); + +enum { + SPI_CFG0_CS_HOLD_SHIFT = 0, + SPI_CFG0_CS_SETUP_SHIFT = 16, +}; + +enum { + SPI_CFG2_SCK_LOW_SHIFT = 0, + SPI_CFG2_SCK_HIGH_SHIFT = 16, +}; + +enum { + SPI_CFG1_TICK_DLY_SHIFT = 29, + SPI_CFG1_TICK_DLY_MASK = 0x7 << SPI_CFG1_TICK_DLY_SHIFT, + +}; + +#endif diff --git a/src/soc/mediatek/mt8192/spi.c b/src/soc/mediatek/mt8192/spi.c new file mode 100644 index 0000000..116bb34 --- /dev/null +++ b/src/soc/mediatek/mt8192/spi.c @@ -0,0 +1,142 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <assert.h> +#include <soc/addressmap.h> +#include <soc/gpio.h> +#include <soc/spi.h> + +struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { + { + .regs = (void *)SPI0_BASE, + .cs_gpio = GPIO(SPI0_CSB), + }, + { + .regs = (void *)SPI1_BASE, + .cs_gpio = GPIO(SPI1_CSB), + }, + { + .regs = (void *)SPI2_BASE, + .cs_gpio = GPIO(SCP_SPI2_CSB), + }, + { + .regs = (void *)SPI3_BASE, + .cs_gpio = GPIO(CAM_RST1), + }, + { + .regs = (void *)SPI4_BASE, + .cs_gpio = GPIO(EINT5), + }, + { + .regs = (void *)SPI5_BASE, + .cs_gpio = GPIO(SPI5_CSB), + }, + { + .regs = (void *)SPI6_BASE, + .cs_gpio = GPIO(EINT1), + }, + { + .regs = (void *)SPI7_BASE, + .cs_gpio = GPIO(SDA0), + } +}; + +struct pad_func { + u8 pin_id; + u8 func; +}; + +#define PAD_FUNC(name, func) {PAD_##name##_ID, PAD_##name##_FUNC_##func} +#define PAD_FUNC_GPIO(name) {PAD_##name##_ID, 0} + +static const struct pad_func pad0_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC(SPI0_MI, SPI0_A_MI), + PAD_FUNC_GPIO(SPI0_CSB), + PAD_FUNC(SPI0_MO, SPI0_A_MO), + PAD_FUNC(SPI0_CLK, SPI0_A_CLK), + }, + { + PAD_FUNC(SPI1_MI, SPI1_A_MI), + PAD_FUNC_GPIO(SPI1_CSB), + PAD_FUNC(SPI1_MO, SPI1_A_MO), + PAD_FUNC(SPI1_CLK, SPI1_A_CLK), + }, + { + PAD_FUNC(SCP_SPI2_MI, SPI2_MI), + PAD_FUNC_GPIO(SCP_SPI2_CSB), + PAD_FUNC(SCP_SPI2_MO, SPI2_MO), + PAD_FUNC(SCP_SPI2_CK, SPI2_CLK), + }, + { + PAD_FUNC(CAM_RST2, SPI3_MI), + PAD_FUNC_GPIO(CAM_RST1), + PAD_FUNC(CAM_PDN0, SPI3_MO), + PAD_FUNC(CAM_RST0, SPI3_CLK), + }, + { + PAD_FUNC(EINT6, SPI4_A_MI), + PAD_FUNC_GPIO(EINT5), + PAD_FUNC(EINT7, SPI4_A_MO), + PAD_FUNC(EINT4, SPI4_A_CLK), + }, + { + PAD_FUNC(SPI5_MI, SPI5_A_MI), + PAD_FUNC_GPIO(SPI5_CSB), + PAD_FUNC(SPI5_MO, SPI5_A_MO), + PAD_FUNC(SPI5_CLK, SPI5_A_CLK), + }, + { + PAD_FUNC(EINT2, SPI6_MI), + PAD_FUNC_GPIO(EINT1), + PAD_FUNC(EINT3, SPI6_MO), + PAD_FUNC(EINT0, SPI6_CLK), + }, + { + PAD_FUNC(EINT16, SPI7_A_MI), + PAD_FUNC_GPIO(SDA0), + PAD_FUNC(EINT17, SPI7_A_MO), + PAD_FUNC(SCL0, SPI7_A_CLK), + } +}; + +void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) +{ + assert(bus < SPI_BUS_NUMBER); + const struct pad_func *ptr = NULL; + + if (pad_select == SPI_PAD0_MASK) + ptr = pad0_funcs[bus]; + else + assert(pad_select == SPI_PAD0_MASK); + + for (int i = 0; i < 4; i++) + gpio_set_mode((gpio_t){.id = ptr[i].pin_id}, ptr[i].func); +} + +void mtk_spi_set_timing(struct mtk_spi_regs *regs, u32 sck_ticks, u32 cs_ticks, + unsigned int tick_dly) +{ + write32(&regs->spi_cfg0_reg, + ((cs_ticks - 1) << SPI_CFG0_CS_HOLD_SHIFT) | + ((cs_ticks - 1) << SPI_CFG0_CS_SETUP_SHIFT)); + + write32(&regs->spi_cfg2_reg, + ((sck_ticks - 1) << SPI_CFG2_SCK_HIGH_SHIFT) | + ((sck_ticks - 1) << SPI_CFG2_SCK_LOW_SHIFT)); + + clrsetbits32(&regs->spi_cfg1_reg, SPI_CFG1_TICK_DLY_MASK | + SPI_CFG1_CS_IDLE_MASK, + (tick_dly << SPI_CFG1_TICK_DLY_SHIFT) | + ((cs_ticks - 1) << SPI_CFG1_CS_IDLE_SHIFT)); +} + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = SPI_BUS_NUMBER - 1, + }, +}; + +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map); -- To view, visit https://review.coreboot.org/c/coreboot/+/43960 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2094dd2f14ad19b7dbd66a8e694cc71d654a2b4b Gerrit-Change-Number: 43960 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: mb/google/asurada: Add a stub implementation of Asurada mainboard
by CK HU (Code Review) 13 Aug '20

13 Aug '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43963 ) Change subject: mb/google/asurada: Add a stub implementation of Asurada mainboard ...................................................................... mb/google/asurada: Add a stub implementation of Asurada mainboard Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 --- A src/mainboard/google/asurada/Kconfig A src/mainboard/google/asurada/Kconfig.name A src/mainboard/google/asurada/Makefile.inc A src/mainboard/google/asurada/bootblock.c A src/mainboard/google/asurada/chromeos.c A src/mainboard/google/asurada/chromeos.fmd A src/mainboard/google/asurada/devicetree.cb A src/mainboard/google/asurada/mainboard.c A src/mainboard/google/asurada/memlayout.ld A src/mainboard/google/asurada/reset.c 10 files changed, 199 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/43963/1 diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig new file mode 100644 index 0000000..aeb13b0 --- /dev/null +++ b/src/mainboard/google/asurada/Kconfig @@ -0,0 +1,64 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +# Umbrella option to be selected by variant boards. +config BOARD_GOOGLE_ASURADA_COMMON + def_bool n + +if BOARD_GOOGLE_ASURADA_COMMON + +config VBOOT + select EC_GOOGLE_CHROMEEC_SWITCHES + select VBOOT_VBNV_FLASH + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOOTBLOCK_CONSOLE + select SOC_MEDIATEK_MT8192 + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_CHROMEOS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select SPI_FLASH + select SPI_FLASH_INCLUDE_ALL_DRIVERS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SPI + select MAINBOARD_HAS_SPI_TPM_CR50 if VBOOT + select MAINBOARD_HAS_TPM2 if VBOOT + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_FORCE_NATIVE_VGA_INIT + select HAVE_LINEAR_FRAMEBUFFER + +config MAINBOARD_DIR + string + default "google/asurada" + +config MAINBOARD_PART_NUMBER + string + default "Asurada" if BOARD_GOOGLE_ASURADA + +config DRIVER_TPM_SPI_BUS + hex + default 0x0 + +config BOOT_DEVICE_SPI_FLASH_BUS + int + default 1 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x2 + +endif diff --git a/src/mainboard/google/asurada/Kconfig.name b/src/mainboard/google/asurada/Kconfig.name new file mode 100644 index 0000000..df3dc24 --- /dev/null +++ b/src/mainboard/google/asurada/Kconfig.name @@ -0,0 +1,5 @@ +comment "Asurada" + +config BOARD_GOOGLE_ASURADA + bool "-> Asurada" + select BOARD_GOOGLE_ASURADA_COMMON diff --git a/src/mainboard/google/asurada/Makefile.inc b/src/mainboard/google/asurada/Makefile.inc new file mode 100644 index 0000000..80b7c0b --- /dev/null +++ b/src/mainboard/google/asurada/Makefile.inc @@ -0,0 +1,12 @@ +bootblock-y += memlayout.ld +bootblock-y += bootblock.c + +verstage-y += memlayout.ld +verstage-y += reset.c + +romstage-y += memlayout.ld + +ramstage-y += memlayout.ld +ramstage-y += chromeos.c +ramstage-y += mainboard.c +ramstage-y += reset.c diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c new file mode 100644 index 0000000..5dcae8c --- /dev/null +++ b/src/mainboard/google/asurada/bootblock.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/google/asurada/chromeos.c b/src/mainboard/google/asurada/chromeos.c new file mode 100644 index 0000000..8f9fa53 --- /dev/null +++ b/src/mainboard/google/asurada/chromeos.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <boot/coreboot_tables.h> +#include <gpio.h> +#include <security/tpm/tis.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ +} + +int get_write_protect_state(void) +{ + return 0; +} + +int tis_plat_irq_status(void) +{ + return 0; +} diff --git a/src/mainboard/google/asurada/chromeos.fmd b/src/mainboard/google/asurada/chromeos.fmd new file mode 100644 index 0000000..2635854 --- /dev/null +++ b/src/mainboard/google/asurada/chromeos.fmd @@ -0,0 +1,45 @@ +# Firmware Layout Description for Chrome OS. +# +# The size and address of every section must be aligned to at least 4K, except: +# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. +# +# 'FMAP' may be found by binary search so its starting address should be better +# aligned to larger values. +# +# For sections to be preserved on update, add (PRESERVE) to individual sections +# instead of a group section; otherwise the preserved data may be wrong if you +# resize or reorder sections inside a group. + +FLASH@0x0 8M { + WP_RO@0x0 4M { + RO_SECTION { + BOOTBLOCK 128K + FMAP 4K + COREBOOT(CBFS) + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 32K # At least 16K. + } + RW_SECTION_A 1500K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + RW_MISC 36K { + RW_VPD(PRESERVE) 16K # At least 8K. + RW_NVRAM(PRESERVE) 8K + RW_DDR_TRAINING(PRESERVE) 8K + RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + } + RW_SECTION_B 1500K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 0x100 + } + RW_SHARED 36K { # Will be force updated on recovery. + SHARED_DATA 4K # 4K or less for netboot params. + RW_UNUSED + } + RW_LEGACY(CBFS) 1M # Minimal 1M. +} diff --git a/src/mainboard/google/asurada/devicetree.cb b/src/mainboard/google/asurada/devicetree.cb new file mode 100644 index 0000000..9f682c3 --- /dev/null +++ b/src/mainboard/google/asurada/devicetree.cb @@ -0,0 +1,19 @@ +## +## This file is part of the coreboot project. +## +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip soc/mediatek/mt8192 + device cpu_cluster 0 on + device cpu 0 on end + end +end diff --git a/src/mainboard/google/asurada/mainboard.c b/src/mainboard/google/asurada/mainboard.c new file mode 100644 index 0000000..e6040fa --- /dev/null +++ b/src/mainboard/google/asurada/mainboard.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +static void mainboard_init(struct device *dev) +{ +} + +static void mainboard_enable(struct device *dev) +{ + dev->ops->init = &mainboard_init; +} + +struct chip_operations mainboard_ops = { + .name = CONFIG_MAINBOARD_PART_NUMBER, + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/google/asurada/memlayout.ld b/src/mainboard/google/asurada/memlayout.ld new file mode 100644 index 0000000..0f1fcec --- /dev/null +++ b/src/mainboard/google/asurada/memlayout.ld @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/asurada/reset.c b/src/mainboard/google/asurada/reset.c new file mode 100644 index 0000000..3a97ee5 --- /dev/null +++ b/src/mainboard/google/asurada/reset.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <reset.h> + +void do_board_reset(void) +{ +} -- To view, visit https://review.coreboot.org/c/coreboot/+/43963 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic7c8bc8a4bba40d1b511823e09945be52198b247 Gerrit-Change-Number: 43963 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

5 24

Change in coreboot[master]: cse_lite: Move global reset after MRC writeback.
by Caveh Jalali (Code Review) 13 Aug '20

13 Aug '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback. ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/44430/1/src/soc/intel/common/block… File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/44430/1/src/soc/intel/common/block… PS1, Line 657: #if CONFIG(SOC_INTEL_TIGERLAKE) > It would be helpful to have a comment here explaining why this particular phase was chosen for Tiger […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Aug 2020 08:22:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: comment

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