coreboot-gerrit August 2020

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback.
by Nick Vaccaro (Code Review) 13 Aug '20

13 Aug '20

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback. ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 13 Aug 2020 20:59:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/picasso/bl_uapp: Update header file
by Marshall Dawson (Code Review) 13 Aug '20

13 Aug '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44428 ) Change subject: vc/amd/picasso/bl_uapp: Update header file ...................................................................... vc/amd/picasso/bl_uapp: Update header file Update to match the 0.8.6.7B release of PSP blobs. BUG=b:163857965,b:137123167 TEST=Boot Trembyle, run SST Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I728dc17ba2cfb40bc6eaaa30556a3f6bc57d18f6 --- M src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h 1 file changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/44428/1 diff --git a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h index 45ea67e..69ada34 100644 --- a/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h +++ b/src/vendorcode/amd/fsp/picasso/include/bl_uapp/bl_syscall_public.h @@ -52,6 +52,7 @@ #define SVC_WRITE_POSTCODE 0x44 #define SVC_GET_MAX_WORKBUF_SIZE 0x45 #define SVC_SHA 0x46 +#define SVC_RSAPKCS_VERIFY 0x47 typedef struct _RSAPSS_VERIFY_PARAMS_T { @@ -64,6 +65,17 @@ char *pSig; // Signature to be verified, same size as ModulusSize } RSAPSS_VERIFY_PARAMS; +typedef struct RSAPKCS_VERIFY_PARAMS_T +{ + char *pHash; // Message digest to verify the RSA signature + unsigned int HashLen; // hash length in bytes + char *pModulus; // Modulus address + unsigned int ModulusSize; // Modulus length in bytes + char *pExponent; // Exponent address + unsigned int ExpSize; // Exponent length in bytes + char *pSig; // Signature to be verified, same size as ModulusSize +} RSAPKCS_VERIFY_PARAMS; + typedef enum _PSP_BOOT_MODE { PSP_BOOT_MODE_S0 = 0x0, @@ -347,7 +359,8 @@ */ uint32_t svc_crypto_sha(SHA_GENERIC_DATA *sha_op, SHA_OPERATION_MODE sha_mode); -/* RSA PSS Verification of signature and data +/* + * RSA PSS Verification of signature and data * * Parameters: * RSAPSS_VERIFY_PARAMS - Pointer to RSA PSS parameters @@ -356,6 +369,16 @@ */ uint32_t svc_rsa_pss_verify(const RSAPSS_VERIFY_PARAMS *params); +/* + * RSA PKCS Verification of signature and data + * + * Parameters: + * RSAPKCS_VERIFY_PARAMS - Pointer to RSA PKCS parameters + * + * Return value: BL_OK or error code + */ +uint32_t svc_rsa_pkcs_verify(const RSAPKCS_VERIFY_PARAMS *params); + /* C entry point for the Bootloader Userspace Application */ void Main(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/44428 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I728dc17ba2cfb40bc6eaaa30556a3f6bc57d18f6 Gerrit-Change-Number: 44428 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: 3rdparty/amd_blobs: Move the pointer for picasso update
by Marshall Dawson (Code Review) 13 Aug '20

13 Aug '20

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44427 ) Change subject: 3rdparty/amd_blobs: Move the pointer for picasso update ...................................................................... 3rdparty/amd_blobs: Move the pointer for picasso update Update PSP to 0.8.6.7B. BUG=b:163857965 TEST=none Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Change-Id: I634dadccc51b36f9ac25c3238a794564ce580d5a --- M 3rdparty/amd_blobs 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/44427/1 diff --git a/3rdparty/amd_blobs b/3rdparty/amd_blobs index 70fc3cb..3bd9078 160000 --- a/3rdparty/amd_blobs +++ b/3rdparty/amd_blobs @@ -1 +1 @@ -Subproject commit 70fc3cb79cc025895c897e13bb15fa3d89a23d48 +Subproject commit 3bd9078d27b10ea732a31bfabe48fa9868379850 -- To view, visit https://review.coreboot.org/c/coreboot/+/44427 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I634dadccc51b36f9ac25c3238a794564ce580d5a Gerrit-Change-Number: 44427 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/Makefiles: Clean up non-existing directory inclusion
by HAOUAS Elyes (Code Review) 13 Aug '20

13 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44317 ) Change subject: superio/Makefiles: Clean up non-existing directory inclusion ...................................................................... superio/Makefiles: Clean up non-existing directory inclusion Change-Id: I080f5b67c6e555fcc025ec11a1d15dddfe3a546d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/superio/Makefile.inc M src/superio/fintek/Makefile.inc M src/superio/ite/Makefile.inc M src/superio/nsc/Makefile.inc M src/superio/smsc/Makefile.inc M src/superio/winbond/Makefile.inc 6 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44317/1 diff --git a/src/superio/Makefile.inc b/src/superio/Makefile.inc index 2b52ca4..e874f34 100644 --- a/src/superio/Makefile.inc +++ b/src/superio/Makefile.inc @@ -2,14 +2,12 @@ subdirs-y += aspeed subdirs-y += fintek -subdirs-y += intel subdirs-y += ite subdirs-y += nsc subdirs-y += nuvoton subdirs-y += renesas subdirs-y += serverengines subdirs-y += smsc -subdirs-y += via subdirs-y += winbond ramstage-$(CONFIG_ARCH_RAMSTAGE_X86_32) += common/conf_mode.c diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 3d11d29..1c34f6d 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -4,13 +4,11 @@ bootblock-$(CONFIG_SUPERIO_FINTEK_COMMON_PRE_RAM) += common/early_serial.c romstage-$(CONFIG_SUPERIO_FINTEK_COMMON_PRE_RAM) += common/early_serial.c -subdirs-y += f71805f subdirs-y += f71808a subdirs-y += f71859 subdirs-y += f71863fg subdirs-y += f71869ad subdirs-y += f71872 -subdirs-y += f81216h subdirs-y += f81865f subdirs-y += f81866d subdirs-y += f81803a diff --git a/src/superio/ite/Makefile.inc b/src/superio/ite/Makefile.inc index f2ebda0..8ff122b 100644 --- a/src/superio/ite/Makefile.inc +++ b/src/superio/ite/Makefile.inc @@ -10,9 +10,7 @@ subdirs-y += it8528e subdirs-y += it8613e subdirs-y += it8623e -subdirs-y += it8671f subdirs-y += it8712f -subdirs-y += it8716f subdirs-y += it8718f subdirs-y += it8720f subdirs-y += it8721f diff --git a/src/superio/nsc/Makefile.inc b/src/superio/nsc/Makefile.inc index 1b5c395..2419e47 100644 --- a/src/superio/nsc/Makefile.inc +++ b/src/superio/nsc/Makefile.inc @@ -4,11 +4,7 @@ bootblock-$(CONFIG_SUPERIO_NSC_COMMON_PRE_RAM) += common/early_serial.c romstage-$(CONFIG_SUPERIO_NSC_COMMON_PRE_RAM) += common/early_serial.c -subdirs-y += pc87309 -subdirs-y += pc87360 -subdirs-y += pc87366 subdirs-y += pc87382 subdirs-y += pc87384 subdirs-y += pc87392 subdirs-y += pc87417 -subdirs-y += pc97317 diff --git a/src/superio/smsc/Makefile.inc b/src/superio/smsc/Makefile.inc index 9442a9e..86cf9c5 100644 --- a/src/superio/smsc/Makefile.inc +++ b/src/superio/smsc/Makefile.inc @@ -1,9 +1,6 @@ # SPDX-License-Identifier: GPL-2.0-only -subdirs-y += dme1737 subdirs-y += fdc37n972 -subdirs-y += lpc47b272 -subdirs-y += lpc47b397 subdirs-y += lpc47m10x subdirs-y += lpc47m15x subdirs-y += lpc47n207 @@ -15,5 +12,4 @@ subdirs-y += mec1308 subdirs-y += smscsuperio subdirs-y += sio1036 -subdirs-y += sch4037 subdirs-y += sch5545 diff --git a/src/superio/winbond/Makefile.inc b/src/superio/winbond/Makefile.inc index f6b9d57..68c4142 100644 --- a/src/superio/winbond/Makefile.inc +++ b/src/superio/winbond/Makefile.inc @@ -10,6 +10,4 @@ subdirs-y += w83627thg subdirs-y += w83627uhg subdirs-y += w83667hg-a -subdirs-y += w83697hf subdirs-y += w83977tf -subdirs-y += wpcd376i -- To view, visit https://review.coreboot.org/c/coreboot/+/44317 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I080f5b67c6e555fcc025ec11a1d15dddfe3a546d Gerrit-Change-Number: 44317 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Refactor ternary expressions
by Felix Singer (Code Review) 13 Aug '20

13 Aug '20

Felix Singer has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44365 ) Change subject: soc/intel/skylake: Refactor ternary expressions ...................................................................... soc/intel/skylake: Refactor ternary expressions Replace ternary expressions by `dev && dev->enabled`. Change-Id: Ie7afa48bf2c8bdad5a043f7cb6953d05b7b6597d Signed-off-by: Felix Singer <felixsinger(a)posteo.net> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/romstage/romstage.c 2 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44365/1 diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index 9239fd2..e96d624 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -167,7 +167,7 @@ } dev = pcidev_path_on_root(PCH_DEVFN_SATA); - params->SataEnable = dev ? dev->enabled : 0; + params->SataEnable = dev && dev->enabled; if (params->SataEnable) { memcpy(params->SataPortsEnable, config->SataPortsEnable, sizeof(params->SataPortsEnable)); @@ -236,7 +236,7 @@ params->SaImguEnable = dev && dev->enabled; dev = pcidev_path_on_root(PCH_DEVFN_CSE_3); - params->Heci3Enabled = dev ? dev->enabled : 0; + params->Heci3Enabled = dev && dev->enabled; params->LogoPtr = config->LogoPtr; params->LogoSize = config->LogoSize; @@ -248,7 +248,7 @@ params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx; dev = pcidev_path_on_root(PCH_DEVFN_GBE); - params->PchLanEnable = dev ? dev->enabled : 0; + params->PchLanEnable = dev && dev->enabled; if (params->PchLanEnable) { params->PchLanLtrEnable = config->EnableLanLtr; params->PchLanK1OffEnable = config->EnableLanK1Off; @@ -258,7 +258,7 @@ params->SsicPortEnable = config->SsicPortEnable; dev = pcidev_path_on_root(PCH_DEVFN_EMMC); - params->ScsEmmcEnabled = dev ? dev->enabled : 0; + params->ScsEmmcEnabled = dev && dev->enabled; params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; dev = pcidev_path_on_root(PCH_DEVFN_SDCARD); @@ -275,10 +275,10 @@ /* If ISH is enabled, enable ISH elements */ dev = pcidev_path_on_root(PCH_DEVFN_ISH); - params->PchIshEnable = dev ? dev->enabled : 0; + params->PchIshEnable = dev && dev->enabled; dev = pcidev_path_on_root(PCH_DEVFN_HDA); - params->PchHdaEnable = dev ? dev->enabled : 0; + params->PchHdaEnable = dev && dev->enabled; params->PchHdaVcType = config->PchHdaVcType; params->PchHdaIoBufferOwnership = config->IoBufferOwnership; @@ -353,7 +353,7 @@ /* Show SPI controller if enabled in devicetree.cb */ dev = pcidev_path_on_root(PCH_DEVFN_SPI); - params->ShowSpiController = dev ? dev->enabled : 0; + params->ShowSpiController = dev && dev->enabled; /* Enable xDCI controller if enabled in devicetree and allowed */ dev = pcidev_path_on_root(PCH_DEVFN_USBOTG); @@ -367,7 +367,7 @@ /* Enable or disable Gaussian Mixture Model in devicetree */ dev = pcidev_path_on_root(SA_DEVFN_GMM); - params->GmmEnable = dev ? dev->enabled : 0; + params->GmmEnable = dev && dev->enabled; /* * Send VR specific mailbox commands: diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 76f7a73..5d651ca 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -295,13 +295,13 @@ m_t_cfg->PchDciEn = config->PchDciEn; dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB); - m_cfg->EnableTraceHub = dev ? dev->enabled : 0; + m_cfg->EnableTraceHub = dev && dev->enabled; m_cfg->TraceHubMemReg0Size = config->TraceHubMemReg0Size; m_cfg->TraceHubMemReg1Size = config->TraceHubMemReg1Size; /* Enable SMBus controller */ dev = pcidev_path_on_root(PCH_DEVFN_SMBUS); - m_cfg->SmbusEnable = dev ? dev->enabled : 0; + m_cfg->SmbusEnable = dev && dev->enabled; /* Set primary graphic device */ soc_primary_gfx_config_params(m_cfg, config); -- To view, visit https://review.coreboot.org/c/coreboot/+/44365 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7afa48bf2c8bdad5a043f7cb6953d05b7b6597d Gerrit-Change-Number: 44365 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/intel/fsp2_0: add Kconfig for separate stack in DRAM
by Felix Held (Code Review) 13 Aug '20

13 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44406 ) Change subject: drivers/intel/fsp2_0: add Kconfig for separate stack in DRAM ...................................................................... drivers/intel/fsp2_0: add Kconfig for separate stack in DRAM soc/amd/picasso selected FSP_USES_CB_STACK even though it is FSP 2.0 based, so it doesn't reuse coreboot's stack, but sets up its own stack. In contrast to all other FSP 2.0 based platforms, this stack isn't in the CAR region, since AMD Picasso doesn't support CAR and the DRAM is already available when the x86 cores are released from reset. Selecting FSP_USES_CB_STACK ended up doing the right thing, but is semantically wrong. This patch introduces the new Kconfig option FSP_USES_STACK_IN_DRAM that will also result in the right code path in the FSP driver being taken. BUG=b:155501050 TEST=Mandolin still boots. Change-Id: Icd0ff8e17a535e2c247793b64f4b0565887183d8 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/drivers/intel/fsp2_0/Kconfig M src/drivers/intel/fsp2_0/memory_init.c M src/soc/amd/picasso/Kconfig 3 files changed, 19 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44406/1 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3caa04a..2d04a0b 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -130,14 +130,24 @@ without reinitializing stack pointer. This feature is supported Icelake onwards. +config FSP_USES_STACK_IN_DRAM + bool + default n + help + Enable support for FSP to use a DRAM region as stack. This is used in + non-CAR platforms where FSP still uses its own separate stack. + config FSP_TEMP_RAM_SIZE hex - depends on FSP_USES_CB_STACK + depends on FSP_USES_CB_STACK || FSP_USES_STACK_IN_DRAM help - The amount of anticipated heap usage in CAR by FSP to setup HOB. - This configuration is applicable for FSP specification using shared - stack with coreboot/bootloader. - Sync this value with Platform FSP integration guide recommendation. + The amount of memory coreboot reserves for the FSP to use. In the + case of FSP 2.1 and newer that share the stack with coreboot instead + of having its own stack, this is the amount of anticipated heap usage + in CAR by FSP to setup HOB and needs to be the recommened value from + the Platform FSP integration guide. In the case of the FSP having its + own stack that will be placed in DRAM and not in CAR, this is the + amount of memory the FSP needs for its stack and heap. config FSP2_0_USES_TPM_MRC_HASH bool diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index 7f5d389..8190c5e 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -184,8 +184,9 @@ * top and does not reinitialize stack pointer. The parameters passed * as StackBase and StackSize are actually for temporary RAM and HOBs * and are not related to FSP stack at all. + * Non-CAR FSP 2.0 platforms pass a DRAM location for the FSP stack. */ - if (CONFIG(FSP_USES_CB_STACK)) { + if (CONFIG(FSP_USES_CB_STACK) || CONFIG(FSP_USES_STACK_IN_DRAM)) { arch_upd->StackBase = temp_ram; arch_upd->StackSize = sizeof(temp_ram); } else if (setup_fsp_stack_frame(arch_upd, memmap)) { diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 526900a..8ebe9b6 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -53,7 +53,7 @@ select PLATFORM_USES_FSP2_0 select FSP_COMPRESS_FSP_M_LZMA select FSP_COMPRESS_FSP_S_LZMA - select FSP_USES_CB_STACK + select FSP_USES_STACK_IN_DRAM select UDK_2017_BINDING select HAVE_CF9_RESET select SUPPORT_CPU_UCODE_IN_CBFS @@ -377,7 +377,7 @@ config FSP_TEMP_RAM_SIZE hex - depends on FSP_USES_CB_STACK + depends on FSP_USES_STACK_IN_DRAM default 0x40000 help The amount of coreboot-allocated heap and stack usage by the FSP. -- To view, visit https://review.coreboot.org/c/coreboot/+/44406 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd0ff8e17a535e2c247793b64f4b0565887183d8 Gerrit-Change-Number: 44406 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: xeon_sp/cpx: Enable ACPI P-state support
by Jonathan Zhang (Code Review) 13 Aug '20

13 Aug '20

Jonathan Zhang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44404 ) Change subject: xeon_sp/cpx: Enable ACPI P-state support ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/44404/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44404/4//COMMIT_MSG@7 PS4, Line 7: xeon_sp/cpx: Enable ACPI P-state support Please also cleanup the redundant definition in include/soc/cpu.h . -- To view, visit https://review.coreboot.org/c/coreboot/+/44404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc Gerrit-Change-Number: 44404 Gerrit-PatchSet: 4 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Comment-Date: Thu, 13 Aug 2020 16:00:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback.
by Paul Menzel (Code Review) 13 Aug '20

13 Aug '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback. ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/c/coreboot/+/44430/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44430/2//COMMIT_MSG@7 PS2, Line 7: cse_lite: Move global reset after MRC writeback. Please remove the dot/period at the end of the summary. https://review.coreboot.org/c/coreboot/+/44430/2/src/soc/intel/common/block… File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/44430/2/src/soc/intel/common/block… PS2, Line 660: * memory training sequence. Please use 96 character text width. -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 13 Aug 2020 15:38:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback.
by Tim Wawrzynczak (Code Review) 13 Aug '20

13 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback. ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 13 Aug 2020 15:33:02 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/asus/am1i-a/buildOpts.c: fix the memory interleaving options
by Mike Banon (Code Review) 13 Aug '20

13 Aug '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40532 ) Change subject: mb/asus/am1i-a/buildOpts.c: fix the memory interleaving options ...................................................................... mb/asus/am1i-a/buildOpts.c: fix the memory interleaving options Fix the memory interleaving options in accordance with buildOpts.c of the other AMD boards like Lenovo G505S and ASUS A88XM-E. Example: if BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING is defined as FALSE then BLDOPT_REMOVE_NODE_INTERLEAVE should be defined as TRUE. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: Ib66e86d894c70e710ec67943c9d59c22108a7f2b --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/40532/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 71fedaa..48a9fe9 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -61,7 +61,7 @@ #define BLDOPT_REMOVE_ECC_SUPPORT TRUE //#define BLDOPT_REMOVE_BANK_INTERLEAVE TRUE //#define BLDOPT_REMOVE_DCT_INTERLEAVE TRUE -//#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE +#define BLDOPT_REMOVE_NODE_INTERLEAVE TRUE #define BLDOPT_REMOVE_PARALLEL_TRAINING TRUE #define BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT TRUE //#define BLDOPT_REMOVE_MEM_RESTORE_SUPPORT TRUE @@ -108,9 +108,9 @@ #define BLDCFG_MEMORY_RDIMM_CAPABLE TRUE #define BLDCFG_MEMORY_UDIMM_CAPABLE TRUE #define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE -#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE +#define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING TRUE #define BLDCFG_MEMORY_ENABLE_NODE_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE +#define BLDCFG_MEMORY_CHANNEL_INTERLEAVING TRUE #define BLDCFG_MEMORY_POWER_DOWN TRUE #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT #define BLDCFG_ONLINE_SPARE FALSE -- To view, visit https://review.coreboot.org/c/coreboot/+/40532 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib66e86d894c70e710ec67943c9d59c22108a7f2b Gerrit-Change-Number: 40532 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020