coreboot-gerrit August 2020

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Change in coreboot[master]: mb/system76/lemp9: gpio: disable internal SATAXPCIE pull-ups
by Felix Singer (Code Review) 14 Aug '20

14 Aug '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43645 ) Change subject: mb/system76/lemp9: gpio: disable internal SATAXPCIE pull-ups ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/43645 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6be716620695ac38c44a17abe1c4de97b099b8d7 Gerrit-Change-Number: 43645 Gerrit-PatchSet: 18 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Aug 2020 02:51:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/lemp9: gpio: configure unused pads
by Felix Singer (Code Review) 14 Aug '20

14 Aug '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43644 ) Change subject: mb/system76/lemp9: gpio: configure unused pads ...................................................................... Patch Set 18: (1 comment) https://review.coreboot.org/c/coreboot/+/43644/18/src/mainboard/system76/le… File src/mainboard/system76/lemp9/gpio.h: PS18: Configure the 20k pull-ups for the NC pads in a follow-up commit. Instead configure them with NONE as done with PAD_CFG_NC() and check if the build is reproducible. -- To view, visit https://review.coreboot.org/c/coreboot/+/43644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia370c180d5ae6f48360be14af3cbab29e6814e75 Gerrit-Change-Number: 43644 Gerrit-PatchSet: 18 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Aug 2020 02:41:06 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/lemp9: gpio: configure unused pads
by Felix Singer (Code Review) 14 Aug '20

14 Aug '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43644 ) Change subject: mb/system76/lemp9: gpio: configure unused pads ...................................................................... Patch Set 18: (1 comment) https://review.coreboot.org/c/coreboot/+/43644/18/src/mainboard/system76/le… File src/mainboard/system76/lemp9/gpio.h: PS18: Please add the new pads in a follow-up commit. -- To view, visit https://review.coreboot.org/c/coreboot/+/43644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia370c180d5ae6f48360be14af3cbab29e6814e75 Gerrit-Change-Number: 43644 Gerrit-PatchSet: 18 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Aug 2020 02:33:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
by Matt DeVillier (Code Review) 14 Aug '20

14 Aug '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40278 ) Change subject: mb/purism/librem_whl: Add new board Librem Mini (WHL-U) ...................................................................... Patch Set 8: (2 comments) https://review.coreboot.org/c/coreboot/+/40278/7/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/40278/7/src/mainboard/purism/libre… PS7, Line 135: # Misc : register "Device4Enable" = "1" : # HECI must be enabled w/HAP disable else S3 issues : register "HeciEnabled" = "1" : register "Heci3Enabled" = "0" > Please move these down to the devicetree. Done https://review.coreboot.org/c/coreboot/+/40278/7/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/ramstage.c: https://review.coreboot.org/c/coreboot/+/40278/7/src/mainboard/purism/libre… PS7, Line 8: /* Configure pads prior to SiliconInit() in case there's any : * dependencies during hardware initialization. */ > I think this is wrong. GPIOs are configured after silicon init. I would just delete it. mainboard_silicon_init_params() is called in: src/soc/intel/cannonlake/fsp_params.c platform_fsp_silicon_init_params_cb() ln 274 per src/drivers/intel/fsp2_0/silicon_init.c, this happens before silicon_init is called -- To view, visit https://review.coreboot.org/c/coreboot/+/40278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 Gerrit-Change-Number: 40278 Gerrit-PatchSet: 8 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 14 Aug 2020 02:05:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
by Matt DeVillier (Code Review) 14 Aug '20

14 Aug '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Angel Pons, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40278 to look at the new patch set (#8). Change subject: mb/purism/librem_whl: Add new board Librem Mini (WHL-U) ...................................................................... mb/purism/librem_whl: Add new board Librem Mini (WHL-U) Add new librem_whl baseboard and Librem Mini variant. Tested with SeaBIOS, Tianocore, and Heads payloads. All functions working normally except SATA, which is limited via a FSP UDP to 3Gbps until the correct HSIO PHY settings can be determined. https://puri.sm/products/librem-mini/ Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 --- A src/mainboard/purism/librem_whl/Kconfig A src/mainboard/purism/librem_whl/Kconfig.name A src/mainboard/purism/librem_whl/Makefile.inc A src/mainboard/purism/librem_whl/acpi/mainboard.asl A src/mainboard/purism/librem_whl/board_info.txt A src/mainboard/purism/librem_whl/devicetree.cb A src/mainboard/purism/librem_whl/dsdt.asl A src/mainboard/purism/librem_whl/ramstage.c A src/mainboard/purism/librem_whl/romstage.c A src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt A src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c A src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c A src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h 13 files changed, 690 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/40278/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/40278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 Gerrit-Change-Number: 40278 Gerrit-PatchSet: 8 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
by Felix Singer (Code Review) 14 Aug '20

14 Aug '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40278 ) Change subject: mb/purism/librem_whl: Add new board Librem Mini (WHL-U) ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/c/coreboot/+/40278/7/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/40278/7/src/mainboard/purism/libre… PS7, Line 135: # Misc : register "Device4Enable" = "1" : # HECI must be enabled w/HAP disable else S3 issues : register "HeciEnabled" = "1" : register "Heci3Enabled" = "0" Please move these down to the devicetree. https://review.coreboot.org/c/coreboot/+/40278/7/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/ramstage.c: https://review.coreboot.org/c/coreboot/+/40278/7/src/mainboard/purism/libre… PS7, Line 8: /* Configure pads prior to SiliconInit() in case there's any : * dependencies during hardware initialization. */ I think this is wrong. GPIOs are configured after silicon init. I would just delete it. -- To view, visit https://review.coreboot.org/c/coreboot/+/40278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 Gerrit-Change-Number: 40278 Gerrit-PatchSet: 7 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 14 Aug 2020 01:57:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback.
by Caveh Jalali (Code Review) 14 Aug '20

14 Aug '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback. ...................................................................... Patch Set 2: (1 comment) https://review.coreboot.org/c/coreboot/+/44430/2/src/soc/intel/common/block… File src/soc/intel/common/block/cse/cse_lite.c: https://review.coreboot.org/c/coreboot/+/44430/2/src/soc/intel/common/block… PS2, Line 660: * memory training sequence. > Please use 96 character text width. Ack -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 14 Aug 2020 01:57:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8192: Add DRAM resource in ramstage
by CK HU (Code Review) 14 Aug '20

14 Aug '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44410 ) Change subject: soc/mediatek/mt8192: Add DRAM resource in ramstage ...................................................................... soc/mediatek/mt8192: Add DRAM resource in ramstage Add DRAM resource in ramstage to load payload. Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: Iac02f81fc7d47851b3bba442eb7043169fbdbcfb --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/soc.c 2 files changed, 31 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/44410/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 25574c9..b0faf62 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -18,7 +18,9 @@ romstage-y += ../common/uart.c ramstage-y += ../common/gpio.c gpio.c +ramstage-y += emi.c ramstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c +ramstage-y += soc.c ramstage-y += ../common/timer.c ramstage-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/soc.c b/src/soc/mediatek/mt8192/soc.c new file mode 100644 index 0000000..9850fa6 --- /dev/null +++ b/src/soc/mediatek/mt8192/soc.c @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> +#include <soc/emi.h> +#include <symbols.h> + +static void soc_read_resources(struct device *dev) +{ + ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB); +} + +static void soc_init(struct device *dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .init = soc_init, +}; + +static void enable_soc_dev(struct device *dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_mediatek_mt8192_ops = { + CHIP_NAME("SOC Mediatek MT8192") + .enable_dev = enable_soc_dev, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/44410 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac02f81fc7d47851b3bba442eb7043169fbdbcfb Gerrit-Change-Number: 44410 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/ite/it8728f: Correct Kconfig selections
by Matt DeVillier (Code Review) 14 Aug '20

14 Aug '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44419 ) Change subject: superio/ite/it8728f: Correct Kconfig selections ...................................................................... superio/ite/it8728f: Correct Kconfig selections Per the datasheet and the it87 kernel driver, the IT8728F supports both 5 fans (vs 3) and use of a single 7-bit register for the PWM slope (5 bits in closed-loop mode). Change-Id: I3d1e6f5030f18d2c8ff533965ae4718be0f3c279 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/superio/ite/it8728f/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/44419/1 diff --git a/src/superio/ite/it8728f/Kconfig b/src/superio/ite/it8728f/Kconfig index 46410af..be0c207 100644 --- a/src/superio/ite/it8728f/Kconfig +++ b/src/superio/ite/it8728f/Kconfig @@ -7,3 +7,5 @@ select SUPERIO_ITE_ENV_CTRL_PWM_FREQ2 select SUPERIO_ITE_ENV_CTRL_FAN16_CONFIG select SUPERIO_ITE_ENV_CTRL_8BIT_PWM + select SUPERIO_ITE_ENV_CTRL_5FANS + select SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG -- To view, visit https://review.coreboot.org/c/coreboot/+/44419 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3d1e6f5030f18d2c8ff533965ae4718be0f3c279 Gerrit-Change-Number: 44419 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: superio/ite/common: Add support for closed-loop mode
by Matt DeVillier (Code Review) 14 Aug '20

14 Aug '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44418 ) Change subject: superio/ite/common: Add support for closed-loop mode ...................................................................... superio/ite/common: Add support for closed-loop mode Add support for tachometer closed loop mode, and programming of initial RPM vs initial PWM value. Change-Id: Idff29331c979f8518021103b6f8d19e75e657e3a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h 3 files changed, 23 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/44418/1 diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 8668110..c87f32d 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -128,13 +128,19 @@ pwm_ctrl = ITE_EC_FAN_CTL_PWM_MODE_AUTOMATIC; pwm_ctrl |= ITE_EC_FAN_CTL_TEMPIN(conf->tmpin); - pwm_start = ITE_EC_FAN_CTL_PWM_START_DUTY(conf->pwm_start); - - if (CONFIG(SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG)) { - pwm_auto = conf->slope & 0x7f; - } else { - pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); + if (conf->clsd_loop) { + pwm_ctrl |= ITE_EC_FAN_PWM_CLSD_LOOP; + pwm_start = ITE_EC_FAN_CTL_PWM_START_RPM(conf->rpm_start); pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + } else { + pwm_start = ITE_EC_FAN_CTL_PWM_START_DUTY(conf->pwm_start); + + if (CONFIG(SUPERIO_ITE_ENV_CTRL_7BIT_SLOPE_REG)) { + pwm_auto = conf->slope & 0x7f; + } else { + pwm_start |= ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(conf->slope); + pwm_auto = ITE_EC_FAN_CTL_PWM_SLOPE_LOWER(conf->slope); + } } if (conf->smoothing) diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index 7bce809..145c6c1 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -91,6 +91,7 @@ ? (0x1e + ((x)-4)) \ : (0x15 + ((x)-1)) \ ) +#define ITE_EC_FAN_PWM_CLSD_LOOP (1 << 2) #if CONFIG(SUPERIO_ITE_ENV_CTRL_5FANS) #define ITE_EC_FAN_CTL_TEMPIN_MASK (7 << 3) @@ -110,6 +111,13 @@ ? ITE_EC_FAN_MAX_PWM \ : (_p * ITE_EC_FAN_MAX_PWM) / 100; \ }) +#define ITE_EC_FAN_CTL_PWM_RPM(p) \ + ({ \ + const unsigned int _p = p; \ + (_p >= 4080) \ + ? 0xFF \ + : (_p / 16); \ + }) #define ITE_EC_HIGH_TEMP_LIMIT(x) (0x40 + ((x-1) * 2)) #define ITE_EC_LOW_TEMP_LIMIT(x) (0x41 + ((x-1) * 2)) @@ -178,6 +186,7 @@ /* Common for ITE_EC_FAN_CTL_PWM_START */ #define ITE_EC_FAN_CTL_PWM_SLOPE_BIT6(s) (((s) & 0x40) << 1) #define ITE_EC_FAN_CTL_PWM_START_DUTY(p) ITE_EC_FAN_CTL_PWM_DUTY(p) +#define ITE_EC_FAN_CTL_PWM_START_RPM(p) ITE_EC_FAN_CTL_PWM_RPM(p) /* Common for ITE_EC_FAN_CTL_PWM_AUTO */ #define ITE_EC_FAN_CTL_AUTO_SMOOTHING_EN (1 << 7) diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index fa896e4..1e1446b 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -60,6 +60,8 @@ u8 smoothing; /* enable smoothing */ u8 pwm_start; /* start at this duty cycle (%) */ u8 slope; /* increase duty cycle by `slope`%/°C */ + u8 clsd_loop; /* tachometer closed-loop mode enable */ + u8 rpm_start; /* start at this RPM (clsd_loop = 1) */ }; struct ite_ec_fan_config { -- To view, visit https://review.coreboot.org/c/coreboot/+/44418 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idff29331c979f8518021103b6f8d19e75e657e3a Gerrit-Change-Number: 44418 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020