coreboot-gerrit August 2020

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Change in coreboot[master]: mb/system76/lemp9: enable TPM
by Michael Niewöhner (Code Review) 14 Aug '20

14 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43641 ) Change subject: mb/system76/lemp9: enable TPM ...................................................................... Patch Set 14: will test that in the next days -- To view, visit https://review.coreboot.org/c/coreboot/+/43641 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I26d3b396fe1e99368e18fd3a6a9f02e3585b9f6e Gerrit-Change-Number: 43641 Gerrit-PatchSet: 14 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Aug 2020 17:01:27 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/system76/lemp9: gpio: configure unused pads
by Michael Niewöhner (Code Review) 14 Aug '20

14 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43644 ) Change subject: mb/system76/lemp9: gpio: configure unused pads ...................................................................... Patch Set 18: (2 comments) https://review.coreboot.org/c/coreboot/+/43644/18/src/mainboard/system76/le… File src/mainboard/system76/lemp9/gpio.h: PS18: > Please add the new pads in a follow-up commit. I have not added any new pads; all pads where there already PS18: > Configure the 20k pull-ups for the NC pads in a follow-up commit. […] This patch does a single thing: configure the NC pads according to schematics. Yes, that involves dropping the macro but there is no gain in doing that in a single commit. Further, reproducibility is not wanted because some NC pads are plain wrong -> we get nothing from reproducibility here. -- To view, visit https://review.coreboot.org/c/coreboot/+/43644 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia370c180d5ae6f48360be14af3cbab29e6814e75 Gerrit-Change-Number: 43644 Gerrit-PatchSet: 18 Gerrit-Owner: Michael Niewöhner Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Aug 2020 16:57:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/volteer: Disable TBT if platform is only USB3
by Brandon Breitenstein (Code Review) 14 Aug '20

14 Aug '20

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43771 ) Change subject: mb/volteer: Disable TBT if platform is only USB3 ...................................................................... mb/volteer: Disable TBT if platform is only USB3 TBT ports should be disabled if the DB is a USB3 DB. It is assumed if the DB doesn't support TBT the platform as a whole should only be USB3 capable and TBT functionality on both ports should be disabled BUG=NONE BRANCH=NONE TEST=Built coreboot and verified that TBT was disabled on platform with USB3 DB and enabled on platform with USB4/TBT DB Change-Id: I594f2e9483aaf896de2b6aea9a3460bd3826c58c Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/mainboard/google/volteer/romstage.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/43771/1 diff --git a/src/mainboard/google/volteer/romstage.c b/src/mainboard/google/volteer/romstage.c index d35bbb5..a8da340 100644 --- a/src/mainboard/google/volteer/romstage.c +++ b/src/mainboard/google/volteer/romstage.c @@ -31,6 +31,13 @@ if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) mem_cfg->PchHdaEnable = 0; + /* If the DB is USB3 disable TBT on the platform */ + if (fw_config_probe(FW_CONFIG(DB_USB, USB3_ACTIVE)) || + fw_config_probe(FW_CONFIG(DB_USB, USB3_PASSIVE))) { + mem_cfg->TcssItbtPcie0En = 0; + mem_cfg->TcssItbtPcie1En = 0; + } + meminit_lpddr4x(mem_cfg, board_cfg, &spd_info, half_populated); } -- To view, visit https://review.coreboot.org/c/coreboot/+/43771 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I594f2e9483aaf896de2b6aea9a3460bd3826c58c Gerrit-Change-Number: 43771 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
by Duncan Laurie (Code Review) 14 Aug '20

14 Aug '20

Duncan Laurie has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40278 ) Change subject: mb/purism/librem_whl: Add new board Librem Mini (WHL-U) ...................................................................... Patch Set 8: Code-Review+1 (2 comments) This looks like a nice little device, do you happen to know if it can be powered from the type-c port? https://review.coreboot.org/c/coreboot/+/40278/8/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/40278/8/src/mainboard/purism/libre… PS8, Line 96: Type-A front left upper You might consider describing these ports in the ACPI XHCI config as well, having the kernel report which ports are external can be useful in a media center or a kiosk application that wants to lock down external ports. Currently this has to be listed separately in devicetree but I've been thinking of ways to unify it. (example https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… ) Also related is the option to enable wake-on-attach/detach for the external ports, another feature that I have found useful in a media center setup but obviously can be more of a product behavior decision: https://review.coreboot.org/plugins/gitiles/coreboot/+/refs/heads/master/sr… Neither of these actually matter for base functionality and aren't exactly critical so feel free to ignore. https://review.coreboot.org/c/coreboot/+/40278/8/src/mainboard/purism/libre… PS8, Line 136: AcousticNoiseMitigation I think enabling this without any of the related settings (slew rates) isn't going to do anything. -- To view, visit https://review.coreboot.org/c/coreboot/+/40278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 Gerrit-Change-Number: 40278 Gerrit-PatchSet: 8 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 14 Aug 2020 15:59:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/block/gspi: Clear the GSPI controller data
by Karthik Ramasubramanian (Code Review) 14 Aug '20

14 Aug '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44275 ) Change subject: soc/intel/common/block/gspi: Clear the GSPI controller data ...................................................................... soc/intel/common/block/gspi: Clear the GSPI controller data Clear the GSPI controller data after resource allocation. This will ensure that any early BAR cached by the GSPI controller driver is cleared. This will allow using GSPI before and after resource allocation in ramstage. BUG=b:154333137 TEST=Ensure that the device boots to OS. Ensure that the TPM initialization is successful before and after resource allocation stage in ramstage. Change-Id: I4444266e35cca54e2c9bd9221733e59737ad8ebd Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/common/block/gspi/gspi.c 1 file changed, 7 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/44275/1 diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 599ab7e..10dd504 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -2,6 +2,7 @@ #include <device/mmio.h> #include <assert.h> +#include <bootstate.h> #include <console/console.h> #include <delay.h> #include <device/device.h> @@ -725,3 +726,9 @@ .xfer = gspi_ctrlr_xfer, .max_xfer_size = SPI_CTRLR_DEFAULT_MAX_XFER_SIZE, }; + +static void gspi_clear_base_stash(void *unused) +{ + memset(gspi_base, 0, sizeof(gspi_base)); +} +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_EXIT, gspi_clear_base_stash, NULL); -- To view, visit https://review.coreboot.org/c/coreboot/+/44275 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4444266e35cca54e2c9bd9221733e59737ad8ebd Gerrit-Change-Number: 44275 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Add missing clock power management dxio descriptor in...
by Justin Frodsham (Code Review) 14 Aug '20

14 Aug '20

Justin Frodsham has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44450 ) Change subject: mb/google/zork: Add missing clock power management dxio descriptor initializers to trembyle and dalboz. ...................................................................... mb/google/zork: Add missing clock power management dxio descriptor initializers to trembyle and dalboz. BUG=b:162423378 TEST=MAke sure the clk pm config callback executed properly Change-Id: Ifabbb5820b9b995e7d84489a834a6f7b82db4636 --- M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44450/1 diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c index c6e63ad..50fce1a 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c @@ -57,6 +57,7 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, + .clk_pm_support = true, } }; diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c index 26a5d33..8a15854 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c @@ -32,6 +32,7 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ4, + .clk_pm_support = true, }, { // WLAN @@ -61,6 +62,7 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ1, + .clk_pm_support = true, } }; -- To view, visit https://review.coreboot.org/c/coreboot/+/44450 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifabbb5820b9b995e7d84489a834a6f7b82db4636 Gerrit-Change-Number: 44450 Gerrit-PatchSet: 1 Gerrit-Owner: Justin Frodsham <justin.frodsham(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso/acpi: Set missing RTC offsets
by Raul Rangel (Code Review) 14 Aug '20

14 Aug '20

Raul Rangel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44448 ) Change subject: soc/amd/picasso/acpi: Set missing RTC offsets ...................................................................... soc/amd/picasso/acpi: Set missing RTC offsets The RTC Date Alarm and RTC AltCentury fields are supported on picasso. These get consumed by the linux kernel: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/t… The values are never actually used by the kernel though. So this is really a nop change. BUG=b:160277722 TEST=Boot kernel and make sure suspend stress test works. Signed-off-by: Raul E Rangel <rrangel(a)chromium.org> Change-Id: Ie83d7e0a06107a6de095f3e4c521d91e90920c0b --- M src/soc/amd/picasso/acpi.c 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44448/1 diff --git a/src/soc/amd/picasso/acpi.c b/src/soc/amd/picasso/acpi.c index 8062cfa..da6bc94 100644 --- a/src/soc/amd/picasso/acpi.c +++ b/src/soc/amd/picasso/acpi.c @@ -112,9 +112,9 @@ fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ - fadt->day_alrm = 0; /* 0x7d these have to be */ - fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ - fadt->century = 0; /* 0x7f to make rtc alarm work */ + fadt->day_alrm = 0x0d; + fadt->mon_alrm = 0; + fadt->century = 0x32; fadt->iapc_boot_arch = ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ fadt->flags |= ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44448 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie83d7e0a06107a6de095f3e4c521d91e90920c0b Gerrit-Change-Number: 44448 Gerrit-PatchSet: 1 Gerrit-Owner: Raul Rangel <rrangel(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Add a board specific reset
by Karthik Ramasubramanian (Code Review) 14 Aug '20

14 Aug '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44189 ) Change subject: mb/google/dedede: Add a board specific reset ...................................................................... mb/google/dedede: Add a board specific reset When ME jumps from RO to RW, global reset is initiated. When AP is reset as part of global reset, TPM initialization fails. This is because AP reset is not detected by TPM hosting an older firmware version. Request Embedded Controller (EC) to perform AP reset so that TPM can detect that event. BUG=b:162290856, b:162386991 TEST=Ensure that the device boots to OS with the board-specific reset sequence when ME jumps from RO to RW with an older and newer Cr50 firmware. Cq-Depend: chromium:2337430 Change-Id: Ib1f7271130e0b4b68c7f0917ecc4eadba1486206 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/dedede/mainboard.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/44189/1 diff --git a/src/mainboard/google/dedede/mainboard.c b/src/mainboard/google/dedede/mainboard.c index cb84e1f..1fbdfce 100644 --- a/src/mainboard/google/dedede/mainboard.c +++ b/src/mainboard/google/dedede/mainboard.c @@ -5,8 +5,16 @@ #include <baseboard/variants.h> #include <device/device.h> #include <ec/ec.h> +#include <ec/google/chromeec/ec.h> +#include <intelblocks/cse.h> #include <vendorcode/google/chromeos/chromeos.h> +void cse_board_reset(void) +{ + /* TODO: Check tpm firmware version before initiating AP reset. */ + google_chromeec_ap_reset(); +} + __weak void variant_isst_override(void) { /* -- To view, visit https://review.coreboot.org/c/coreboot/+/44189 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1f7271130e0b4b68c7f0917ecc4eadba1486206 Gerrit-Change-Number: 44189 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/am1i-a/buildOpts.c: choose the 1600 MHz RAM frequency
by Mike Banon (Code Review) 14 Aug '20

14 Aug '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40533 ) Change subject: mb/asus/am1i-a/buildOpts.c: choose the 1600 MHz RAM frequency ...................................................................... mb/asus/am1i-a/buildOpts.c: choose the 1600 MHz RAM frequency Together with the "AMD_XMP" changes, now this board with Crucial BLT8G3D1869DT1TX0 sticks could run at 1600 MHz CL8 (8-8-9-23) speeds. Earlier only 1333 MHz CL9 (9-9-10-27) has been possible with coreboot. tRP in "CL-tRCD-tRP-tRAS" gets set 1 point higher by AGESA because of Errata 638. See more info in a BKDG for AMD Family 16h Models 00h-0Fh. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I192096a8756a9985395ae8e9c8abf6ca0405c2bb --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/40533/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index 48a9fe9..51f46de 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -116,7 +116,7 @@ #define BLDCFG_ONLINE_SPARE FALSE #define BLDCFG_BANK_SWIZZLE TRUE #define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE #define BLDCFG_USE_BURST_MODE FALSE -- To view, visit https://review.coreboot.org/c/coreboot/+/40533 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I192096a8756a9985395ae8e9c8abf6ca0405c2bb Gerrit-Change-Number: 40533 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/sandybridge: Drop none reliable MCHBARx_AND_OR macro
by HAOUAS Elyes (Code Review) 14 Aug '20

14 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44459 ) Change subject: nb/sandybridge: Drop none reliable MCHBARx_AND_OR macro ...................................................................... nb/sandybridge: Drop none reliable MCHBARx_AND_OR macro Use of MCHBARx_AND_OR gives an error: overflow in conversion from 'int' to 'u16' {aka 'volatile short unsigned int'} changes value from '(int)*(volatile u16 *)((unsigned int)((int)i * 1024) + 4275127072) & -65536 | 26214' to '26214' [-Werror=overflow] Change-Id: I86e78195cd16c014e3e067edbb901756130a77ce Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 2 files changed, 36 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/44459/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3527c8e..2fe83cf 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -178,7 +178,7 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel) { - u32 addr, stretch; + u32 reg32, addr, stretch; stretch = ctrl->ref_card_offset[channel]; /* @@ -190,13 +190,18 @@ stretch = 3; addr = SCHED_SECOND_CBIT_ch(channel); - MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); - printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); + reg32 = MCHBAR32(addr); + reg32 &= 0xffffc3ff; + reg32 |= ((stretch << 12) | (stretch << 10)); + printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, reg32); } else { addr = TC_OTHP_ch(channel); - MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); - printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); + reg32 = MCHBAR32(addr); + reg32 &= 0xfff0ffff; + reg32 |= ((stretch << 16) | (stretch << 18)); + printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, reg32); } + MCHBAR32(addr) = reg32; } void dram_timing_regs(ramctr_timing *ctrl) @@ -3964,6 +3969,7 @@ { const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f }; int i, pat; + u32 reg32, int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; @@ -3985,8 +3991,10 @@ FOR_ALL_POPULATED_CHANNELS { /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), - ~0x3f000000, rege3c_b24[i] << 24); + reg32 = MCHBAR32(GDCRCMDDEBUGMUXCFG_Cz_S(channel); + reg32 &= ~0x3f000000; + reg32 |= (rege3c_b24[i] << 24); + MCHBAR32(GDCRCMDDEBUGMUXCFG_Cz_S(channel) = reg32; udelay(2); @@ -4481,13 +4489,17 @@ int channel; int t1_cycles = 0, t1_ns = 0, t2_ns; int t3_ns; - u32 r32; + u32 r32, reg32; /* FIXME: This register only exists on Ivy Bridge */ MCHBAR32(WMM_READ_CONFIG) = 0x46; - FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); + FOR_ALL_CHANNELS { + reg32 = MCHBAR32(TC_OTHP_ch(channel); + reg32 &= 0xffffcfff; + reg32 |= 0x1000; + MCHBAR32(TC_OTHP_ch(channel) = reg32; + } if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -4522,12 +4534,18 @@ } MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; - MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); + reg32 = MCHBAR32(MEM_TRML_THRESHOLDS_CONFIG); + reg32 &= ~0x00ffffff; + reg32 |= 0x00e4d5d0; + MCHBAR32(MEM_TRML_THRESHOLDS_CONFIG) = reg32; MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); - FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); - + FOR_ALL_CHANNELS { + reg32 = MCHBAR32(TC_RFP_ch(channel); + reg32 &= ~(3 << 16); + reg32 |= (1 << 16); + MCHBAR32(TC_RFP_ch(channel) = reg32; + } MCHBAR32_OR(MC_INIT_STATE_G, 1); MCHBAR32_OR(MC_INIT_STATE_G, 0x80); MCHBAR32(BANDTIMERS_SNB) = 0xfa; @@ -4555,9 +4573,11 @@ /* The graphics driver will use these watermark values */ printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); - MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0, - ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | + reg32 = MCHBAR32(SSKPD); + reg32 &= 0xC0C0C0C0; + reg32 |= ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); + MCHBAR32(SSKPD) = reg32; } void restore_timings(ramctr_timing *ctrl) diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 72724a3..902ed39 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -73,9 +73,6 @@ #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) #define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* As there are many registers, define them on a separate file */ #include "mchbar_regs.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/44459 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86e78195cd16c014e3e067edbb901756130a77ce Gerrit-Change-Number: 44459 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020