coreboot-gerrit August 2020

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Change in coreboot[master]: nb/common: Introduce reg{8,16,32}_and_or()
by HAOUAS Elyes (Code Review) 14 Aug '20

14 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44460 ) Change subject: nb/common: Introduce reg{8,16,32}_and_or() ...................................................................... nb/common: Introduce reg{8,16,32}_and_or() Change-Id: I8f42ff7c3f275fa1f763b545728be64ee2475324 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- A src/northbridge/intel/common/mchbar.h 1 file changed, 33 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/44460/1 diff --git a/src/northbridge/intel/common/mchbar.h b/src/northbridge/intel/common/mchbar.h new file mode 100644 index 0000000..f5d7e4c --- /dev/null +++ b/src/northbridge/intel/common/mchbar.h @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef INTEL_COMMON_MCHBAR_H +#define INTEL_COMMON_MCHBAR_H + +#include <stdint.h> + +uint8_t reg8_and_or(u8 reg, u8 mask, u8 or) +{ + u8 value; + value = mchbar8; + value &= mask; + value |= or; + return value; +} + +uint16_t reg16_and_or(u16 reg, u16 mask, u16 or) +{ + u16 value; + value = mchbar16; + value &= mask; + value |= or; + return value; +} + +uint32_t reg32_and_or(u32 reg, u32 mask, u32 or) +{ + u32 value; + value = mchbar32; + value &= mask; + value |= or; + return value; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44460 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f42ff7c3f275fa1f763b545728be64ee2475324 Gerrit-Change-Number: 44460 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: trogdor: SoC makefile blob support
by Saurabh Gorecha (Code Review) 14 Aug '20

14 Aug '20

Saurabh Gorecha has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35508 ) Change subject: trogdor: SoC makefile blob support ...................................................................... Patch Set 88: (1 comment) https://review.coreboot.org/c/coreboot/+/35508/86/src/soc/qualcomm/sc7180/M… File src/soc/qualcomm/sc7180/Makefile.inc: https://review.coreboot.org/c/coreboot/+/35508/86/src/soc/qualcomm/sc7180/M… PS86, Line 68: BL31_MAKEARGS += PLAT=sc7180 > *ping* […] We should add it similarly to https://review.coreboot.org/c/coreboot/+/35504/82/src/soc/qualcomm/sc7180/M… -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 88 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Saurabh Gorecha Gerrit-Comment-Date: Fri, 14 Aug 2020 13:01:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
by Angel Pons (Code Review) 14 Aug '20

14 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40278 ) Change subject: mb/purism/librem_whl: Add new board Librem Mini (WHL-U) ...................................................................... Patch Set 8: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/40278/8//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40278/8//COMMIT_MSG@14 PS8, Line 14: UDP UPD https://review.coreboot.org/c/coreboot/+/40278/8/src/mainboard/purism/libre… File src/mainboard/purism/librem_whl/acpi/mainboard.asl: https://review.coreboot.org/c/coreboot/+/40278/8/src/mainboard/purism/libre… PS8, Line 3: { nit: this should go on the next line (if this is needed at all) -- To view, visit https://review.coreboot.org/c/coreboot/+/40278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 Gerrit-Change-Number: 40278 Gerrit-PatchSet: 8 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Fri, 14 Aug 2020 11:14:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Add IGD Device ID
by Aamir Bohra (Code Review) 14 Aug '20

14 Aug '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44000 ) Change subject: soc/intel/jasperlake: Add IGD Device ID ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab3ba286f36afbf9533ac3cc62891fa390ca2441 Gerrit-Change-Number: 44000 Gerrit-PatchSet: 3 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Fri, 14 Aug 2020 10:17:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/ocp/deltalake: enable VT-d
by Jonathan Zhang (Code Review) 14 Aug '20

14 Aug '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44281 ) Change subject: mb/ocp/deltalake: enable VT-d ...................................................................... mb/ocp/deltalake: enable VT-d Update devicetree.cb to configure VT-d to be enabled. TESTED=booted on DeltaLake config A server, and verify DMAR table. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I7d76cd9d50d3e69a4919de281f11d30851bffa3f --- M src/mainboard/ocp/deltalake/devicetree.cb 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/44281/1 diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index f77a214..1773f9f 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -33,8 +33,9 @@ # configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL register "pstate_req_ratio" = "0xa" - register "coherency_support" = "0" - register "ats_support" = "0" + # configure VT-d + register "vtd_support" = "1" + register "x2apic" = "1" register "gen1_dec" = "0x00fc0601" # BIC in-band update support register "gen2_dec" = "0x000c0ca1" # IPMI KCS -- To view, visit https://review.coreboot.org/c/coreboot/+/44281 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7d76cd9d50d3e69a4919de281f11d30851bffa3f Gerrit-Change-Number: 44281 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx: add VT-d support
by Jonathan Zhang (Code Review) 14 Aug '20

14 Aug '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44280 ) Change subject: soc/intel/xeon_sp/cpx: add VT-d support ...................................................................... soc/intel/xeon_sp/cpx: add VT-d support Intel CPX-SP FSP added support for VT-d through adding UPD parameter X2apic. Based on devicetree.cb setting, enable VT-d programming through FSP-M. When VT-d is enabled, add DMAR ACPI table. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ic66374af6e53fb847c1bdc324eb3f4e01c334a94 --- M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/cpx/chip.h M src/soc/intel/xeon_sp/cpx/romstage.c 3 files changed, 324 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/44280/1 diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 62569e6..0f310f6 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -448,12 +448,315 @@ return current; } +/* + * Ports Stack Stack(HOB) IioConfigIou + * ========================================== + * 0 CSTACK stack 0 IOU0 + * 1A..1D PSTACK0 stack 1 IOU1 + * 2A..2D PSTACK1 stack 2 IOU2 + * 3A..3D PSTACK2 stack 4 IOU3 + */ +static int get_stack_for_port(int p) +{ + if (p == 0) + return CSTACK; + else if (p >= PORT_1A && p <= PORT_1D) + return PSTACK0; + else if (p >= PORT_2A && p <= PORT_2D) + return PSTACK1; + else //if (p >= PORT_3A && p <= PORT_3D) + return PSTACK2; +} + +static unsigned long acpi_create_drhd(unsigned long current, int socket, int stack) +{ + int IoApicID[] = { + // socket 0 + PC00_IOAPIC_ID, PC01_IOAPIC_ID, PC02_IOAPIC_ID, PC03_IOAPIC_ID, + PC04_IOAPIC_ID, PC05_IOAPIC_ID, + // socket 1 + PC06_IOAPIC_ID, PC07_IOAPIC_ID, PC08_IOAPIC_ID, PC09_IOAPIC_ID, + PC10_IOAPIC_ID, PC11_IOAPIC_ID, + }; + + uint32_t enum_id; + unsigned long tmp = current; + + size_t hob_size; + const uint8_t fsp_hob_iio_universal_data_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid( + fsp_hob_iio_universal_data_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + uint32_t reg_base = + hob->PlatformData.IIO_resource[socket].StackRes[stack].VtdBarAddress; + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", + __func__, socket, stack, bus, pcie_seg, reg_base); + + // Add DRHD Hardware Unit + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", + DRHD_INCLUDE_PCI_ALL, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, DRHD_INCLUDE_PCI_ALL, + pcie_seg, reg_base); + } else { + printk(BIOS_DEBUG, "[Hardware Unit Definition] Flags: 0x%x, PCI Segment Number: 0x%x, " + "Register Base Address: 0x%x\n", 0, pcie_seg, reg_base); + current += acpi_create_dmar_drhd(current, 0, pcie_seg, reg_base); + } + + // Add PCH IOAPIC + if (socket == 0 && stack == CSTACK) { + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + PCH_IOAPIC_ID, PCH_IOAPIC_BUS_NUMBER, + PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, PCH_IOAPIC_ID, + PCH_IOAPIC_BUS_NUMBER, PCH_IOAPIC_DEV_NUM, PCH_IOAPIC_FUNC_NUM); + } + + // Add IOAPIC entry + enum_id = IoApicID[(socket*MAX_IIO_STACK)+stack]; + printk(BIOS_DEBUG, " [IOAPIC Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", enum_id, bus, APIC_DEV_NUM, APIC_FUNC_NUM); + current += acpi_create_dmar_ds_ioapic(current, enum_id, bus, + APIC_DEV_NUM, APIC_FUNC_NUM); + + // Add CBDMA devices for CSTACK + if (socket != 0 && stack == CSTACK) { + for (int cbdma_func_id = 0; cbdma_func_id < 8; ++cbdma_func_id) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, CBDMA_DEV_NUM, cbdma_func_id); + current += acpi_create_dmar_ds_pci(current, + bus, CBDMA_DEV_NUM, cbdma_func_id); + } + } + + // Add PCIe Ports + if (socket != 0 || stack != CSTACK) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + if (get_stack_for_port(p) != stack) + continue; + + uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; + uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; + + uint32_t id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + PCI_VENDOR_ID); + if (id == 0xffffffff) + continue; + + printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, dev, func); + current += acpi_create_dmar_ds_pci_br(current, + bus, dev, func); + } + + // Add VMD + if (hob->PlatformData.VMDStackEnable[socket][stack] && + stack >= PSTACK0 && stack <= PSTACK2) { + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, VMD_DEV_NUM, VMD_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, + bus, VMD_DEV_NUM, VMD_FUNC_NUM); + } + } + + // Add HPET + if (socket == 0 && stack == CSTACK) { + uint16_t hpet_capid = read16((void *)HPET_BASE_ADDRESS); + uint16_t num_hpets = (hpet_capid >> 0x08) & 0x1F; // Bits [8:12] has hpet count + printk(BIOS_SPEW, "%s hpet_capid: 0x%x, num_hpets: 0x%x\n", + __func__, hpet_capid, num_hpets); + //BIT 15 + if (num_hpets && (num_hpets != 0x1f) && + (read32((void *)(HPET_BASE_ADDRESS + 0x100)) & (0x00008000))) { + printk(BIOS_DEBUG, " [Message-capable HPET Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, HPET_BUS_NUM, HPET_DEV_NUM, HPET0_FUNC_NUM); + current += acpi_create_dmar_ds_msi_hpet(current, 0, HPET_BUS_NUM, + HPET_DEV_NUM, HPET0_FUNC_NUM); + } + } + + acpi_dmar_drhd_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_atsr(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + unsigned long tmp = current; + bool first = true; + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + + for (int stack = 0; stack <= PSTACK2; ++stack) { + uint32_t bus = hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + uint64_t vtd_mmio_cap = read64((void *)(vtd_base + VTD_EXT_CAP_LOW)); + printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, vtd_base: 0x%x, " + "vtd_mmio_cap: 0x%llx\n", + __func__, socket, stack, bus, vtd_base, vtd_mmio_cap); + + // ATSR is applicable only for platform supporting device IOTLBs + // through the VT-d extended capability register + assert(vtd_mmio_cap != 0xffffffffffffffff); + if ((vtd_mmio_cap & 0x4) == 0) // BIT 2 + continue; + + for (int p = 0; p < NUMBER_PORTS_PER_SOCKET; ++p) { + if (socket == 0 && p == 0) + continue; + if (get_stack_for_port(p) != stack) + continue; + + uint32_t dev = iio_resource.PcieInfo.PortInfo[p].Device; + uint32_t func = iio_resource.PcieInfo.PortInfo[p].Function; + + u32 id = pci_mmio_read_config32(PCI_DEV(bus, dev, func), + PCI_VENDOR_ID); + if (id == 0xffffffff) + continue; + + if (first) { + printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " + "PCI Segment Number: 0x%x\n", + 0, pcie_seg); + current += acpi_create_dmar_atsr(current, 0, pcie_seg); + first = 0; + } + + printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " + "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", + 0, bus, dev, func); + current += acpi_create_dmar_ds_pci_br(current, bus, dev, func); + } + } + if (tmp != current) + acpi_dmar_atsr_fixup(tmp, current); + } + + return current; +} + +static unsigned long acpi_create_rmrr(unsigned long current) +{ + uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000); + + uint32_t *ptr; + + // reserve memory + ptr = cbmem_find(CBMEM_ID_STORAGE_DATA); + if (!ptr) { + ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size); + assert(ptr != NULL); + memset(ptr, 0, size); + } + + unsigned long tmp = current; + printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, " + "End Address (limit): 0x%x\n", + 0, (uint32_t) ptr, (uint32_t) ((uint32_t) ptr + size - 1)); + current += acpi_create_dmar_rmrr(current, 0, (uint32_t) ptr, + (uint32_t) ((uint32_t) ptr + size - 1)); + + printk(BIOS_DEBUG, " [PCI Endpoint Device] Enumeration ID: 0x%x, PCI Bus Number: 0x%x, " + "PCI Path: 0x%x, 0x%x\n", + 0, XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER, + PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM); + + acpi_dmar_rmrr_fixup(tmp, current); + + return current; +} + +static unsigned long acpi_create_rhsa(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + for (int socket = 0; socket < hob->PlatformData.numofIIO; ++socket) { + IIO_RESOURCE_INSTANCE iio_resource = + hob->PlatformData.IIO_resource[socket]; + for (int stack = 0; stack <= PSTACK2; ++stack) { + uint32_t vtd_base = iio_resource.StackRes[stack].VtdBarAddress; + if (!vtd_base) + continue; + + printk(BIOS_DEBUG, "[Remapping Hardware Static Affinity] Base Address: 0x%x, " + "Proximity Domain: 0x%x\n", vtd_base, socket); + current += acpi_create_dmar_rhsa(current, vtd_base, socket); + } + } + + return current; +} + +static unsigned long acpi_fill_dmar(unsigned long current) +{ + size_t hob_size; + const uint8_t uds_guid[16] = FSP_HOB_IIO_UNIVERSAL_DATA_GUID; + const IIO_UDS *hob = fsp_find_extension_hob_by_guid(uds_guid, &hob_size); + assert(hob != NULL && hob_size != 0); + + // DRHD + for (int iio = 1; iio <= hob->PlatformData.numofIIO; ++iio) { + int socket = iio; + if (socket == hob->PlatformData.numofIIO) // socket 0 should be last DRHD entry + socket = 0; + + if (socket == 0) { + for (int stack = 1; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack); + current = acpi_create_drhd(current, socket, CSTACK); + } else { + for (int stack = 0; stack <= PSTACK2; ++stack) + current = acpi_create_drhd(current, socket, stack); + } + } + + // RMRR + current = acpi_create_rmrr(current); + + // ATSR - causes hang + current = acpi_create_atsr(current); + + // RHSA + current = acpi_create_rhsa(current); + + return current; +} + unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { acpi_srat_t *srat; acpi_slit_t *slit; + acpi_dmar_t *dmar; + + const struct soc_intel_xeon_sp_cpx_config *const config = config_of(device); /* SRAT */ current = ALIGN(current, 8); @@ -471,5 +774,18 @@ current += slit->header.length; acpi_add_table(rsdp, slit); + /* DMAR */ + if (config->vtd_support) { + current = ALIGN(current, 8); + dmar = (acpi_dmar_t *)current; + printk(BIOS_DEBUG, "ACPI: * DMAR\n"); + printk(BIOS_DEBUG, "[DMA Remapping table] Flags: 0x%x\n", + (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT)); + acpi_create_dmar(dmar, (DMAR_INTR_REMAP | DMAR_X2APIC_OPT_OUT), acpi_fill_dmar); + current += dmar->header.length; + current = acpi_align_current(current); + acpi_add_table(rsdp, dmar); + } + return current; } diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index e46f34f..5d12079 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -84,8 +84,9 @@ uint32_t pstate_req_ratio; - uint32_t coherency_support; - uint32_t ats_support; + uint8_t vtd_support; + uint8_t vmx_enable; + uint8_t x2apic; /* Generic IO decode ranges */ uint32_t gen1_dec; diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 96949fd..e96b13e 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -13,6 +13,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSPM_CONFIG *m_cfg = &mupd->FspmConfig; + const config_t *config = config_of_soc(); /* ErrorLevel - 0 (disable) to 8 (verbose) */ m_cfg->DebugPrintLevel = 8; @@ -61,5 +62,9 @@ m_cfg->PEXPHIDE = 0x0; m_cfg->HidePEXPMenu = 0x0; + /* Enable VT-d according to DTB */ + m_cfg->VtdSupport = config->vtd_support; + m_cfg->X2apic = config->x2apic; + mainboard_memory_init_params(mupd); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44280 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic66374af6e53fb847c1bdc324eb3f4e01c334a94 Gerrit-Change-Number: 44280 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 15

Change in coreboot[master]: soc/intel/xeon_sp/cpx: remove unsupported configs
by Jonathan Zhang (Code Review) 14 Aug '20

14 Aug '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44402 ) Change subject: soc/intel/xeon_sp/cpx: remove unsupported configs ...................................................................... soc/intel/xeon_sp/cpx: remove unsupported configs coherency_support and ats_support are not supported by CPX-SP FSP. Remove them from soc_intel_xeon_sp_cpx_config struct. Remove corresponding settings from DeltaLake devicetree.cb. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: Ibe1c4e88817fc4be7915e95fa829f0a4c0d947f2 --- M src/mainboard/ocp/deltalake/devicetree.cb M src/soc/intel/xeon_sp/cpx/chip.h 2 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44402/1 diff --git a/src/mainboard/ocp/deltalake/devicetree.cb b/src/mainboard/ocp/deltalake/devicetree.cb index f77a214..24a2850 100644 --- a/src/mainboard/ocp/deltalake/devicetree.cb +++ b/src/mainboard/ocp/deltalake/devicetree.cb @@ -33,9 +33,6 @@ # configure PSTATE_REQ_RATIO for MSR_IA32_PERF_CTRL register "pstate_req_ratio" = "0xa" - register "coherency_support" = "0" - register "ats_support" = "0" - register "gen1_dec" = "0x00fc0601" # BIC in-band update support register "gen2_dec" = "0x000c0ca1" # IPMI KCS diff --git a/src/soc/intel/xeon_sp/cpx/chip.h b/src/soc/intel/xeon_sp/cpx/chip.h index e46f34f..aa605a4 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.h +++ b/src/soc/intel/xeon_sp/cpx/chip.h @@ -84,9 +84,6 @@ uint32_t pstate_req_ratio; - uint32_t coherency_support; - uint32_t ats_support; - /* Generic IO decode ranges */ uint32_t gen1_dec; uint32_t gen2_dec; -- To view, visit https://review.coreboot.org/c/coreboot/+/44402 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe1c4e88817fc4be7915e95fa829f0a4c0d947f2 Gerrit-Change-Number: 44402 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: doc/mb/ocp: update Delta Lake documentation
by Jonathan Zhang (Code Review) 14 Aug '20

14 Aug '20

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44360 ) Change subject: doc/mb/ocp: update Delta Lake documentation ...................................................................... doc/mb/ocp: update Delta Lake documentation Update Delta Lake documentation following ww30 to ww33 build/test/release cycle. Signed-off-by: Jonathan Zhang <jonzhang(a)fb.com> Change-Id: I9bb3a4daa423503d487045f2f069a43d2cc09129 --- M Documentation/mainboard/ocp/deltalake.md 1 file changed, 30 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/44360/1 diff --git a/Documentation/mainboard/ocp/deltalake.md b/Documentation/mainboard/ocp/deltalake.md index c4c3284..97b1f42 100644 --- a/Documentation/mainboard/ocp/deltalake.md +++ b/Documentation/mainboard/ocp/deltalake.md @@ -1,7 +1,8 @@ # OCP Delta Lake This page describes coreboot support status for the [OCP] (Open Compute Project) -Delta Lake server platform. +Delta Lake server platform. This page is updated following each 4-weeks +build/test/release cycle. ## Introduction @@ -22,7 +23,7 @@ - FSP blob: The blob (Intel Cooper Lake Scalable Processor Firmware Support Package) is not yet available to the public. It will be made public some time after the MP (Mass Production) of CooperLake Scalable Processor when the FSP is mature. -- Microcode: Not yet available to the public. +- Microcode: Available through github.com:otcshare/Intel-Generic-Microcode.git. - ME binary: Not yet available to the public. ## Payload @@ -55,26 +56,43 @@ - Type 2 -- Baseboard Information - Type 3 -- System Enclosure or Chassis - Type 4 -- Processor Information + - Type 7 -- Cache Information - Type 8 -- Port Connector Information - Type 9 -- PCI Slot Information - Type 11 -- OEM String - Type 13 -- BIOS Language Information - - Type 16 -- Physical Memory Array - - Type 19 -- Memory Array Mapped Address + - Type 32 -- System Boot Information + - Type 38 -- IPMI Device Information - Type 127 -- End-of-Table - - BMC integration: - BMC readiness check - IPMI commands - watchdog timer - POST complete pin acknowledgement + - Check BMC version: ipmidump -device - SEL record generation - Early serial output - port 80h direct to GPIO -- ACPI tables: APIC/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT +- ACPI tables: APIC/DMAR/DSDT/FACP/FACS/HPET/MCFG/SPMI/SRAT/SLIT/SSDT - Skipping memory training upon subsequent reboots by using MRC cache - BMC crash dump - Error injection through ITP +- Versions + - Check FSP version: cbmem | grep LB_TAG_PLATFORM_BLOB_VERSION + - Check Microcode version: cat /proc/cpuinfo | grep microcode +- Devices: + - Boot drive + - NIC card + - All 5 data drives +- Power button +- localboot +- netboot from IPv6 + +## Stress/performance tests passed +- OS warm reboot overnight (6 hours) +- Mprime test (6 hours) +- MLC (Intel Memory Latency Check) +- Linkpack ## Firmware configurations [ChromeOS VPD] is used to store most of the firmware configurations. @@ -84,29 +102,24 @@ VPD variables supported are: - firmware_version: This variable holds overall firmware version. coreboot uses that value to populate smbios type 1 version field. +- DeltaLake specific VPDs: check mb/ocp/deltalake/vpd.h. ## Known issues -- Even though CPX-SP FSP is based on FSP 2.2 framework, it does not - support FSP_USES_CB_STACK. An IPS ticket is filed with Intel. -- VT-d is not supported. An IPS ticket is filed with Intel. -- PCIe bifuration is not supported. An IPS ticket is filed with Intel. - ME based power capping. This is a bug in ME. An IPS ticket is filed with Intel. -- RO_VPD region as well as other RO regions are not write protected. - HECI is not set up correctly, so BMC is not able to get PCH and DIMM - temperature sensor readings. + temperature sensor readings. An IPS ticket is filed. ## Feature gaps -- Delta Lake DVT is not supported, as we only have Delta Lake EVT servers - at the moment. - SMBIOS: - - Type 7 -- Cache Information + - Type 16 -- Physical Memory Array - Type 17 -- Memory Device + - Type 19 -- Memory Array Mapped Address - Type 38 -- IPMI Device Information - Type 41 -- Onboard Devices Extended Information -- ACPI: - - DMAR +- Hardware error injection, detection, reporting - PFR/CBnT +- RO_VPD region as well as other RO regions are not write protected. ## Technology -- To view, visit https://review.coreboot.org/c/coreboot/+/44360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9bb3a4daa423503d487045f2f069a43d2cc09129 Gerrit-Change-Number: 44360 Gerrit-PatchSet: 1 Gerrit-Owner: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: soc/intel/gpio: set default value for RXEVCFG in native mode
by Maxim Polyakov (Code Review) 14 Aug '20

14 Aug '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41030 ) Change subject: soc/intel/gpio: set default value for RXEVCFG in native mode ...................................................................... soc/intel/gpio: set default value for RXEVCFG in native mode According to the documentation (Intel document #549921), RX Level/Edge Configuration (RXEVCFG) settings are not applicable in the native mode and BIOS does not need to configure them. Therefore, there is no need to change the default value for this field in the PAD_CFG_DW0 register. Set the RX Level/Edge to disable (2h = Drive '0') for all PAD_CFG_NF* macros. Change-Id: Ia667ae4bac4198fe269091050bf067c0a488289a Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/soc/intel/common/block/include/intelblocks/gpio_defs.h 1 file changed, 22 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/41030/1 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index 6eaaf0c..4bb318b 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -190,9 +190,10 @@ #endif /* Native function configuration */ -#define PAD_CFG_NF(pad, pull, rst, func) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(TxLASTRxE)) +#define PAD_CFG_NF(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE)) /* * Set native function with RX Level/Edge configuration and disable @@ -207,31 +208,36 @@ /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S Not applicable to all SOCs. Refer EDS */ -#define PAD_CFG_NF_1V8(pad, pull, rst, func) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) |\ - PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8) +#define PAD_CFG_NF_1V8(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(TxLASTRxE) | PAD_CFG1_TOL_1V8) #endif /* Native function configuration for standby state */ -#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate)) +#define PAD_CFG_NF_IOSSTATE(pad, pull, rst, func, iosstate) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate)) /* Native function configuration for standby state, also configuring iostandby as masked */ -#define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(IGNORE)) +#define PAD_CFG_NF_IOSTANDBY_IGNORE(pad, pull, rst, func) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(IGNORE)) /* Native function configuration for standby state, also configuring iosstate and iosterm */ -#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_FUNC(func), PAD_PULL(pull) | \ - PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) +#define PAD_CFG_NF_IOSSTATE_IOSTERM(pad, pull, rst, func, iosstate, iosterm) \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_FUNC(func), \ + PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* Configure native function, iosstate, iosterm and disable input/output buffer */ #define PAD_CFG_NF_BUF_IOSSTATE_IOSTERM(pad, pull, rst, func, bufdis, iosstate, iosterm) \ - _PAD_CFG_STRUCT(pad, PAD_RESET(rst) | PAD_BUF(bufdis) | PAD_FUNC(func), \ + _PAD_CFG_STRUCT(pad, \ + PAD_RESET(rst) | PAD_CFG0_TRIG_OFF | PAD_BUF(bufdis) | PAD_FUNC(func), \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) /* General purpose output, no pullup/down. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/41030 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia667ae4bac4198fe269091050bf067c0a488289a Gerrit-Change-Number: 41030 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

6 26

Change in coreboot[master]: ec/google/chromeec: Add helper to request AP reset
by Karthik Ramasubramanian (Code Review) 14 Aug '20

14 Aug '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44188 ) Change subject: ec/google/chromeec: Add helper to request AP reset ...................................................................... ec/google/chromeec: Add helper to request AP reset Add a helper function to initiate AP reset through Embedded Controller (EC). BUG=b:162290856 TEST=Ensure that the EC resets AP on boards where the command is supported. Change-Id: I01d7dfec72a8a3f6d2c4844bc062672e494860d8 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 25 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/44188/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index e66e3b1..40285dc 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1539,3 +1539,21 @@ return 0; } + +int google_chromeec_ap_reset(void) +{ + struct chromeec_command cmd = { + .cmd_code = EC_CMD_AP_RESET, + .cmd_version = 0, + .cmd_data_in = NULL, + .cmd_size_in = 0, + .cmd_data_out = NULL, + .cmd_size_out = 0, + .cmd_dev_index = 0, + }; + + if (google_chromeec_command(&cmd)) + return -1; + + return 0; +} diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index aead5f7..9d4e588 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -337,6 +337,13 @@ */ int google_chromeec_get_keybd_config(struct ec_response_keybd_config *keybd); +/** + * Send EC command to perform AP reset + * + * @return 0 on success, -1 on error + */ +int google_chromeec_ap_reset(void); + #if CONFIG(HAVE_ACPI_TABLES) /** * Writes USB Type-C PD related information to the SSDT -- To view, visit https://review.coreboot.org/c/coreboot/+/44188 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I01d7dfec72a8a3f6d2c4844bc062672e494860d8 Gerrit-Change-Number: 44188 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

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