coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: [WIP] skl: PEG for Optimus
by Benjamin Doron (Code Review) 15 Aug '20

15 Aug '20

Hello build bot (Jenkins), Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/40625 to look at the new patch set (#10). Change subject: [WIP] skl: PEG for Optimus ...................................................................... [WIP] skl: PEG for Optimus Creates PEG ACPI device for Optimus. Bugs: - "Data Link Layer Link Active not set in 1000ms" appears when using nouveau, but not the nvidia binary driver Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/acpi/pch.asl A src/soc/intel/skylake/acpi/peg.asl 2 files changed, 229 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/40625/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/40625 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I107bd5f7c192b8ffc83de6d8f1ac314bb5dcbfbd Gerrit-Change-Number: 40625 Gerrit-PatchSet: 10 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Benjamin Doron (Code Review) 15 Aug '20

15 Aug '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42745 ) Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... Patch Set 8: > Now the FSP option was mostly already enabled, so a `default n` > would be wrong as it would change that. But not for Jasper Lake. > So it should at least be mentioned in the commit message that > CB:41763 is effectively reverted. PAVP is enabled in the Jasperlake FSP, but I changed the Kconfig to preserve the old behaviour. -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 8 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sat, 15 Aug 2020 05:13:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel: Configure PAVP at compile-time
by Benjamin Doron (Code Review) 15 Aug '20

15 Aug '20

Hello build bot (Jenkins), Justin TerAvest, Angel Pons, Subrata Banik, Ronak Kanabar, Andrey Petrov, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/42745 to look at the new patch set (#8). Change subject: soc/intel: Configure PAVP at compile-time ...................................................................... soc/intel: Configure PAVP at compile-time Expose configuration of Intel's PAVP (Protected Audio-Video Path, a digital rights protection technology for multimedia content) to Kconfig. Also add a period at the end of Kconfig help for MMA while editing the file. Note that Jasperlake can now enable PAVP, whereas previously it was disabled. Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/apollolake/chip.c M src/soc/intel/cannonlake/fsp_params.c M src/soc/intel/common/Kconfig.common M src/soc/intel/icelake/fsp_params.c M src/soc/intel/jasperlake/fsp_params.c M src/soc/intel/skylake/chip.c 6 files changed, 25 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/42745/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/42745 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2aae741bb30e3be3c64324cd6334778bd271a903 Gerrit-Change-Number: 42745 Gerrit-PatchSet: 8 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Justin TerAvest <teravest(a)chromium.org> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Benjamin Doron (Code Review) 15 Aug '20

15 Aug '20

Hello build bot (Jenkins), Nico Huber, Matt DeVillier, Paul Menzel, Angel Pons, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/39538 to look at the new patch set (#25). Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... soc/intel/skylake: Configure L1 substates for PCH root ports Exposes PcieRpL1Substates to devicetree to allow boards to override this configuration. Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I36150858485715016158595c832c142b0582ddb8 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip.h 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/39538/25 -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 25 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake/acpi.c: Name devices on secondary bus
by Benjamin Doron (Code Review) 15 Aug '20

15 Aug '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43074 ) Change subject: soc/intel/skylake/acpi.c: Name devices on secondary bus ...................................................................... Patch Set 10: > In case the device has no acpi name/scope that's a SoC bug, as it simply doesn't provide those names yet. A console log will show what's missing. This can be done for other SoCs too if the implementation is correct. -- To view, visit https://review.coreboot.org/c/coreboot/+/43074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Gerrit-Change-Number: 43074 Gerrit-PatchSet: 10 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Prasun Gera Gerrit-Comment-Date: Sat, 15 Aug 2020 04:52:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/acpi.c: Name devices on secondary bus
by Benjamin Doron (Code Review) 15 Aug '20

15 Aug '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph, Angel Pons, Evgeny Zinoviev, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43074 to look at the new patch set (#10). Change subject: soc/intel/skylake/acpi.c: Name devices on secondary bus ...................................................................... soc/intel/skylake/acpi.c: Name devices on secondary bus Naming a device allows an ACPI _ROM method to be written for it. GPUs may require this to make the configuration data contained within available to an OS driver. This may be required for GPUs that do not contain their vBIOS, or perhaps the drivers require it in this form/fashion. Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully obtains the vBIOS via ACPI (kernel 5.7.11). Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/acpi.c 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/43074/10 -- To view, visit https://review.coreboot.org/c/coreboot/+/43074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Gerrit-Change-Number: 43074 Gerrit-PatchSet: 10 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Prasun Gera Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake/acpi.c: Name devices on secondary bus
by Benjamin Doron (Code Review) 15 Aug '20

15 Aug '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph, Angel Pons, Evgeny Zinoviev, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43074 to look at the new patch set (#8). Change subject: soc/intel/skylake/acpi.c: Name devices on secondary bus ...................................................................... soc/intel/skylake/acpi.c: Name devices on secondary bus Naming a device allows an ACPI _ROM method to be written for it. GPUs may require this to make the configuration data contained within available to an OS driver. This may be required for GPUs that do not contain their vBIOS, or perhaps the drivers require it in this form/fashion. Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully obtains the vBIOS via ACPI (kernel 5.7.11). Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- 0 files changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/43074/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/43074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Gerrit-Change-Number: 43074 Gerrit-PatchSet: 8 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Prasun Gera Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/skylake/acpi.c: Name devices on secondary bus
by Benjamin Doron (Code Review) 15 Aug '20

15 Aug '20

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph, Angel Pons, Evgeny Zinoviev, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43074 to look at the new patch set (#7). Change subject: soc/intel/skylake/acpi.c: Name devices on secondary bus ...................................................................... soc/intel/skylake/acpi.c: Name devices on secondary bus Naming a device allows an ACPI _ROM method to be written for it. GPUs may require this to make the configuration data contained within available to an OS driver. This may be required for GPUs that do not contain their vBIOS, or perhaps the drivers require it in this form/fashion. Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully obtains the vBIOS via ACPI (kernel 5.7.11). Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/acpi.c 1 file changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/43074/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/43074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Gerrit-Change-Number: 43074 Gerrit-PatchSet: 7 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Prasun Gera Gerrit-MessageType: newpatchset

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Change in coreboot[master]: [WIP] changes mmc
by Bora Guvendik (Code Review) 15 Aug '20

15 Aug '20

Bora Guvendik has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44490 ) Change subject: [WIP] changes mmc ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/44490 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7a486aba6b5678f62031de793c0866e03df117e7 Gerrit-Change-Number: 44490 Gerrit-PatchSet: 1 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.corp-partner.google.com> Gerrit-MessageType: abandon

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Change in coreboot[master]: arch/x86/postcar: Configure MMU along with MTRRs
by Patrick Rudolph (Code Review) 15 Aug '20

15 Aug '20

Patrick Rudolph has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/30501 ) Change subject: arch/x86/postcar: Configure MMU along with MTRRs ...................................................................... Abandoned replaced by new patch series -- To view, visit https://review.coreboot.org/c/coreboot/+/30501 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I235c70f05f63ed6d5146f093cf7f735879de4219 Gerrit-Change-Number: 30501 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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coreboot-gerrit August 2020