coreboot-gerrit August 2020

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Change in coreboot[master]: xeon_sp/cpx: Enable ACPI P-state support
by Johnny Lin (Code Review) 17 Aug '20

17 Aug '20

Johnny Lin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44404 ) Change subject: xeon_sp/cpx: Enable ACPI P-state support ...................................................................... Patch Set 7: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc Gerrit-Change-Number: 44404 Gerrit-PatchSet: 7 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 17 Aug 2020 05:11:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/mediatek/mt8192: Initialize watch dog in bootblock
by CK HU (Code Review) 17 Aug '20

17 Aug '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44434 ) Change subject: soc/mediatek/mt8192: Initialize watch dog in bootblock ...................................................................... soc/mediatek/mt8192: Initialize watch dog in bootblock Watch dog driver would print reboot reason and disable watch dog function in coreboot. Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: I7e849659700218f1c50365c2d68a32be2f703d94 --- M src/soc/mediatek/mt8192/Makefile.inc M src/soc/mediatek/mt8192/bootblock.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/44434/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index 0ba9feb..2a825fb 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -6,6 +6,7 @@ bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c +bootblock-y += ../common/wdt.c verstage-y += ../common/gpio.c gpio.c verstage-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c index f48e78c..770c603 100755 --- a/src/soc/mediatek/mt8192/bootblock.c +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -2,8 +2,10 @@ #include <bootblock_common.h> #include <soc/mmu_operations.h> +#include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); + mtk_wdt_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44434 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e849659700218f1c50365c2d68a32be2f703d94 Gerrit-Change-Number: 44434 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/mediatek/mt8192: Initialize mmu in bootblock
by CK HU (Code Review) 17 Aug '20

17 Aug '20

CK HU has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44433 ) Change subject: soc/mediatek/mt8192: Initialize mmu in bootblock ...................................................................... soc/mediatek/mt8192: Initialize mmu in bootblock Initialize CPU mmu and config range. Signed-off-by: CK Hu <ck.hu(a)mediatek.com> Change-Id: I5ba405dab87d51d373704657ccb44c07c7249041 --- M src/soc/mediatek/mt8192/Makefile.inc A src/soc/mediatek/mt8192/bootblock.c 2 files changed, 11 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/44433/1 diff --git a/src/soc/mediatek/mt8192/Makefile.inc b/src/soc/mediatek/mt8192/Makefile.inc index b0faf62..0ba9feb 100644 --- a/src/soc/mediatek/mt8192/Makefile.inc +++ b/src/soc/mediatek/mt8192/Makefile.inc @@ -1,6 +1,8 @@ ifeq ($(CONFIG_SOC_MEDIATEK_MT8192),y) +bootblock-y += bootblock.c bootblock-y += ../common/gpio.c gpio.c +bootblock-y += ../common/mmu_operations.c bootblock-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c bootblock-y += ../common/timer.c bootblock-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8192/bootblock.c b/src/soc/mediatek/mt8192/bootblock.c new file mode 100755 index 0000000..f48e78c --- /dev/null +++ b/src/soc/mediatek/mt8192/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootblock_common.h> +#include <soc/mmu_operations.h> + +void bootblock_soc_init(void) +{ + mtk_mmu_init(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44433 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ba405dab87d51d373704657ccb44c07c7249041 Gerrit-Change-Number: 44433 Gerrit-PatchSet: 1 Gerrit-Owner: CK HU <ck.hu(a)mediatek.com> Gerrit-MessageType: newchange

2 6

Change in coreboot[master]: xeon_sp/cpx: Enable ACPI P-state support
by Jingle Hsu (Code Review) 17 Aug '20

17 Aug '20

Hello build bot (Jenkins), Jonathan Zhang, Johnny Lin, Angel Pons, Morgan Jang, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44404 to look at the new patch set (#7). Change subject: xeon_sp/cpx: Enable ACPI P-state support ...................................................................... xeon_sp/cpx: Enable ACPI P-state support Implement ACPI P-state support to enable driver acpi_cpufreq. This patch leverages code from the Skylake project. Tested=On OCP Delta Lake cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies 1501000 1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com> --- M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/acpi.h M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 5 files changed, 142 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44404/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/44404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc Gerrit-Change-Number: 44404 Gerrit-PatchSet: 7 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: Revert "soc/intel/common/{pch,sata}: Remove SATA common code driver"
by Andrew McRae (Code Review) 17 Aug '20

17 Aug '20

Hello build bot (Jenkins), Nico Huber, Patrick Georgi, Martin Roth, Furquan Shaikh, Wonkyu Kim, Matt DeVillier, Subrata Banik, Angel Pons, Michael Niewöhner, Aamir Bohra, Patrick Rudolph, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43077 to review the following change. Change subject: Revert "soc/intel/common/{pch,sata}: Remove SATA common code driver" ...................................................................... Revert "soc/intel/common/{pch,sata}: Remove SATA common code driver" This reverts commit ebeaad9298f5b8df022ac77089a5c15dac6e069a. Reason for revert: Causes timeout on SATA access on Comet-lake (Puff mainboard). Change-Id: Ic092896a1f66010430775c6490967745336e07b3 --- M src/soc/intel/cannonlake/Kconfig A src/soc/intel/common/block/sata/Kconfig A src/soc/intel/common/block/sata/Makefile.inc A src/soc/intel/common/block/sata/sata.c M src/soc/intel/common/pch/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/tigerlake/Kconfig 8 files changed, 122 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/43077/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index dfc90cd..f06d84b 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -84,6 +84,7 @@ select PLATFORM_USES_FSP2_0 select REG_SCRIPT select SMP + select SOC_AHCI_PORT_IMPLEMENTED_INVERT select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE diff --git a/src/soc/intel/common/block/sata/Kconfig b/src/soc/intel/common/block/sata/Kconfig new file mode 100644 index 0000000..98ff696 --- /dev/null +++ b/src/soc/intel/common/block/sata/Kconfig @@ -0,0 +1,14 @@ +config SOC_INTEL_COMMON_BLOCK_SATA + bool + help + Intel Processor common SATA support + +config SOC_AHCI_PORT_IMPLEMENTED_INVERT + depends on SOC_INTEL_COMMON_BLOCK_SATA + bool + help + SATA PCI configuration space offset 0x92 Port + implement register bit 0-2 represents respective + SATA port enable status as in 0 = Disable; 1 = Enable. + If this option is selected then port enable status will be + inverted as in 0 = Enable; 1 = Disable. diff --git a/src/soc/intel/common/block/sata/Makefile.inc b/src/soc/intel/common/block/sata/Makefile.inc new file mode 100644 index 0000000..623d151 --- /dev/null +++ b/src/soc/intel/common/block/sata/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SATA) += sata.c diff --git a/src/soc/intel/common/block/sata/sata.c b/src/soc/intel/common/block/sata/sata.c new file mode 100644 index 0000000..d3f82ed --- /dev/null +++ b/src/soc/intel/common/block/sata/sata.c @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> + +#define SATA_ABAR_PORT_IMPLEMENTED 0x0c +#define SATA_PCI_CFG_PORT_CTL_STS 0x92 + +static void *sata_get_ahci_bar(struct device *dev) +{ + uintptr_t bar; + + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); +} + +/* + * SATA Port control and Status. By default, the SATA ports are set (by HW) + * to the disabled state (e.g. bits[3:0] == '0') as a result of an initial + * power on reset. When enabled by software as per SATA port mapping, + * the ports can transition between the on, partial and slumber states + * and can detect devices. When disabled, the port is in the off state and + * can't detect any devices. + */ +static void sata_final(struct device *dev) +{ + void *ahcibar = sata_get_ahci_bar(dev); + u8 port_impl, temp; + + /* Set Bus Master */ + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + + /* Read Ports Implemented (GHC_PI) */ + port_impl = read8(ahcibar + SATA_ABAR_PORT_IMPLEMENTED); + + if (CONFIG(SOC_AHCI_PORT_IMPLEMENTED_INVERT)) + port_impl = ~port_impl; + + port_impl &= 0x07; /* bit 0-2 */ + + /* Port enable */ + temp = pci_read_config8(dev, SATA_PCI_CFG_PORT_CTL_STS); + temp |= port_impl; + pci_write_config8(dev, SATA_PCI_CFG_PORT_CTL_STS, temp); +} + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .final = sata_final, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids[] = { + PCI_DEVICE_ID_INTEL_SPT_U_SATA, + PCI_DEVICE_ID_INTEL_SPT_U_Y_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_SPT_KBL_SATA, + PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI, + PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI, + PCI_DEVICE_ID_INTEL_LWB_SATA_RAID, + PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID, + PCI_DEVICE_ID_INTEL_LWB_SATA_AHCI_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SSATA_AHCI_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SATA_RAID_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SSATA_RAID_SUPER, + PCI_DEVICE_ID_INTEL_LWB_SATA_ALT, + PCI_DEVICE_ID_INTEL_LWB_SATA_ALT_RST, + PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT, + PCI_DEVICE_ID_INTEL_LWB_SSATA_ALT_RST, + PCI_DEVICE_ID_INTEL_CNL_SATA, + PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_CNP_CMP_COMPAT_SATA, + PCI_DEVICE_ID_INTEL_CNP_H_SATA, + PCI_DEVICE_ID_INTEL_CNP_LP_SATA, + PCI_DEVICE_ID_INTEL_ICP_U_SATA, + PCI_DEVICE_ID_INTEL_CMP_SATA, + PCI_DEVICE_ID_INTEL_CMP_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_CMP_LP_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_HALO_SATA, + PCI_DEVICE_ID_INTEL_CMP_H_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_TGP_LP_SATA, + PCI_DEVICE_ID_INTEL_TGP_SATA, + PCI_DEVICE_ID_INTEL_TGP_PREMIUM_SATA, + PCI_DEVICE_ID_INTEL_TGP_COMPAT_SATA, + PCI_DEVICE_ID_INTEL_MCC_AHCI_SATA, + PCI_DEVICE_ID_INTEL_JSP_SATA_1, + PCI_DEVICE_ID_INTEL_JSP_SATA_2, + 0 +}; + +static const struct pci_driver pch_sata __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +}; diff --git a/src/soc/intel/common/pch/Kconfig b/src/soc/intel/common/pch/Kconfig index 6e7f2f6..cca65d6 100644 --- a/src/soc/intel/common/pch/Kconfig +++ b/src/soc/intel/common/pch/Kconfig @@ -32,6 +32,7 @@ select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_PMC select SOC_INTEL_COMMON_BLOCK_RTC + select SOC_INTEL_COMMON_BLOCK_SATA select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SPI select SOC_INTEL_COMMON_BLOCK_TCO diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 52092ba..2a5156b 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -34,6 +34,7 @@ select PLATFORM_USES_FSP2_1 select REG_SCRIPT select SMP + select SOC_AHCI_PORT_IMPLEMENTED_INVERT select PMC_GLOBAL_RESET_ENABLE_LOCK select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 21dba0e..bfefbf2 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -35,6 +35,7 @@ select PLATFORM_USES_FSP2_1 select REG_SCRIPT select SMP + select SOC_AHCI_PORT_IMPLEMENTED_INVERT select PMC_GLOBAL_RESET_ENABLE_LOCK select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index fbf56b4..e0d29fb 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -34,6 +34,7 @@ select PLATFORM_USES_FSP2_1 select REG_SCRIPT select SMP + select SOC_AHCI_PORT_IMPLEMENTED_INVERT select PMC_GLOBAL_RESET_ENABLE_LOCK select CPU_INTEL_COMMON_SMM select SOC_INTEL_COMMON -- To view, visit https://review.coreboot.org/c/coreboot/+/43077 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic092896a1f66010430775c6490967745336e07b3 Gerrit-Change-Number: 43077 Gerrit-PatchSet: 1 Gerrit-Owner: Andrew McRae <amcrae(a)chromium.org> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: David Hendricks <david.hendricks(a)gmail.com> Gerrit-CC: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-CC: Lance Zhao Gerrit-CC: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: WIP: inteltool: Add option to output GPIOs as coreboot macros
by Matt DeVillier (Code Review) 16 Aug '20

16 Aug '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39394 ) Change subject: WIP: inteltool: Add option to output GPIOs as coreboot macros ...................................................................... WIP: inteltool: Add option to output GPIOs as coreboot macros based on Nico's work in CB:25145, but updated to use current macros found in gpio_defs.h in soc/intel/common. Avoids use of "legacy" macros which are only applicable to Skylake/Kabylake. Test: Generate reasonably sane list of macros for out-of-tree Whiskeylake-based device. Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: Ide0f0f529d62b312a719e78b0e2f747f41067a36 --- M util/inteltool/gpio.c M util/inteltool/gpio_groups.c M util/inteltool/inteltool.c M util/inteltool/inteltool.h 4 files changed, 212 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/39394/1 diff --git a/util/inteltool/gpio.c b/util/inteltool/gpio.c index e4e3570..05b5181 100644 --- a/util/inteltool/gpio.c +++ b/util/inteltool/gpio.c @@ -1072,7 +1072,7 @@ case PCI_DEVICE_ID_INTEL_HM370: case PCI_DEVICE_ID_INTEL_CM246: case PCI_DEVICE_ID_INTEL_ICELAKE_LP_U: - print_gpio_groups(sb); + print_gpio_groups(sb, false); return 0; case PCI_DEVICE_ID_INTEL_82371XX: printf("This southbridge has GPIOs in the PM unit.\n"); diff --git a/util/inteltool/gpio_groups.c b/util/inteltool/gpio_groups.c index 5457109..d034860 100644 --- a/util/inteltool/gpio_groups.c +++ b/util/inteltool/gpio_groups.c @@ -49,13 +49,185 @@ return "RESERVED"; } +static const char *decode_table_gpio_term(const size_t term) +{ + switch (term) { + case 0: return "NONE"; + case 2: return "DN_5K"; + case 4: return "DN_20K"; + case 9: return "UP_1K"; + case 10: return "UP_5K"; + case 11: return "UP_2K"; + case 12: return "UP_20K"; + case 13: return "UP_667"; + case 15: return "NATIVE"; + default: return "UNSUPPORTED"; + } +} + +static const char *decode_table_gpio_reset(const size_t reset) +{ + switch (reset) { + case 0: return "PWROK"; + case 1: return "DEEP"; + case 2: return "PLTRST"; + case 3: return "RSMRST"; + default: return "UNSUPPORTED"; + } +} + +static const char *decode_table_gpio_nf(const size_t pad_mode) +{ + switch (pad_mode) { + case 0: return "GPIO"; + case 1: return "NF1"; + case 2: return "NF2"; + case 3: return "NF3"; + default: return "UNSUPPORTED"; + } +} + +static const char *decode_table_gpio_trig(const size_t trig_mode) +{ + switch (trig_mode) { + case 0: return "LEVEL"; + case 1: return "EDGE_SINGLE"; + case 2: return "OFF"; + case 3: return "EDGE_BOTH"; + default: return "UNSUPPORTED"; + } +} + +static int print_table_gpio(const struct gpio_group *const group, + const size_t pad, + const uint32_t dw0, const uint32_t dw1) +{ + const size_t tx_state = dw0 >> 0 & 1; + const size_t tx_disable = dw0 >> 8 & 1; + const size_t rx_disable = dw0 >> 9 & 1; + const size_t pad_mode = dw0 >> 10 & 3; + const size_t int_route = dw0 >> 17 & 0x0f; + const size_t rx_invert = dw0 >> 23 & 1; + const size_t rx_evcfg = dw0 >> 25 & 3; + const size_t rx_raw1 = dw0 >> 28 & 1; + const size_t rx_padsel = dw0 >> 29 & 1; + const size_t pad_reset = dw0 >> 30 & 3; + const size_t term = dw1 >> 10 & 0x0f; + const size_t pad_tol = dw1 >> 25 & 0x01; + const size_t driver = dw1 >> 4 & 1; + + const char *const pad_name = group->pad_names[pad * group->func_count]; + + if (rx_padsel || rx_raw1) + return -1; + + if (pad_mode) { + printf("PAD_CFG_NF%s(%s, %s, %s, %s),\n", + pad_tol ? "_1V8" : "", pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_nf(pad_mode)); + } else if (!tx_disable) { + if (!rx_disable) { + fprintf(stderr, "WARNING: %s has both TX and RX enabled" + ", disabling RX!\n", pad_name); + } + if (term) { + printf("PAD_CFG_TERM_GPO(%s, %zu, %s, %s),\n", + pad_name, tx_state, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } else { + printf("PAD_CFG_GPO(%s, %zu, %s),\n", + pad_name, tx_state, + decode_table_gpio_reset(pad_reset)); + } + } else if (!rx_disable && tx_disable) { + switch (int_route) { + case 0x0: + if (rx_invert || rx_evcfg > 1) + return -1; + if (driver) { + printf("PAD_CFG_GPI_GPIO_DRIVER(%s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } else if (rx_evcfg & ~0x04) { + printf("PAD_CFG_GPI(%s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } else { + printf("PAD_CFG_GPI_INT(%s, %s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_trig(rx_evcfg)); + } + break; + case 0x1: + return -1; + case 0x2: + if (rx_evcfg == 1) { + printf("PAD_CFG_GPI_SMI_" + "%s(%s, %s, %s, %s),\n", + rx_invert ? "LOW" : "HIGH", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_trig(rx_evcfg)); + } else { + return -1; + } + break; + case 0x4: + if (rx_evcfg > 1) + return -1; + printf("PAD_CFG_GPI_SCI_%s(%s, %s, %s, %s),\n", + rx_invert ? "LOW" : "HIGH", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_trig(rx_evcfg)); + break; + case 0x8: + if (rx_evcfg > 1) + return -1; + if (rx_evcfg && !rx_invert) { + printf("PAD_CFG_GPI_APIC(%s, %s, %s, %s, %s),\n", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset), + decode_table_gpio_trig(rx_evcfg), + rx_invert ? "INVERT" : "NONE"); + } else { + printf("PAD_CFG_GPI_APIC%s%s(%s, %s, %s),\n", + rx_evcfg ? "_EDGE" : "", + rx_invert ? "_LOW" : "_HIGH", + pad_name, + decode_table_gpio_term(term), + decode_table_gpio_reset(pad_reset)); + } + break; + default: + return -1; + } + } else { + printf("PAD_NC(%s, %s),\n", pad_name, decode_table_gpio_term(term)); + } + return 0; +} + static void print_gpio_group(const uint8_t pid, size_t pad_cfg, const struct gpio_group *const group, - size_t pad_stepping) + size_t pad_stepping, const bool use_macros) { size_t p; - printf("%s\n", group->display); + if (use_macros) + printf("\n/* %s */\n\n", group->display); + else + printf("%s\n", group->display); for (p = 0; p < group->pad_count; ++p, pad_cfg += pad_stepping) { const uint32_t dw0 = read_pcr32(pid, pad_cfg); @@ -63,21 +235,31 @@ const char *const pad_name = group->pad_names[p * group->func_count]; - printf("0x%04zx: 0x%016"PRIx64" %-12s %-20s\n", pad_cfg, - (uint64_t)dw1 << 32 | dw0, - pad_name[0] == '*' ? &pad_name[1] : pad_name, - decode_pad_mode(group, p, dw0)); + if (use_macros) { + printf("/* %-8s %-20s */\t", + group->pad_names[p * group->func_count], + decode_pad_mode(group, p, dw0)); + + if (print_table_gpio(group, p, dw0, dw1)) + printf("PAD_CFG_UNSUPPORTED,\n"); + } else { + printf("0x%04zx: 0x%016"PRIx64" %-12s %-20s\n", pad_cfg, + (uint64_t)dw1 << 32 | dw0, + pad_name[0] == '*' ? &pad_name[1] : pad_name, + decode_pad_mode(group, p, dw0)); + } } } static void print_gpio_community(const struct gpio_community *const community, - size_t pad_stepping) + size_t pad_stepping, const bool use_macros) { size_t group, pad_count; size_t pad_cfg; /* offset in bytes under this communities PCR port */ - printf("%s\n\nPCR Port ID: 0x%06zx\n\n", - community->name, (size_t)community->pcr_port_id << 16); + if (!use_macros) + printf("%s\n\nPCR Port ID: 0x%06zx\n\n", + community->name, (size_t)community->pcr_port_id << 16); for (group = 0, pad_count = 0; group < community->group_count; ++group) pad_count += community->groups[group]->pad_count; @@ -92,7 +274,7 @@ for (group = 0; group < community->group_count; ++group) { print_gpio_group(community->pcr_port_id, pad_cfg, community->groups[group], - pad_stepping); + pad_stepping, use_macros); pad_cfg += community->groups[group]->pad_count * pad_stepping; } } @@ -176,7 +358,7 @@ } } -void print_gpio_groups(struct pci_dev *const sb) +void print_gpio_groups(struct pci_dev *const sb, const bool use_macros) { size_t community_count; const struct gpio_community *const *communities; @@ -192,5 +374,5 @@ printf("\n============= GPIOS =============\n\n"); for (; community_count; --community_count) - print_gpio_community(*communities++, pad_stepping); + print_gpio_community(*communities++, pad_stepping, use_macros); } diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 555aa2f..bd0e5e9 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -490,7 +490,7 @@ static void print_usage(const char *name) { - printf("usage: %s [-vh?gGrpmedPMaAsfSRx]\n", name); + printf("usage: %s [-vh?gGrpmedPMaAsfSRxC]\n", name); printf("\n" " -v | --version: print the version\n" " -h | --help: print this help\n\n" @@ -510,6 +510,7 @@ " -A | --ambs: dump AMB registers\n" " -x | --sgx: dump SGX status\n" " -a | --all: dump all known (safe) registers\n" + " -C | --macros: dump GPIOs in coreboot macro format\n" " --pcr=PORT_ID: dump all registers of a PCR port\n" " (may be specified max %d times)\n" "\n", MAX_PCR_PORTS); @@ -570,7 +571,7 @@ int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0; int dump_spi = 0, dump_gfx = 0, dump_ahci = 0, dump_sgx = 0; - int show_gpio_diffs = 0; + int show_gpio_diffs = 0, use_gpio_macros = 0; size_t pcr_count = 0; uint8_t dump_pcr[MAX_PCR_PORTS]; @@ -593,11 +594,12 @@ {"gfx", 0, 0, 'f'}, {"ahci", 0, 0, 'R'}, {"sgx", 0, 0, 'x'}, + {"macros", 0, 0, 'C'}, {"pcr", required_argument, 0, LONG_OPT_PCR}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAsfRS:x", + while ((opt = getopt_long(argc, argv, "vh?gGrpmedPMaAsfRCS:x", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -665,6 +667,10 @@ case 'x': dump_sgx = 1; break; + case 'C': + dump_gpios = 1; + use_gpio_macros = 1; + break; case LONG_OPT_PCR: if (pcr_count < MAX_PCR_PORTS) { errno = 0; @@ -795,8 +801,12 @@ /* Now do the deed */ if (dump_gpios) { - print_gpios(sb, 1, show_gpio_diffs); - printf("\n\n"); + if (use_gpio_macros) { + print_gpio_groups(sb, use_gpio_macros); + } else { + print_gpios(sb, 1, show_gpio_diffs); + printf("\n\n"); + } } else if (show_gpio_diffs) { print_gpios(sb, 0, show_gpio_diffs); printf("\n\n"); diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index dc55246..5468c21 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -19,6 +19,7 @@ #include <commonlib/helpers.h> +#include <stdbool.h> #include <stdint.h> #if defined(__GLIBC__) @@ -399,7 +400,7 @@ const struct gpio_community *const *get_gpio_communitys(struct pci_dev *const sb, size_t* community_count, size_t* pad_stepping); -void print_gpio_groups(struct pci_dev *sb); +void print_gpio_groups(struct pci_dev *sb, bool use_macros); int print_epbar(struct pci_dev *nb); int print_dmibar(struct pci_dev *nb); int print_pciexbar(struct pci_dev *nb); -- To view, visit https://review.coreboot.org/c/coreboot/+/39394 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ide0f0f529d62b312a719e78b0e2f747f41067a36 Gerrit-Change-Number: 39394 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
by Angel Pons (Code Review) 16 Aug '20

16 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40278 ) Change subject: mb/purism/librem_whl: Add new board Librem Mini (WHL-U) ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/40278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 Gerrit-Change-Number: 40278 Gerrit-PatchSet: 10 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 16 Aug 2020 19:33:03 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/agesa/f15tn: test the memps0_freq and memps1_freq before using...
by Mike Banon (Code Review) 16 Aug '20

16 Aug '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44508 ) Change subject: vc/amd/agesa/f15tn: test the memps0_freq and memps1_freq before using them ...................................................................... vc/amd/agesa/f15tn: test the memps0_freq and memps1_freq before using them This fix helps to avoid a division by zero. Not tested on a real hardware yet. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I0189b404bc87e14e5d0d68eca39a837cd99ffa6f --- M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c 1 file changed, 22 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/44508/1 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c index 75ec2fb..8f600f8 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxGmcInitTN.c @@ -279,9 +279,10 @@ * * * @param[in] Gfx Pointer to global GFX configuration - * + * @retval AGESA_SUCCESS Configuration successfully applied + * @retval AGESA_ERROR Requested configuration not supported */ -STATIC VOID +STATIC AGESA_STATUS GfxGmcInitializeSequencerTN ( IN GFX_PLATFORM_CONFIG *Gfx ) @@ -331,8 +332,19 @@ //scale_mp0 = sclk_max_freq / memps0_freq //scale_mp1 = sclk_max_freq / memps1_freq //Multiply it by 100 to avoid dealing with floating point values - scale_mp0 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps0_freq; - scale_mp1 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps1_freq; + if (memps0_freq != 0) + scale_mp0 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps0_freq; + else { + IDS_HDT_CONSOLE (GNB_TRACE, " ERROR! memps0_freq is 0 at GfxGmcInitializeSequencerTN\n"); + return AGESA_ERROR; + } + + if (memps1_freq != 0) + scale_mp1 = (GfxLibGetMaxSclk (GnbLibGetHeader (Gfx)) * 100) / memps1_freq; + else { + IDS_HDT_CONSOLE (GNB_TRACE, " ERROR! memps1_freq is 0 at GfxGmcInitializeSequencerTN\n"); + return AGESA_ERROR; + } GnbRegisterReadTN (TYPE_GMM , 0x2774 , &ex1047.Value, 0, GnbLibGetHeader (Gfx)); GnbRegisterReadTN (TYPE_GMM , 0x2778 , &ex1048.Value, 0, GnbLibGetHeader (Gfx)); @@ -429,6 +441,8 @@ } GnbRegisterWriteTN (TYPE_GMM , 0x2004 , &ex1012.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); GnbRegisterWriteTN (TYPE_GMM , 0x2214 , &ex1034.Value, GNB_REG_ACC_FLAG_S3SAVE, GnbLibGetHeader (Gfx)); + + return AGESA_SUCCESS; } /*----------------------------------------------------------------------------------------*/ @@ -531,7 +545,10 @@ GNB_TABLE_FLAGS_FORCE_S3_SAVE, GnbLibGetHeader (Gfx) ); - GfxGmcInitializeSequencerTN (Gfx); + if (GfxGmcInitializeSequencerTN (Gfx) == AGESA_ERROR) { + ASSERT (FALSE); + return AGESA_ERROR; + }; GfxGmcInitializeFbLocationTN (Gfx); GfxGmcSecureGarlicAccessTN (Gfx); GfxGmcInitializeC6LocationTN (Gfx); -- To view, visit https://review.coreboot.org/c/coreboot/+/44508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0189b404bc87e14e5d0d68eca39a837cd99ffa6f Gerrit-Change-Number: 44508 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/kontron: Add the Kontron mAL10 COMe module support
by Maxim Polyakov (Code Review) 16 Aug '20

16 Aug '20

Maxim Polyakov has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39133 ) Change subject: mb/kontron: Add the Kontron mAL10 COMe module support ...................................................................... Patch Set 41: (3 comments) https://review.coreboot.org/c/coreboot/+/39133/24/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/acpi/sbus.asl: PS24: > rename to smbus.asl […] Move to CB:44507 https://review.coreboot.org/c/coreboot/+/39133/39/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c: https://review.coreboot.org/c/coreboot/+/39133/39/src/mainboard/kontron/mal… PS39, Line 6: static const struct pad_config gpio_table[] = { > Just curious, is there a specific reason for having that in gpio. […] gpio.h contains macros that are not included in gpio_defs.h. I would not like to combine this with gpio config and also, it would be better when new definitions need to be added. I saw some examples of boards and decided to repeat it. https://review.coreboot.org/c/coreboot/+/39133/24/src/mainboard/kontron/mal… File src/mainboard/kontron/mal10/variants/mal10/devicetree.cb: https://review.coreboot.org/c/coreboot/+/39133/24/src/mainboard/kontron/mal… PS24, Line 108: chip drivers/crb > It's indeed the fTPM Done -- To view, visit https://review.coreboot.org/c/coreboot/+/39133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Gerrit-Change-Number: 39133 Gerrit-PatchSet: 41 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Lance Zhao Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Andrey Petrov <anpetrov(a)fb.com> Gerrit-CC: Michael Niewöhner Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Sun, 16 Aug 2020 15:41:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <felixsinger(a)posteo.net> Comment-In-Reply-To: Maxim Polyakov <max.senia.poliak(a)gmail.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Michael Niewöhner Gerrit-MessageType: comment

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Change in coreboot[master]: ec/kontron: add option to configure I2C frequency
by Maxim Polyakov (Code Review) 16 Aug '20

16 Aug '20

Maxim Polyakov has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39845 ) Change subject: ec/kontron: add option to configure I2C frequency ...................................................................... ec/kontron: add option to configure I2C frequency Allows to change the frequency for the I2C bus by overriding 2c_freq option from the devicetree of the board. For example, if the bus is not beyond the board, then we can increase the frequency in order to read DMI parameters from EEPROM faster. Tested on kontron COMe module with T10-TNI carrierboard [1,2] [1] https://review.coreboot.org/c/coreboot/+/39133 [2] Change-Id: I36a7ae30f1197f77854634fac3a9e1911ce92093 Signed-off-by: Maxim Polyakov <max.senia.poliak(a)gmail.com> --- M src/ec/kontron/kempld/chip.h M src/ec/kontron/kempld/kempld_i2c.c 2 files changed, 20 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/39845/1 diff --git a/src/ec/kontron/kempld/chip.h b/src/ec/kontron/kempld/chip.h index 597f281..2b18faf 100644 --- a/src/ec/kontron/kempld/chip.h +++ b/src/ec/kontron/kempld/chip.h @@ -32,6 +32,7 @@ struct ec_kontron_kempld_config { struct kempld_uart uart[KEMPLD_NUM_UARTS]; + unsigned short i2c_freq; }; #endif /* EC_KONTRON_KEMPLD_CHIP_H */ diff --git a/src/ec/kontron/kempld/kempld_i2c.c b/src/ec/kontron/kempld/kempld_i2c.c index ab41097..24297f0c9 100644 --- a/src/ec/kontron/kempld/kempld_i2c.c +++ b/src/ec/kontron/kempld/kempld_i2c.c @@ -27,6 +27,7 @@ #include <timer.h> #include <delay.h> +#include "chip.h" #include "kempld.h" #include "kempld_internal.h" @@ -54,8 +55,8 @@ #define I2C_CMD_READ_NACK 0x29 #define I2C_CMD_IACK 0x01 -#define KEMPLD_I2C_FREQ_MAX 2700 /* 2.7 mHz */ -#define KEMPLD_I2C_FREQ_STD 100 /* 100 kHz */ +#define KEMPLD_I2C_FREQ_MAX 2700 /* 2.7 mHz */ +#define KEMPLD_I2C_FREQ_STD_DEFAULT 100 /* 100 kHz */ #define EIO 5 #define ENXIO 6 @@ -244,12 +245,17 @@ void kempld_i2c_device_init(struct device *const dev) { + const struct ec_kontron_kempld_config *const config = dev->chip_info; + unsigned short frequency; u16 prescale_corr; long prescale; u8 ctrl; u8 stat; u8 cfg; + if (!config) + return; + if (kempld_get_mutex(100) < 0) return; @@ -258,11 +264,20 @@ ctrl &= ~(I2C_CTRL_EN | I2C_CTRL_IEN); kempld_write8(KEMPLD_I2C_CTRL, ctrl); + frequency = KEMPLD_I2C_FREQ_STD_DEFAULT; + if (config->i2c_freq) { + if (config->i2c_freq <= KEMPLD_I2C_FREQ_MAX) + frequency = config->i2c_freq + else + printk(BIOS_INFO, "kempld_i2c: %d kHz is an invalid frequency value. " + "Set default value %d kHz\n", config->i2c_freq, frequency); + } + const u8 spec_major = KEMPLD_SPEC_GET_MAJOR(kempld_read8(KEMPLD_SPEC)); if (spec_major == 1) - prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 5) - 1000; + prescale = KEMPLD_CLK / (frequency * 5) - 1000; else - prescale = KEMPLD_CLK / (KEMPLD_I2C_FREQ_STD * 4) - 3000; + prescale = KEMPLD_CLK / (frequency * 4) - 3000; if (prescale < 0) prescale = 0; -- To view, visit https://review.coreboot.org/c/coreboot/+/39845 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36a7ae30f1197f77854634fac3a9e1911ce92093 Gerrit-Change-Number: 39845 Gerrit-PatchSet: 1 Gerrit-Owner: Maxim Polyakov <max.senia.poliak(a)gmail.com> Gerrit-MessageType: newchange

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