coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/x4x/raminit_ddr23.c: Remove dead assignment
by HAOUAS Elyes (Code Review) 17 Aug '20

17 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44292 ) Change subject: nb/intel/x4x/raminit_ddr23.c: Remove dead assignment ...................................................................... nb/intel/x4x/raminit_ddr23.c: Remove dead assignment Change-Id: I2da586abf63517a2e9b73ea4d3fab513370947bd Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/44292/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 7c12ee0..89228f6 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -919,9 +919,6 @@ break; } - if (async != 1) - reg8 = MCHBAR8(0x188) & 0x1e; - MCHBAR8_AND(0x180, ~0x80); if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) -- To view, visit https://review.coreboot.org/c/coreboot/+/44292 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2da586abf63517a2e9b73ea4d3fab513370947bd Gerrit-Change-Number: 44292 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: drivers/usb: Avoid value overwritten before its usage
by John Zhao (Code Review) 17 Aug '20

17 Aug '20

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44185 ) Change subject: drivers/usb: Avoid value overwritten before its usage ...................................................................... drivers/usb: Avoid value overwritten before its usage Coverity detects that value assigned to variable "ret" is overwritten before it is used. Fix the issue by returning right value. Found-by: Coverity CID 1255942, 1241836 TEST=None Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I2e1fb5400ff64c6178bb30601896780f8d67b5c6 --- M src/drivers/usb/ehci_debug.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/44185/1 diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 5998172..3a52cca 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -581,7 +581,7 @@ ctrl = read32(&ehci_debug->control); ctrl &= ~(DBGP_CLAIM | DBGP_OUT); write32(&ehci_debug->control, ctrl); - //return ret; + return ret; next_debug_port: if (CONFIG_USBDEBUG_DEFAULT_PORT == 0) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44185 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2e1fb5400ff64c6178bb30601896780f8d67b5c6 Gerrit-Change-Number: 44185 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/{nb x4x}: Remove unused/deprecated cmos bits
by Arthur Heymans (Code Review) 17 Aug '20

17 Aug '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44251 ) Change subject: mb/{nb x4x}: Remove unused/deprecated cmos bits ...................................................................... mb/{nb x4x}: Remove unused/deprecated cmos bits Receiver enable results are now saved in flash. Change-Id: Ib1a985147b081860c58d1649c4e50301b8144b0c Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/cmos.layout M src/mainboard/asus/p5qc/cmos.layout M src/mainboard/asus/p5qpl-am/cmos.layout M src/mainboard/foxconn/g41s-k/cmos.layout M src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout M src/mainboard/intel/dg41wv/cmos.layout M src/mainboard/intel/dg43gt/cmos.layout M src/mainboard/lenovo/thinkcentre_a58/cmos.layout 8 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/44251/1 diff --git a/src/mainboard/asrock/g41c-gs/cmos.layout b/src/mainboard/asrock/g41c-gs/cmos.layout index f90467cd..c4f1b08 100644 --- a/src/mainboard/asrock/g41c-gs/cmos.layout +++ b/src/mainboard/asrock/g41c-gs/cmos.layout @@ -52,7 +52,6 @@ # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/asus/p5qc/cmos.layout b/src/mainboard/asus/p5qc/cmos.layout index 79f7347..3e8d5f0a 100644 --- a/src/mainboard/asus/p5qc/cmos.layout +++ b/src/mainboard/asus/p5qc/cmos.layout @@ -50,7 +50,6 @@ # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/asus/p5qpl-am/cmos.layout b/src/mainboard/asus/p5qpl-am/cmos.layout index 4905f1d..b1f6e77 100644 --- a/src/mainboard/asus/p5qpl-am/cmos.layout +++ b/src/mainboard/asus/p5qpl-am/cmos.layout @@ -52,7 +52,6 @@ # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/foxconn/g41s-k/cmos.layout b/src/mainboard/foxconn/g41s-k/cmos.layout index f90467cd..c4f1b08 100644 --- a/src/mainboard/foxconn/g41s-k/cmos.layout +++ b/src/mainboard/foxconn/g41s-k/cmos.layout @@ -52,7 +52,6 @@ # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index 79094e6..46940bd 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -53,7 +53,6 @@ # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/intel/dg41wv/cmos.layout b/src/mainboard/intel/dg41wv/cmos.layout index 4905f1d..b1f6e77 100644 --- a/src/mainboard/intel/dg41wv/cmos.layout +++ b/src/mainboard/intel/dg41wv/cmos.layout @@ -52,7 +52,6 @@ # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/intel/dg43gt/cmos.layout b/src/mainboard/intel/dg43gt/cmos.layout index 79bb1b8..2174ecd 100644 --- a/src/mainboard/intel/dg43gt/cmos.layout +++ b/src/mainboard/intel/dg43gt/cmos.layout @@ -52,7 +52,6 @@ # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout index 4905f1d..b1f6e77 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout +++ b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout @@ -52,7 +52,6 @@ # coreboot config options: check sums 984 16 h 0 check_sum -1024 144 r 0 recv_enable_results # ----------------------------------------------------------------- enumerations -- To view, visit https://review.coreboot.org/c/coreboot/+/44251 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib1a985147b081860c58d1649c4e50301b8144b0c Gerrit-Change-Number: 44251 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/model_6fx: Include Conroe-L microcode
by Arthur Heymans (Code Review) 17 Aug '20

17 Aug '20

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44248 ) Change subject: cpu/intel/model_6fx: Include Conroe-L microcode ...................................................................... cpu/intel/model_6fx: Include Conroe-L microcode This CPU variant has a different CPUID signature. Change-Id: Ice2c1b86382e5d91d9eda717e6522ed0a9c2229f Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/intel/model_6fx/Makefile.inc 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44248/1 diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index f1d64b7..f6f838d 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -4,4 +4,5 @@ ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c subdirs-y += ../smm/gen1 -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) \ + 3rdparty/intel-microcode/intel-ucode/06-16-01 -- To view, visit https://review.coreboot.org/c/coreboot/+/44248 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ice2c1b86382e5d91d9eda717e6522ed0a9c2229f Gerrit-Change-Number: 44248 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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Change in coreboot[master]: libpayload/defconfig: Set default heap size to 1MiB
by Nico Huber (Code Review) 17 Aug '20

17 Aug '20

Hello Felix Singer, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44176 to review the following change. Change subject: libpayload/defconfig: Set default heap size to 1MiB ...................................................................... libpayload/defconfig: Set default heap size to 1MiB libpayload's drivers keeps growing. With certain hardware/payload combinations (last time witnessed with Kontron/bSL6 and FILO), the default configuration runs out of memory. As there is a lot enabled by default, also set a big default heap size. Tested with FILO on QEMU/Q35. Change-Id: I51a1514097aeb8b3c835a2387db66869b81d0bcc Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- M payloads/libpayload/configs/defconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/44176/1 diff --git a/payloads/libpayload/configs/defconfig b/payloads/libpayload/configs/defconfig index 896039e..4ef1ed1 100644 --- a/payloads/libpayload/configs/defconfig +++ b/payloads/libpayload/configs/defconfig @@ -5,4 +5,4 @@ CONFIG_LP_USB_OHCI=y CONFIG_LP_USB_EHCI=y CONFIG_LP_USB_XHCI=y -CONFIG_LP_HEAP_SIZE=262144 +CONFIG_LP_HEAP_SIZE=1048576 -- To view, visit https://review.coreboot.org/c/coreboot/+/44176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51a1514097aeb8b3c835a2387db66869b81d0bcc Gerrit-Change-Number: 44176 Gerrit-PatchSet: 1 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/skylake: Call mainboard ACPI sleep methods
by Patrick Georgi (Code Review) 17 Aug '20

17 Aug '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38318 ) Change subject: soc/intel/skylake: Call mainboard ACPI sleep methods ...................................................................... soc/intel/skylake: Call mainboard ACPI sleep methods Skylake mainboards also can implement ACPI functionality surrounding sleep. Tested on an Acer Aspire VN7-572G (Skylake-U). Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38318 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/skylake/acpi/platform.asl 1 file changed, 12 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/skylake/acpi/platform.asl b/src/soc/intel/skylake/acpi/platform.asl index d989fb1..6b9dc40 100644 --- a/src/soc/intel/skylake/acpi/platform.asl +++ b/src/soc/intel/skylake/acpi/platform.asl @@ -3,6 +3,9 @@ /* Enable ACPI _SWS methods */ #include <soc/intel/common/acpi/acpi_wake_source.asl> +External (\_SB.MPTS, MethodObj) +External (\_SB.MWAK, MethodObj) + /* * The _PIC method is called by the OS to choose between interrupt * routing via the i8259 interrupt controller or the APIC. @@ -24,11 +27,20 @@ Method (_PTS, 1) { + If (CondRefOf (\_SB.MPTS)) + { + \_SB.MPTS (Arg0) + } } /* The _WAK method is called on system wakeup */ Method (_WAK, 1) { + If (CondRefOf (\_SB.MWAK)) + { + \_SB.MWAK (Arg0) + } + Return (Package (){ 0, 0 }) } -- To view, visit https://review.coreboot.org/c/coreboot/+/38318 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I969d92c7445b01964d92d28b21f6667614ea82e7 Gerrit-Change-Number: 38318 Gerrit-PatchSet: 11 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lance Zhao Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jasperlake: Add IGD Device ID
by Subrata Banik (Code Review) 17 Aug '20

17 Aug '20

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44000 ) Change subject: soc/intel/jasperlake: Add IGD Device ID ...................................................................... soc/intel/jasperlake: Add IGD Device ID Add IGD Device ID for Jasperlake. Reference is taken from Jasperlake EDS volume 1(Document Number: 613601). TEST=Build and boot Jasperlake platform. Change-Id: Iab3ba286f36afbf9533ac3cc62891fa390ca2441 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44000 Reviewed-by: Subrata Banik <subrata.banik(a)intel.com> Reviewed-by: Aamir Bohra <aamir.bohra(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/include/device/pci_ids.h M src/soc/intel/common/block/graphics/graphics.c M src/soc/intel/jasperlake/bootblock/report_platform.c 3 files changed, 3 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Subrata Banik: Looks good to me, approved Aamir Bohra: Looks good to me, approved diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 589e50c..b1d3d3f 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3638,6 +3638,7 @@ #define PCI_DEVICE_ID_INTEL_EHL_GT2_3 0x4570 #define PCI_DEVICE_ID_INTEL_JSL_GT1 0x4E51 #define PCI_DEVICE_ID_INTEL_JSL_GT2 0x4E71 +#define PCI_DEVICE_ID_INTEL_JSL_GT3 0x4E61 #define PCI_DEVICE_ID_INTEL_ADL_GT0 0x46ff #define PCI_DEVICE_ID_INTEL_ADL_GT1 0x4600 diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 38d41df..4561a38 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -282,6 +282,7 @@ PCI_DEVICE_ID_INTEL_EHL_GT2_3, PCI_DEVICE_ID_INTEL_JSL_GT1, PCI_DEVICE_ID_INTEL_JSL_GT2, + PCI_DEVICE_ID_INTEL_JSL_GT3, PCI_DEVICE_ID_INTEL_ADL_GT0, PCI_DEVICE_ID_INTEL_ADL_GT1, PCI_DEVICE_ID_INTEL_ADL_GT1_1, diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c index 8f1318d..d7eb490 100644 --- a/src/soc/intel/jasperlake/bootblock/report_platform.c +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -44,6 +44,7 @@ } igd_table[] = { { PCI_DEVICE_ID_INTEL_JSL_GT1, "Jasperlake GT1" }, { PCI_DEVICE_ID_INTEL_JSL_GT2, "Jasperlake GT2" }, + { PCI_DEVICE_ID_INTEL_JSL_GT3, "Jasperlake GT3" }, }; static inline uint8_t get_dev_revision(pci_devfn_t dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/44000 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iab3ba286f36afbf9533ac3cc62891fa390ca2441 Gerrit-Change-Number: 44000 Gerrit-PatchSet: 4 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: merged

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Change in coreboot[master]: mb/intel/jslrvp: Update the sleep assertion widths and Power Cycle Du...
by V Sowmya (Code Review) 17 Aug '20

17 Aug '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43793 ) Change subject: mb/intel/jslrvp: Update the sleep assertion widths and Power Cycle Duration ...................................................................... mb/intel/jslrvp: Update the sleep assertion widths and Power Cycle Duration This patch updates the SLP_X assertion width and Power Cycle Duration for the Japerlake RVP. BUG=b:159104150 Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/43793/1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index 616e35c..8b39d51 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -154,6 +154,20 @@ }, }" + /* Set the minimum assertion width */ + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- To view, visit https://review.coreboot.org/c/coreboot/+/43793 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie2a8d959d7ebbf9c24f8c4e8d5c68b70e0ac5708 Gerrit-Change-Number: 43793 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede: Update the sleep assertion widths and Power Cycle D...
by V Sowmya (Code Review) 17 Aug '20

17 Aug '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43792 ) Change subject: mb/google/dedede: Update the sleep assertion widths and Power Cycle Duration ...................................................................... mb/google/dedede: Update the sleep assertion widths and Power Cycle Duration This patch updates the SLP_X assertion width and Power Cycle Duration for the dedede platforms. BUG=b:159104150 Change-Id: I7079cbd564288b5d5b69e07661434439365063d3 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/43792/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 7502489..27a3214 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -166,6 +166,20 @@ # Skip the CPU repalcement check register "SkipCpuReplacementCheck" = "1" + /* Set the minimum assertion width */ + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # NOTE: Duration programmed in the below register should never be smaller than the + # stretch duration programmed in the following registers - + # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + # - PM_CFG.SLP_LAN_MIN_ASST_WDTH + register "PchPmPwrCycDur" = "1" # 1s + device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device -- To view, visit https://review.coreboot.org/c/coreboot/+/43792 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7079cbd564288b5d5b69e07661434439365063d3 Gerrit-Change-Number: 43792 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Add FSP UPD for minimum assertion widths
by V Sowmya (Code Review) 17 Aug '20

17 Aug '20

V Sowmya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43791 ) Change subject: soc/intel/jasperlake: Add FSP UPD for minimum assertion widths ...................................................................... soc/intel/jasperlake: Add FSP UPD for minimum assertion widths Add the FSP UPD for the chipset minimum assertion width and Power cycle duration setting to chip options which can be configured per maiboard. * PchPmSlpS3MinAssert: SLP_S3 Minimum Assertion Width Policy. * PchPmSlpS4MinAssert: SLP_S4 Minimum Assertion Width Policy. * PchPmSlpSusMinAssert: SLP_SUS Minimum Assertion Width Policy. * PchPmSlpAMinAssert: SLP_A Minimum Assertion Width Policy. * PchPmPwrCycDur: PCH PM Reset Power Cycle Duration. * Check to avoid violating the PCH EDS recommendation for the PchPmPwrCycDur setting. BUG=b:159104150 Change-Id: I042e8e34b7dfda3bc21e5f2e6727cb7692ffc7f7 Signed-off-by: V Sowmya <v.sowmya(a)intel.com> --- M src/soc/intel/jasperlake/chip.h M src/soc/intel/jasperlake/fsp_params.c 2 files changed, 187 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/43791/1 diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h index e5e10e3..77421f0 100644 --- a/src/soc/intel/jasperlake/chip.h +++ b/src/soc/intel/jasperlake/chip.h @@ -291,6 +291,59 @@ * for the platforms with soldered down SOC. */ uint8_t SkipCpuReplacementCheck; + + /* + * SLP_S3 Minimum Assertion Width Policy + * 1 = 60us + * 2 = 1ms + * 3 = 50ms (default) + * 4 = 2s + */ + uint8_t PchPmSlpS3MinAssert; + + /* + * SLP_S4 Minimum Assertion Width Policy + * 1 = 1s (default) + * 2 = 2s + * 3 = 3s + * 4 = 4s + */ + uint8_t PchPmSlpS4MinAssert; + + /* + * SLP_SUS Minimum Assertion Width Policy + * 1 = 0ms + * 2 = 500ms + * 3 = 1s + * 4 = 4s (default) + */ + uint8_t PchPmSlpSusMinAssert; + + /* + * SLP_A Minimum Assertion Width Policy + * 1 = 0ms + * 2 = 4s + * 3 = 98ms + * 4 = 2s (default) + */ + uint8_t PchPmSlpAMinAssert; + + /* + * PCH PM Reset Power Cycle Duration + * 0 = 4s (default) + * 1 = 1s + * 2 = 2s + * 3 = 3s + * 4 = 4s + * + * NOTE: Duration programmed in the PchPmPwrCycDur should never be smaller than the + * stretch duration programmed in the following registers - + * - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert) + * - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert) + * - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert) + * - PM_CFG.SLP_LAN_MIN_ASST_WDTH + */ + uint8_t PchPmPwrCycDur; }; typedef struct soc_intel_jasperlake_config config_t; diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 6493fd5..921ff5d 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -41,6 +41,38 @@ PCH_DEVFN_UART2 }; +/* List of Minimum Assertion durations in microseconds */ +enum min_assrt_dur { + MinAssrtDur0s = 0, + MinAssrtDur60us = 60, + MinAssrtDur1ms = 1000, + MinAssrtDur50ms = 50000, + MinAssrtDur98ms = 98000, + MinAssrtDur500ms = 500000, + MinAssrtDur1s = 1000000, + MinAssrtDur2s = 2000000, + MinAssrtDur3s = 3000000, + MinAssrtDur4s = 4000000, +}; + +/* Signal Assertion duration values */ +struct cfg_assrt_dur { + /* Minimum assertion duration of SLP_A signal */ + enum min_assrt_dur slp_a; + + /* Minimum assertion duration of SLP_4 signal */ + enum min_assrt_dur slp_s4; + + /* Minimum assertion duration of SLP_3 signal */ + enum min_assrt_dur slp_s3; + + /* PCH PM Power Cycle duration */ + enum min_assrt_dur pm_pwr_cyc_dur; +}; + +/* Default value of PchPmPwrCycDur */ +#define PCH_PM_PWR_CYC_DUR 0 + static void parse_devicetree(FSP_S_CONFIG *params) { const struct soc_intel_jasperlake_config *config = config_of_soc(); @@ -76,6 +108,92 @@ sizeof(config->SerialIoUartMode)); } +static enum min_assrt_dur get_high_asst_width(const struct cfg_assrt_dur *cfg_assrt_dur) +{ + enum min_assrt_dur max_assert_dur = cfg_assrt_dur->slp_s4; + + if (max_assert_dur < cfg_assrt_dur->slp_s3) + max_assert_dur = cfg_assrt_dur->slp_s3; + + if (max_assert_dur < cfg_assrt_dur->slp_a) + max_assert_dur = cfg_assrt_dur->slp_a; + + return max_assert_dur; +} + +static void get_min_assrt_dur(uint8_t slp_s4_min_asst, uint8_t slp_s3_min_asst, + uint8_t slp_a_min_asst, uint8_t pm_pwr_cyc_dur, + struct cfg_assrt_dur *cfg_assrt_dur) +{ + /* + * Ensure slp_x_dur_list[] elements in the devicetree config are in sync with + * FSP encoded values. + */ + + /* slp_s4_asst_dur_list : 1s, 1s(default), 2s, 3s, 4s */ + const enum min_assrt_dur slp_s4_asst_dur_list[] = { + MinAssrtDur1s, MinAssrtDur1s, MinAssrtDur2s, MinAssrtDur3s, MinAssrtDur4s + }; + + /* slp_s3_asst_dur_list: 50ms, 60us, 1ms, 50ms (Default), 2s */ + const enum min_assrt_dur slp_s3_asst_dur_list[] = { + MinAssrtDur50ms, MinAssrtDur60us, MinAssrtDur1ms, MinAssrtDur50ms, MinAssrtDur2s + }; + + /* slp_a_asst_dur_list: 2s, 0s, 4s, 98ms, 2s(Default) */ + const enum min_assrt_dur slp_a_asst_dur_list[] = { + MinAssrtDur2s, MinAssrtDur0s, MinAssrtDur4s, MinAssrtDur98ms, MinAssrtDur2s + }; + + /* pm_pwr_cyc_dur_list: 4s(Default), 1s, 2s, 3s, 4s */ + const enum min_assrt_dur pm_pwr_cyc_dur_list[] = { + MinAssrtDur4s, MinAssrtDur1s, MinAssrtDur2s, MinAssrtDur3s, MinAssrtDur4s + }; + + /* Get signal assertion width */ + if (slp_s4_min_asst < ARRAY_SIZE(slp_s4_asst_dur_list)) + cfg_assrt_dur->slp_s4 = slp_s4_asst_dur_list[slp_s4_min_asst]; + + if (slp_s3_min_asst < ARRAY_SIZE(slp_s3_asst_dur_list)) + cfg_assrt_dur->slp_s3 = slp_s3_asst_dur_list[slp_s3_min_asst]; + + if (slp_a_min_asst < ARRAY_SIZE(slp_a_asst_dur_list)) + cfg_assrt_dur->slp_a = slp_a_asst_dur_list[slp_a_min_asst]; + + if (pm_pwr_cyc_dur < ARRAY_SIZE(pm_pwr_cyc_dur_list)) + cfg_assrt_dur->pm_pwr_cyc_dur = pm_pwr_cyc_dur_list[pm_pwr_cyc_dur]; +} + +static uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_asst, uint8_t slp_s3_min_asst, + uint8_t slp_a_min_asst, uint8_t pm_pwr_cyc_dur) +{ + /* Set default values for the minimum asserton duration */ + struct cfg_assrt_dur cfg_assrt_dur = { + .slp_a = MinAssrtDur2s, + .slp_s4 = MinAssrtDur1s, + .slp_s3 = MinAssrtDur50ms, + .pm_pwr_cyc_dur = MinAssrtDur4s + }; + + enum min_assrt_dur high_asst_width; + + /* Convert assertion durations from register-encoded to microseconds */ + get_min_assrt_dur(slp_s4_min_asst, slp_s3_min_asst, slp_a_min_asst, pm_pwr_cyc_dur, + &cfg_assrt_dur); + + /* Get the higher assertion duration among PCH EDS specified signals for pwr_cyc_dur */ + high_asst_width = get_high_asst_width(&cfg_assrt_dur); + + if (cfg_assrt_dur.pm_pwr_cyc_dur >= high_asst_width) + return pm_pwr_cyc_dur; + + printk(BIOS_DEBUG, + "Set PmPwrCycDur to 4s as configured PmPwrCycDur(%d) violates PCH EDS " + "spec\n", pm_pwr_cyc_dur); + + return PCH_PM_PWR_CYC_DUR; +} + /* UPD parameters to be initialized before SiliconInit */ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) { @@ -219,6 +337,22 @@ /* Provide correct UART number for FSP debug logs */ params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE; + /* Apply minimum assertion width settings if non-zero */ + if (config->PchPmSlpS3MinAssert) + params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert; + if (config->PchPmSlpS4MinAssert) + params->PchPmSlpS4MinAssert = config->PchPmSlpS4MinAssert; + if (config->PchPmSlpSusMinAssert) + params->PchPmSlpSusMinAssert = config->PchPmSlpSusMinAssert; + if (config->PchPmSlpAMinAssert) + params->PchPmSlpAMinAssert = config->PchPmSlpAMinAssert; + + /* Set Power Cycle Duration */ + if (config->PchPmPwrCycDur) + params->PchPmPwrCycDur = get_pm_pwr_cyc_dur(config->PchPmSlpS4MinAssert, + config->PchPmSlpS3MinAssert, config->PchPmSlpAMinAssert, + config->PchPmPwrCycDur); + /* Override/Fill FSP Silicon Param for mainboard */ mainboard_silicon_init_params(params); } -- To view, visit https://review.coreboot.org/c/coreboot/+/43791 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I042e8e34b7dfda3bc21e5f2e6727cb7692ffc7f7 Gerrit-Change-Number: 43791 Gerrit-PatchSet: 1 Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020