coreboot-gerrit August 2020

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Change in coreboot[master]: crossgcc: Upgrade nasm to version 2.15.01
by HAOUAS Elyes (Code Review) 17 Aug '20

17 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42855 ) Change subject: crossgcc: Upgrade nasm to version 2.15.01 ...................................................................... crossgcc: Upgrade nasm to version 2.15.01 Change-Id: I4b38595cef72053f82216df43f3667abed4c1989 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum A util/crossgcc/sum/nasm-2.15.01.tar.bz2.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/42855/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e7ef9b3..d9e5a0b 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -46,7 +46,7 @@ # CLANG version number CLANG_VERSION=9.0.0 CMAKE_VERSION=3.16.2 -NASM_VERSION=2.14.02 +NASM_VERSION=2.15.01 # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if diff --git a/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum b/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum deleted file mode 100644 index f3b9de9..0000000 --- a/util/crossgcc/sum/nasm-2.14.02.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -fe098ee4dc9c4c983696c4948e64b23e4098b92b tarballs/nasm-2.14.02.tar.bz2 diff --git a/util/crossgcc/sum/nasm-2.15.01.tar.bz2.cksum b/util/crossgcc/sum/nasm-2.15.01.tar.bz2.cksum new file mode 100644 index 0000000..6d3db72 --- /dev/null +++ b/util/crossgcc/sum/nasm-2.15.01.tar.bz2.cksum @@ -0,0 +1 @@ +daba663a7f4d7bf475a104c44b8e8329f76b009d tarballs/nasm-2.15.01.tar.bz2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42855 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4b38595cef72053f82216df43f3667abed4c1989 Gerrit-Change-Number: 42855 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: crossgcc: Upgrade binutils to version 2.34
by HAOUAS Elyes (Code Review) 17 Aug '20

17 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38666 ) Change subject: crossgcc: Upgrade binutils to version 2.34 ...................................................................... crossgcc: Upgrade binutils to version 2.34 Change-Id: I0ad01e5da34c96fee6a9b1a63897a9fb28471c75 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/binutils-2.34_as-ipxe.patch R util/crossgcc/patches/binutils-2.34_mips-gold.patch R util/crossgcc/patches/binutils-2.34_no-bfd-doc.patch D util/crossgcc/sum/binutils-2.33.1.tar.xz.cksum A util/crossgcc/sum/binutils-2.34.tar.xz.cksum 6 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/38666/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index ab2ea89..334c7b7 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -52,7 +52,7 @@ MPC_VERSION=1.1.0 GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 -BINUTILS_VERSION=2.33.1 +BINUTILS_VERSION=2.34 GDB_VERSION=8.3.1 # Conflicting use of _ADR and _HID in coreboot tree needs diff --git a/util/crossgcc/patches/binutils-2.33.1_as-ipxe.patch b/util/crossgcc/patches/binutils-2.34_as-ipxe.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.33.1_as-ipxe.patch rename to util/crossgcc/patches/binutils-2.34_as-ipxe.patch diff --git a/util/crossgcc/patches/binutils-2.33.1_mips-gold.patch b/util/crossgcc/patches/binutils-2.34_mips-gold.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.33.1_mips-gold.patch rename to util/crossgcc/patches/binutils-2.34_mips-gold.patch diff --git a/util/crossgcc/patches/binutils-2.33.1_no-bfd-doc.patch b/util/crossgcc/patches/binutils-2.34_no-bfd-doc.patch similarity index 100% rename from util/crossgcc/patches/binutils-2.33.1_no-bfd-doc.patch rename to util/crossgcc/patches/binutils-2.34_no-bfd-doc.patch diff --git a/util/crossgcc/sum/binutils-2.33.1.tar.xz.cksum b/util/crossgcc/sum/binutils-2.33.1.tar.xz.cksum deleted file mode 100644 index 3a2f076..0000000 --- a/util/crossgcc/sum/binutils-2.33.1.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -06598868f5fa8efc98427dcb790d42c664f1a1a4 tarballs/binutils-2.33.1.tar.xz diff --git a/util/crossgcc/sum/binutils-2.34.tar.xz.cksum b/util/crossgcc/sum/binutils-2.34.tar.xz.cksum new file mode 100644 index 0000000..ea25ae8 --- /dev/null +++ b/util/crossgcc/sum/binutils-2.34.tar.xz.cksum @@ -0,0 +1 @@ +78f7ba4c0775ae75f5b906dc9af03d70b39b0785 tarballs/binutils-2.34.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/38666 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ad01e5da34c96fee6a9b1a63897a9fb28471c75 Gerrit-Change-Number: 38666 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: crossgcc: Update MPFR to version 4.1.0
by HAOUAS Elyes (Code Review) 17 Aug '20

17 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43360 ) Change subject: crossgcc: Update MPFR to version 4.1.0 ...................................................................... crossgcc: Update MPFR to version 4.1.0 Change-Id: I1df2c952229056b44d4c618cebe774ea27b55bd1 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/mpfr-4.0.2.tar.xz.cksum A util/crossgcc/sum/mpfr-4.1.0.tar.xz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/43360/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index cbf3b39..54c8818 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -34,7 +34,7 @@ # GCC toolchain version numbers GMP_VERSION=6.2.0 -MPFR_VERSION=4.0.2 +MPFR_VERSION=4.1.0 MPC_VERSION=1.1.0 GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 diff --git a/util/crossgcc/sum/mpfr-4.0.2.tar.xz.cksum b/util/crossgcc/sum/mpfr-4.0.2.tar.xz.cksum deleted file mode 100644 index 62ede96..0000000 --- a/util/crossgcc/sum/mpfr-4.0.2.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -52c1f2a4c9a202f46cf3275a8d46b562aa584208 tarballs/mpfr-4.0.2.tar.xz diff --git a/util/crossgcc/sum/mpfr-4.1.0.tar.xz.cksum b/util/crossgcc/sum/mpfr-4.1.0.tar.xz.cksum new file mode 100644 index 0000000..b4fcdf7 --- /dev/null +++ b/util/crossgcc/sum/mpfr-4.1.0.tar.xz.cksum @@ -0,0 +1 @@ +159c3a58705662bfde4dc93f2617f3660855ead6 tarballs/mpfr-4.1.0.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/43360 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1df2c952229056b44d4c618cebe774ea27b55bd1 Gerrit-Change-Number: 43360 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Change in coreboot[master]: crossgcc: Upgrade GMP to v6.2.0
by HAOUAS Elyes (Code Review) 17 Aug '20

17 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38465 ) Change subject: crossgcc: Upgrade GMP to v6.2.0 ...................................................................... crossgcc: Upgrade GMP to v6.2.0 gmp_freebsd-configure.patch is integrated in upstream so we don't need them anymore. Change-Id: I8404872f1b65e9173c1fcbd24d7da7bdd7937503 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/gmp-6.1.2_freebsd-configure.patch D util/crossgcc/sum/gmp-6.1.2.tar.xz.cksum A util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum 4 files changed, 2 insertions(+), 22 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/38465/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index ab2ea89..c9609e0 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -47,7 +47,7 @@ THREADS=1 # GCC toolchain version numbers -GMP_VERSION=6.1.2 +GMP_VERSION=6.2.0 MPFR_VERSION=4.0.2 MPC_VERSION=1.1.0 GCC_VERSION=8.3.0 diff --git a/util/crossgcc/patches/gmp-6.1.2_freebsd-configure.patch b/util/crossgcc/patches/gmp-6.1.2_freebsd-configure.patch deleted file mode 100644 index 5770af6..0000000 --- a/util/crossgcc/patches/gmp-6.1.2_freebsd-configure.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- gmp-6.1.2.orig/configure 2016-12-16 16:45:32.000000000 +0100 -+++ gmp-6.1.2/configure 2017-03-08 14:26:11.194245000 +0100 -@@ -6776,7 +6776,7 @@ - long i; - for (i = 0; i < 88 + 1; i++) - a[i] = ~0L; -- r = malloc (10000 * sizeof (unsigned long)); -+ r = calloc (10000, sizeof (unsigned long)); - r2 = r; - for (i = 0; i < 528; i += 23) - { -@@ -8394,7 +8394,7 @@ - long i; - for (i = 0; i < 88 + 1; i++) - a[i] = ~0L; -- r = malloc (10000 * sizeof (unsigned long)); -+ r = calloc (10000, sizeof (unsigned long)); - r2 = r; - for (i = 0; i < 528; i += 23) - { diff --git a/util/crossgcc/sum/gmp-6.1.2.tar.xz.cksum b/util/crossgcc/sum/gmp-6.1.2.tar.xz.cksum deleted file mode 100644 index 774658c..0000000 --- a/util/crossgcc/sum/gmp-6.1.2.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -9dc6981197a7d92f339192eea974f5eca48fcffe tarballs/gmp-6.1.2.tar.xz diff --git a/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum b/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum new file mode 100644 index 0000000..b00b669 --- /dev/null +++ b/util/crossgcc/sum/gmp-6.2.0.tar.xz.cksum @@ -0,0 +1 @@ +052a5411dc74054240eec58132d2cf41211d0ff6 tarballs/gmp-6.2.0.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/38465 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8404872f1b65e9173c1fcbd24d7da7bdd7937503 Gerrit-Change-Number: 38465 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel: Use PCI_BASE_ADDRESS_0 macro instead of magic number
by HAOUAS Elyes (Code Review) 17 Aug '20

17 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44371 ) Change subject: sb/intel: Use PCI_BASE_ADDRESS_0 macro instead of magic number ...................................................................... sb/intel: Use PCI_BASE_ADDRESS_0 macro instead of magic number Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/common/pciehp.c M src/southbridge/intel/i82801gx/usb_ehci.c M src/southbridge/intel/ibexpeak/thermal.c 3 files changed, 6 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/44371/1 diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c index 5556aba..247bf5d 100644 --- a/src/southbridge/intel/common/pciehp.c +++ b/src/southbridge/intel/common/pciehp.c @@ -5,6 +5,7 @@ #include <acpi/acpigen.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_def.h> #include "pciehp.h" @@ -121,7 +122,7 @@ { struct resource *resource; - resource = new_resource(dev, 0x10); + resource = new_resource(dev, PCI_BASE_ADDRESS_0); resource->size = 1 << 23; resource->align = 22; resource->gran = 22; diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c index 0a66136..b01af96 100644 --- a/src/southbridge/intel/i82801gx/usb_ehci.c +++ b/src/southbridge/intel/i82801gx/usb_ehci.c @@ -7,6 +7,7 @@ #include "i82801gx.h" #include <device/pci_ehci.h> #include <device/mmio.h> +#include <device/pci_def.h> #include <device/pci_ops.h> static void usb_ehci_init(struct device *dev) @@ -23,7 +24,7 @@ pci_update_config32(dev, 0xfc, ~(3 << 2), (2 << 2) | (1 << 29) | (1 << 17)); /* Clear any pending port changes */ - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); base = res2mmio(res, 0, 0); reg32 = read32(base + 0x24) | (1 << 2); write32(base + 0x24, reg32); diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c index 0b496da..142d3c7 100644 --- a/src/southbridge/intel/ibexpeak/thermal.c +++ b/src/southbridge/intel/ibexpeak/thermal.c @@ -3,6 +3,7 @@ #include <console/console.h> #include <device/device.h> #include <device/pci.h> +#include <device/pci_def.h> #include <device/pci_ids.h> #include "pch.h" #include <device/mmio.h> @@ -13,7 +14,7 @@ u8 *base; printk(BIOS_DEBUG, "Thermal init start.\n"); - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/44371 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c Gerrit-Change-Number: 44371 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: {soc/intel/common,sb/intel/lynxpoint}/hda_verb.c: Reduce differences
by HAOUAS Elyes (Code Review) 17 Aug '20

17 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44392 ) Change subject: {soc/intel/common,sb/intel/lynxpoint}/hda_verb.c: Reduce differences ...................................................................... {soc/intel/common,sb/intel/lynxpoint}/hda_verb.c: Reduce differences Change-Id: Ie63d7671eb19f0d4c4f67dfe242193e7949afdea Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/common/hda_verb.c M src/southbridge/intel/lynxpoint/hda_verb.c 2 files changed, 29 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/44392/1 diff --git a/src/soc/intel/common/hda_verb.c b/src/soc/intel/common/hda_verb.c index 6c0ace7..80ac489 100644 --- a/src/soc/intel/common/hda_verb.c +++ b/src/soc/intel/common/hda_verb.c @@ -22,9 +22,7 @@ reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -83,18 +81,16 @@ } /* - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int hda_wait_for_ready(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); + u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; udelay(1); @@ -104,27 +100,23 @@ } /* - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int hda_wait_for_valid(u8 *base) { u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ + int timeout = 50; /* Send the verb to the codec */ reg32 = read32(base + HDA_ICII_REG); reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - - int timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } diff --git a/src/southbridge/intel/lynxpoint/hda_verb.c b/src/southbridge/intel/lynxpoint/hda_verb.c index 6017d56..85fde86 100644 --- a/src/southbridge/intel/lynxpoint/hda_verb.c +++ b/src/southbridge/intel/lynxpoint/hda_verb.c @@ -4,10 +4,11 @@ #include <device/azalia_device.h> #include <device/mmio.h> #include <delay.h> + #include "pch.h" #include "hda_verb.h" -/** +/* * Set bits in a register and wait for status */ static int set_bits(void *port, u32 mask, u32 val) @@ -22,9 +23,7 @@ reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -39,7 +38,7 @@ return 0; } -/** +/* * Probe for supported codecs */ int hda_codec_detect(u8 *base) @@ -69,19 +68,17 @@ return 0; } -/** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative +/* + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int hda_wait_for_ready(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); + u32 reg32 = read32(base + HDA_ICII_REG); if (!(reg32 & HDA_ICII_BUSY)) return 0; udelay(1); @@ -90,28 +87,24 @@ return -1; } -/** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative +/* + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int hda_wait_for_valid(u8 *base) { u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ + int timeout = 50; /* Send the verb to the codec */ reg32 = read32(base + HDA_ICII_REG); reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - - int timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } @@ -119,7 +112,7 @@ return -1; } -/** +/* * Find a specific entry within a verb table * * @param verb_table_bytes: verb table size in bytes @@ -148,7 +141,7 @@ const u32 *verb_table_data, u32 viddid, const u32 **verb) { - int idx=0; + int idx = 0; while (idx < (verb_table_bytes / sizeof(u32))) { u32 verb_size = 4 * verb_table_data[idx+2]; // in u32 @@ -164,7 +157,7 @@ return 0; } -/** +/* * Write a supplied verb table */ int hda_codec_write(u8 *base, u32 size, const u32 *data) @@ -184,7 +177,7 @@ return 0; } -/** +/* * Initialize codec, then find the verb table and write it */ int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data) -- To view, visit https://review.coreboot.org/c/coreboot/+/44392 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie63d7671eb19f0d4c4f67dfe242193e7949afdea Gerrit-Change-Number: 44392 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: {sb/intel/*/azalia.c,device/azalia_device.c}: Reduce the difference
by HAOUAS Elyes (Code Review) 17 Aug '20

17 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44370 ) Change subject: {sb/intel/*/azalia.c,device/azalia_device.c}: Reduce the difference ...................................................................... {sb/intel/*/azalia.c,device/azalia_device.c}: Reduce the difference Change-Id: Ia64e0ba10f145cf2eae0cb2ff4951b1455963d5d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/device/azalia_device.c M src/southbridge/intel/bd82x6x/azalia.c M src/southbridge/intel/i82801gx/azalia.c M src/southbridge/intel/i82801ix/azalia.c M src/southbridge/intel/i82801jx/azalia.c M src/southbridge/intel/ibexpeak/azalia.c 6 files changed, 117 insertions(+), 121 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44370/1 diff --git a/src/device/azalia_device.c b/src/device/azalia_device.c index bd35c8e..7b10d41 100644 --- a/src/device/azalia_device.c +++ b/src/device/azalia_device.c @@ -19,9 +19,7 @@ reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -109,15 +107,13 @@ } /** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 50; while (timeout--) { @@ -131,28 +127,28 @@ } /** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) { - /* Use a 50 usec timeout - the Linux kernel uses the - * same duration */ - + u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ int timeout = 25; - write32(base + HDA_ICII_REG, - HDA_ICII_VALID | HDA_ICII_BUSY); + /* Send the verb to the codec */ + reg32 = read32(base + HDA_ICII_REG); + reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; + write32(base + HDA_ICII_REG, reg32); + while (timeout--) { udelay(1); } timeout = 50; while (timeout--) { - u32 reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + reg32 = read32(base + HDA_ICII_REG); + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } @@ -170,14 +166,18 @@ printk(BIOS_DEBUG, "azalia_audio: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) == -1) { + printk(BIOS_DEBUG, " codec not ready.\n"); return; + } reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) == -1) { + printk(BIOS_DEBUG, " codec not valid.\n"); return; + } reg32 = read32(base + HDA_IR_REG); @@ -220,19 +220,18 @@ struct resource *res; u32 codec_mask; - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - // NOTE this will break as soon as the azalia_audio get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the azalia_audio get's a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "azalia_audio: base = %p\n", base); codec_mask = codec_detect(base); if (codec_mask) { - printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", - codec_mask); + printk(BIOS_DEBUG, "azalia_audio: codec_mask = %02x\n", codec_mask); codecs_init(dev, base, codec_mask); } } diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 3d4f7ca..056cd77 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -26,9 +26,7 @@ reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -52,10 +50,9 @@ goto no_codec; /* Write back the value once reset bit is set. */ - write16(base + HDA_GCAP_REG, - read16(base + HDA_GCAP_REG)); + write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); - /* Read in Codec location (BAR + 0xe)[2..0]*/ + /* Read in Codec location (BAR + 0xe)[2..0] */ reg8 = read8(base + HDA_STATESTS_REG); reg8 &= 0x0f; if (!reg8) @@ -73,15 +70,15 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) { - int idx=0; + int idx = 0; while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header + idx += verb_size + 3; // skip verb + header continue; } - *verb = &cim_verb_data[idx+3]; + *verb = &cim_verb_data[idx + 3]; return verb_size; } @@ -90,14 +87,13 @@ } /** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) { /* Use a 1msec timeout */ - int timeout = 1000; while (timeout--) { @@ -111,27 +107,24 @@ } /** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) { u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ + int timeout = 1000; /* Send the verb to the codec */ reg32 = read32(base + HDA_ICII_REG); reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - /* Use a 1msec timeout */ - - int timeout = 1000; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } @@ -213,13 +206,12 @@ u32 codec_mask; u32 reg32; - /* Find base address */ res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the azalia_audio get's a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index add9069..32e58c8 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -50,7 +50,7 @@ if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1) goto no_codec; - /* Read in Codec location (BAR + 0xe)[2..0]*/ + /* Read in Codec location (BAR + 0xe)[2..0] */ reg32 = read32(base + HDA_STATESTS_REG); reg32 &= 0x0f; if (!reg32) @@ -71,12 +71,12 @@ int idx = 0; while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header + idx += verb_size + 3; // skip verb + header continue; } - *verb = &cim_verb_data[idx+3]; + *verb = &cim_verb_data[idx + 3]; return verb_size; } @@ -85,8 +85,8 @@ } /** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) @@ -105,22 +105,21 @@ } /** - * Wait 50usec for the codec to indicate that it accepted the previous command. - * No response would imply that the code is non-operative. + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) { u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ + int timeout = 50; /* Send the verb to the codec */ reg32 = read32(base + HDA_ICII_REG); reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - - int timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) @@ -141,14 +140,18 @@ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) == -1) { + printk(BIOS_DEBUG, " codec not ready.\n"); return; + } reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) == -1) { + printk(BIOS_DEBUG, " codec not valid.\n"); return; + } reg32 = read32(base + HDA_IR_REG); @@ -178,6 +181,7 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; + for (i = 2; i >= 0; i--) { if (codec_mask & (1 << i)) codec_init(dev, base, i); @@ -230,12 +234,12 @@ // Docking not supported pci_and_config8(dev, 0x4d, (u8)~(1 << 7)); // Docking Status - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the azalia_audio get's a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); codec_mask = codec_detect(base); diff --git a/src/southbridge/intel/i82801ix/azalia.c b/src/southbridge/intel/i82801ix/azalia.c index f0c00b6..71ee01d 100644 --- a/src/southbridge/intel/i82801ix/azalia.c +++ b/src/southbridge/intel/i82801ix/azalia.c @@ -50,7 +50,7 @@ if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1) goto no_codec; - /* Read in Codec location (BAR + 0xe)[2..0]*/ + /* Read in Codec location (BAR + 0xe)[2..0] */ reg32 = read32(base + HDA_STATESTS_REG); reg32 &= 0x0f; if (!reg32) @@ -71,12 +71,12 @@ int idx = 0; while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header + idx += verb_size + 3; // skip verb + header continue; } - *verb = &cim_verb_data[idx+3]; + *verb = &cim_verb_data[idx + 3]; return verb_size; } @@ -85,8 +85,8 @@ } /** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) @@ -105,22 +105,21 @@ } /** - * Wait 50usec for the codec to indicate that it accepted the previous command. - * No response would imply that the code is non-operative. + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) { u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ + int timeout = 50; /* Send the verb to the codec */ reg32 = read32(base + HDA_ICII_REG); reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - - int timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) @@ -141,14 +140,18 @@ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) == -1) { + printk(BIOS_DEBUG, " codec not ready.\n"); return; + } reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) == -1) { + printk(BIOS_DEBUG, " codec not valid.\n"); return; + } reg32 = read32(base + HDA_IR_REG); @@ -178,6 +181,7 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; + for (i = 2; i >= 0; i--) { if (codec_mask & (1 << i)) codec_init(dev, base, i); @@ -224,12 +228,12 @@ /* Lock some R/WO bits by writing their current value. */ pci_update_config32(dev, 0x74, ~0, 0); - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the azalia_audio get's a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); codec_mask = codec_detect(base); diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index b53d641..aedd748 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -50,7 +50,7 @@ if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1) goto no_codec; - /* Read in Codec location (BAR + 0xe)[2..0]*/ + /* Read in Codec location (BAR + 0xe)[2..0] */ reg32 = read32(base + HDA_STATESTS_REG); reg32 &= 0x0f; if (!reg32) @@ -71,12 +71,12 @@ int idx = 0; while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header + idx += verb_size + 3; // skip verb + header continue; } - *verb = &cim_verb_data[idx+3]; + *verb = &cim_verb_data[idx + 3]; return verb_size; } @@ -85,8 +85,8 @@ } /** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) @@ -105,22 +105,21 @@ } /** - * Wait 50usec for the codec to indicate that it accepted the previous command. - * No response would imply that the code is non-operative. + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) { u32 reg32; + /* Use a 50 usec timeout - the Linux kernel uses the same duration */ + int timeout = 50; /* Send the verb to the codec */ reg32 = read32(base + HDA_ICII_REG); reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - /* Use a 50 usec timeout - the Linux kernel uses the same duration */ - - int timeout = 50; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) @@ -141,14 +140,18 @@ printk(BIOS_DEBUG, "Azalia: Initializing codec #%d\n", addr); /* 1 */ - if (wait_for_ready(base) == -1) + if (wait_for_ready(base) == -1) { + printk(BIOS_DEBUG, " codec not ready.\n"); return; + } reg32 = (addr << 28) | 0x000f0000; write32(base + HDA_IC_REG, reg32); - if (wait_for_valid(base) == -1) + if (wait_for_valid(base) == -1) { + printk(BIOS_DEBUG, " codec not valid.\n"); return; + } reg32 = read32(base + HDA_IR_REG); @@ -178,6 +181,7 @@ static void codecs_init(struct device *dev, u8 *base, u32 codec_mask) { int i; + for (i = 2; i >= 0; i--) { if (codec_mask & (1 << i)) codec_init(dev, base, i); @@ -224,12 +228,12 @@ /* Lock some R/WO bits by writing their current value. */ pci_update_config32(dev, 0x74, ~0, 0); - res = find_resource(dev, 0x10); + res = find_resource(dev, PCI_BASE_ADDRESS_0); if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the azalia_audio get's a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %p\n", base); codec_mask = codec_detect(base); diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 47d595c..acac6a9 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -22,9 +22,7 @@ reg32 |= val; write32(port, reg32); - /* Wait for readback of register to - * match what was just written to it - */ + /* Wait for readback of register to match what was just written to it */ count = 50; do { /* Wait 1ms based on BKDG wait time */ @@ -48,10 +46,9 @@ goto no_codec; /* Write back the value once reset bit is set. */ - write16(base + HDA_GCAP_REG, - read16(base + HDA_GCAP_REG)); + write16(base + HDA_GCAP_REG, read16(base + HDA_GCAP_REG)); - /* Read in Codec location (BAR + 0xe)[2..0]*/ + /* Read in Codec location (BAR + 0xe)[2..0] */ reg8 = read8(base + HDA_STATESTS_REG); reg8 &= 0x0f; if (!reg8) @@ -69,15 +66,15 @@ static u32 find_verb(struct device *dev, u32 viddid, const u32 **verb) { - int idx=0; + int idx = 0; while (idx < (cim_verb_data_size / sizeof(u32))) { - u32 verb_size = 4 * cim_verb_data[idx+2]; // in u32 + u32 verb_size = 4 * cim_verb_data[idx + 2]; // in u32 if (cim_verb_data[idx] != viddid) { - idx += verb_size + 3; // skip verb + header + idx += verb_size + 3; // skip verb + header continue; } - *verb = &cim_verb_data[idx+3]; + *verb = &cim_verb_data[idx + 3]; return verb_size; } @@ -86,14 +83,13 @@ } /** - * Wait 50usec for the codec to indicate it is ready - * no response would imply that the codec is non-operative + * Wait 50usec for the codec to indicate it is ready. + * No response would imply that the codec is non-operative. */ static int wait_for_ready(u8 *base) { /* Use a 1msec timeout */ - int timeout = 1000; while (timeout--) { @@ -107,27 +103,24 @@ } /** - * Wait 50usec for the codec to indicate that it accepted - * the previous command. No response would imply that the code - * is non-operative + * Wait 50usec for the codec to indicate that it accepted the previous command. + * No response would imply that the code is non-operative. */ static int wait_for_valid(u8 *base) { u32 reg32; + /* Use a 1msec timeout */ + int timeout = 1000; /* Send the verb to the codec */ reg32 = read32(base + HDA_ICII_REG); reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; write32(base + HDA_ICII_REG, reg32); - /* Use a 1msec timeout */ - - int timeout = 1000; while (timeout--) { reg32 = read32(base + HDA_ICII_REG); - if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == - HDA_ICII_VALID) + if ((reg32 & (HDA_ICII_VALID | HDA_ICII_BUSY)) == HDA_ICII_VALID) return 0; udelay(1); } @@ -216,8 +209,8 @@ if (!res) return; - // NOTE this will break as soon as the Azalia get's a bar above - // 4G. Is there anything we can do about it? + // NOTE this will break as soon as the azalia_audio get's a bar above 4G. + // Is there anything we can do about it? base = res2mmio(res, 0, 0); printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); -- To view, visit https://review.coreboot.org/c/coreboot/+/44370 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia64e0ba10f145cf2eae0cb2ff4951b1455963d5d Gerrit-Change-Number: 44370 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

5 17

Change in coreboot[master]: mb/google/zork: add dptc interface support
by chris wang (Code Review) 17 Aug '20

17 Aug '20

Hello Chris Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44264 to review the following change. Change subject: mb/google/zork: add dptc interface support ...................................................................... mb/google/zork: add dptc interface support add dptc support for tablet/clamshell mode Profile 0 : clamshell mode Profile 1 : Tablet mode BUG=b:157943445 BRANCH=none TEST=Build. check the setting changed. Change-Id: I8f952d41ee90f0fdd0ecff9a4d50201f9ee9ce7c Signed-off-by: Chris Wang <chris.wang(a)amd.corp-partner.google.com> --- M src/mainboard/google/zork/dsdt.asl A src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/dptc.asl A src/mainboard/google/zork/variants/berknip/include/variant/acpi/dptc.asl A src/mainboard/google/zork/variants/dalboz/include/variant/acpi/dptc.asl A src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/dptc.asl A src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/dptc.asl A src/mainboard/google/zork/variants/morphius/include/variant/acpi/dptc.asl A src/mainboard/google/zork/variants/trembyle/include/variant/acpi/dptc.asl A src/mainboard/google/zork/variants/vilboz/include/variant/acpi/dptc.asl A src/mainboard/google/zork/variants/woomax/include/variant/acpi/dptc.asl 10 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/44264/1 diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl index 08ea5cf..2dc456d 100644 --- a/src/mainboard/google/zork/dsdt.asl +++ b/src/mainboard/google/zork/dsdt.asl @@ -35,6 +35,8 @@ /* global utility methods expected within the \_SB scope */ #include <arch/x86/acpi/globutil.asl> + #include <variant/acpi/dptc.asl> + /* Describe the SOC */ #include <soc.asl> diff --git a/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/dptc.asl b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/dptc.asl new file mode 100644 index 0000000..6732b24 --- /dev/null +++ b/src/mainboard/google/zork/variants/baseboard/include/baseboard/acpi/dptc.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define DPTC_CTDP 0x0 +#define DPTC_STAPM_TIME_CONSTANT 0x1 +#define DPTC_SKIN_CONTROL_SCALAR 0x2 +#define DPTC_THERMAL_CONTROL_LIMIT 0x3 +#define DPTC_PACKAGE_POWER_LIMIT 0x4 +#define DPTC_SUSTAINED_POWER_LIMIT 0x5 +#define DPTC_FAST_PPT_LIMIT 0x6 +#define DPTC_SLOW_PPT_LIMIT 0x7 +#define DPTC_SLOW_PPT_TIME_CONSTANT 0x8 +#define DPTC_PROCHOT_L 0x9 +#define DPTC_SYS_TEMP_TRACKING 0xa +#define DPTC_VRM_CURRENT_LIMIT 0xb +#define DPTC_VRM_MAXIMUM_CURRENT_LIMIT 0xc +#define DPTC_VRM_LOW_POWER_THRESHOLD 0xd +#define DPTC_VRM_SOC_CURRENT_LIMIT 0xe +#define DPTC_VRM_SOC_LOW_POWER_THRESHOLD 0xf +#define DPTC_DGPU_CONTROL 0x10 + +External(\_SB.ALIB, MethodObj) + +Method(POF0, 0, Serialized) { + return +} + +Method(POF1, 0, Serialized) { + return +} diff --git a/src/mainboard/google/zork/variants/berknip/include/variant/acpi/dptc.asl b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/dptc.asl new file mode 100644 index 0000000..6eab4db --- /dev/null +++ b/src/mainboard/google/zork/variants/berknip/include/variant/acpi/dptc.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptc.asl> + diff --git a/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/dptc.asl b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/dptc.asl new file mode 100644 index 0000000..6eab4db --- /dev/null +++ b/src/mainboard/google/zork/variants/dalboz/include/variant/acpi/dptc.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptc.asl> + diff --git a/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/dptc.asl b/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/dptc.asl new file mode 100644 index 0000000..6eab4db --- /dev/null +++ b/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/dptc.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptc.asl> + diff --git a/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/dptc.asl b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/dptc.asl new file mode 100644 index 0000000..6eab4db --- /dev/null +++ b/src/mainboard/google/zork/variants/ezkinil/include/variant/acpi/dptc.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptc.asl> + diff --git a/src/mainboard/google/zork/variants/morphius/include/variant/acpi/dptc.asl b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/dptc.asl new file mode 100644 index 0000000..6eab4db --- /dev/null +++ b/src/mainboard/google/zork/variants/morphius/include/variant/acpi/dptc.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptc.asl> + diff --git a/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/dptc.asl b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/dptc.asl new file mode 100644 index 0000000..6eab4db --- /dev/null +++ b/src/mainboard/google/zork/variants/trembyle/include/variant/acpi/dptc.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptc.asl> + diff --git a/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/dptc.asl b/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/dptc.asl new file mode 100644 index 0000000..6eab4db --- /dev/null +++ b/src/mainboard/google/zork/variants/vilboz/include/variant/acpi/dptc.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptc.asl> + diff --git a/src/mainboard/google/zork/variants/woomax/include/variant/acpi/dptc.asl b/src/mainboard/google/zork/variants/woomax/include/variant/acpi/dptc.asl new file mode 100644 index 0000000..6eab4db --- /dev/null +++ b/src/mainboard/google/zork/variants/woomax/include/variant/acpi/dptc.asl @@ -0,0 +1,4 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/acpi/dptc.asl> + -- To view, visit https://review.coreboot.org/c/coreboot/+/44264 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8f952d41ee90f0fdd0ecff9a4d50201f9ee9ce7c Gerrit-Change-Number: 44264 Gerrit-PatchSet: 1 Gerrit-Owner: chris wang <Chris.Wang(a)amd.com> Gerrit-Reviewer: Chris Wang <chris.wang(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/ibexpeak: Use <device/azalia_device.h> registers
by HAOUAS Elyes (Code Review) 17 Aug '20

17 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44131 ) Change subject: sb/intel/ibexpeak: Use <device/azalia_device.h> registers ...................................................................... sb/intel/ibexpeak: Use <device/azalia_device.h> registers Change-Id: Ic257a11ec2a2f8b1809ed40ae0f9468574dfd009 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/ibexpeak/azalia.c 1 file changed, 12 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/44131/1 diff --git a/src/southbridge/intel/ibexpeak/azalia.c b/src/southbridge/intel/ibexpeak/azalia.c index 59a384a..47d595c 100644 --- a/src/southbridge/intel/ibexpeak/azalia.c +++ b/src/southbridge/intel/ibexpeak/azalia.c @@ -10,10 +10,6 @@ #include <device/azalia_device.h> #include "pch.h" -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -48,15 +44,15 @@ u8 reg8; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1) goto no_codec; /* Write back the value once reset bit is set. */ - write16(base + 0x0, - read16(base + 0x0)); + write16(base + HDA_GCAP_REG, + read16(base + HDA_GCAP_REG)); /* Read in Codec location (BAR + 0xe)[2..0]*/ - reg8 = read8(base + 0xe); + reg8 = read8(base + HDA_STATESTS_REG); reg8 &= 0x0f; if (!reg8) goto no_codec; @@ -66,7 +62,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } @@ -155,14 +151,14 @@ } reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32); if (wait_for_valid(base) == -1) { printk(BIOS_DEBUG, " codec not valid.\n"); return; } - reg32 = read32(base + 0x64); + reg32 = read32(base + HDA_IR_REG); /* 2 */ printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); @@ -179,7 +175,7 @@ if (wait_for_ready(base) == -1) return; - write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]); if (wait_for_valid(base) == -1) return; @@ -199,7 +195,7 @@ if (wait_for_ready(base) == -1) return; - write32(base + 0x60, pc_beep_verbs[i]); + write32(base + HDA_IC_REG, pc_beep_verbs[i]); if (wait_for_valid(base) == -1) return; @@ -268,9 +264,9 @@ /* Codec Initialization Programming Sequence */ /* Take controller out of reset */ - reg32 = read32(base + 0x08); - reg32 |= (1 << 0); - write32(base + 0x08, reg32); + reg32 = read32(base + HDA_GCTL_REG); + reg32 |= HDA_GCTL_CRST; + write32(base + HDA_GCTL_REG, reg32); /* Wait 1ms */ udelay(1000); -- To view, visit https://review.coreboot.org/c/coreboot/+/44131 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic257a11ec2a2f8b1809ed40ae0f9468574dfd009 Gerrit-Change-Number: 44131 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/i82801jx: Use <device/azalia_device.h> registers
by HAOUAS Elyes (Code Review) 17 Aug '20

17 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44130 ) Change subject: sb/intel/i82801jx: Use <device/azalia_device.h> registers ...................................................................... sb/intel/i82801jx: Use <device/azalia_device.h> registers Change-Id: Ic661a1339892dad668ad3f9e68cab70bf380505f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/i82801jx/azalia.c 1 file changed, 11 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44130/1 diff --git a/src/southbridge/intel/i82801jx/azalia.c b/src/southbridge/intel/i82801jx/azalia.c index ba20a6a..b53d641 100644 --- a/src/southbridge/intel/i82801jx/azalia.c +++ b/src/southbridge/intel/i82801jx/azalia.c @@ -11,10 +11,6 @@ #include "chip.h" #include "i82801jx.h" -#define HDA_ICII_REG 0x68 -#define HDA_ICII_BUSY (1 << 0) -#define HDA_ICII_VALID (1 << 1) - static int set_bits(void *port, u32 mask, u32 val) { u32 reg32; @@ -47,15 +43,15 @@ u32 reg32; /* Set Bit0 to 0 to enter reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 0) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 0) == -1) goto no_codec; /* Set Bit 0 to 1 to exit reset state (BAR + 0x8)[0] */ - if (set_bits(base + 0x08, 1, 1) == -1) + if (set_bits(base + HDA_GCTL_REG, 1, 1) == -1) goto no_codec; /* Read in Codec location (BAR + 0xe)[2..0]*/ - reg32 = read32(base + 0xe); + reg32 = read32(base + HDA_STATESTS_REG); reg32 &= 0x0f; if (!reg32) goto no_codec; @@ -65,7 +61,7 @@ no_codec: /* Codec Not found */ /* Put HDA back in reset (BAR + 0x8) [0] */ - set_bits(base + 0x08, 1, 0); + set_bits(base + HDA_GCTL_REG, 1, 0); printk(BIOS_DEBUG, "Azalia: No codec!\n"); return 0; } @@ -118,9 +114,9 @@ u32 reg32; /* Send the verb to the codec */ - reg32 = read32(base + 0x68); - reg32 |= (1 << 0) | (1 << 1); - write32(base + 0x68, reg32); + reg32 = read32(base + HDA_ICII_REG); + reg32 |= HDA_ICII_BUSY | HDA_ICII_VALID; + write32(base + HDA_ICII_REG, reg32); /* Use a 50 usec timeout - the Linux kernel uses the same duration */ @@ -149,12 +145,12 @@ return; reg32 = (addr << 28) | 0x000f0000; - write32(base + 0x60, reg32); + write32(base + HDA_IC_REG, reg32); if (wait_for_valid(base) == -1) return; - reg32 = read32(base + 0x64); + reg32 = read32(base + HDA_IR_REG); /* 2 */ printk(BIOS_DEBUG, "Azalia: codec viddid: %08x\n", reg32); @@ -171,7 +167,7 @@ if (wait_for_ready(base) == -1) return; - write32(base + 0x60, verb[i]); + write32(base + HDA_IC_REG, verb[i]); if (wait_for_valid(base) == -1) return; @@ -191,7 +187,7 @@ if (wait_for_ready(base) == -1) return; - write32(base + 0x60, pc_beep_verbs[i]); + write32(base + HDA_IC_REG, pc_beep_verbs[i]); if (wait_for_valid(base) == -1) return; -- To view, visit https://review.coreboot.org/c/coreboot/+/44130 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic661a1339892dad668ad3f9e68cab70bf380505f Gerrit-Change-Number: 44130 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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