Change in coreboot[master]: sb/intel: Use PCI_BASE_ADDRESS_0 macro instead of magic number

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44371 )

Change subject: sb/intel: Use PCI_BASE_ADDRESS_0 macro instead of magic number
......................................................................

sb/intel: Use PCI_BASE_ADDRESS_0 macro instead of magic number

Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c
Signed-off-by: Elyes HAOUAS 
---
M src/southbridge/intel/common/pciehp.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/ibexpeak/thermal.c
3 files changed, 6 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/44371/1

diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c
index 5556aba..247bf5d 100644
--- a/src/southbridge/intel/common/pciehp.c
+++ b/src/southbridge/intel/common/pciehp.c
@@ -5,6 +5,7 @@
 #include <acpi/acpigen.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_def.h>

#include "pciehp.h"

@@ -121,7 +122,7 @@
 {
    struct resource *resource;

-	resource = new_resource(dev, 0x10);
+	resource = new_resource(dev, PCI_BASE_ADDRESS_0);
    resource->size = 1 << 23;
    resource->align = 22;
    resource->gran = 22;
diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c
index 0a66136..b01af96 100644
--- a/src/southbridge/intel/i82801gx/usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/usb_ehci.c
@@ -7,6 +7,7 @@
 #include "i82801gx.h"
 #include <device/pci_ehci.h>
 #include <device/mmio.h>
+#include <device/pci_def.h>
 #include <device/pci_ops.h>

static void usb_ehci_init(struct device *dev)
@@ -23,7 +24,7 @@
    pci_update_config32(dev, 0xfc, ~(3 << 2), (2 << 2) | (1 << 29) | (1 << 17));

/* Clear any pending port changes */
-	res = find_resource(dev, 0x10);
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
    base = res2mmio(res, 0, 0);
    reg32 = read32(base + 0x24) | (1 << 2);
    write32(base + 0x24, reg32);
diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c
index 0b496da..142d3c7 100644
--- a/src/southbridge/intel/ibexpeak/thermal.c
+++ b/src/southbridge/intel/ibexpeak/thermal.c
@@ -3,6 +3,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include "pch.h"
 #include <device/mmio.h>
@@ -13,7 +14,7 @@
    u8 *base;
    printk(BIOS_DEBUG, "Thermal init start.\n");

-	res = find_resource(dev, 0x10);
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
    if (!res)
    	return;

[HAOUAS Elyes (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44371

to look at the new patch set (#2).

Change subject: sb/intel: Use PCI_BASE_ADDRESS_0 macro instead of magic number
......................................................................

sb/intel: Use PCI_BASE_ADDRESS_0 macro instead of magic number

Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c
Signed-off-by: Elyes HAOUAS 
---
M src/southbridge/intel/common/pciehp.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/ibexpeak/thermal.c
3 files changed, 6 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/44371/2

Change in coreboot[master]: src: Use PCI_BASE_ADDRESS_* macros instead of magic number

[HAOUAS Elyes (Code Review)]

Hello build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44371

to look at the new patch set (#3).

Change subject: src: Use PCI_BASE_ADDRESS_* macros instead of magic number
......................................................................

src: Use PCI_BASE_ADDRESS_* macros instead of magic number

Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c
Signed-off-by: Elyes HAOUAS 
---
M src/drivers/aspeed/common/ast_main.c
M src/drivers/aspeed/common/ast_mode_corebootfb.c
M src/drivers/uart/oxpcie.c
M src/northbridge/intel/pineview/gma.c
M src/southbridge/intel/common/pciehp.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/ibexpeak/thermal.c
7 files changed, 16 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/44371/3

Change in coreboot[master]: src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers

[HAOUAS Elyes (Code Review)]

Hello build bot (Jenkins), Damien Zammit, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44371

to look at the new patch set (#4).

Change subject: src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers
......................................................................

src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers

Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c
Signed-off-by: Elyes HAOUAS 
---
M src/drivers/aspeed/common/ast_main.c
M src/drivers/aspeed/common/ast_mode_corebootfb.c
M src/drivers/uart/oxpcie.c
M src/northbridge/intel/pineview/gma.c
M src/southbridge/intel/common/pciehp.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/ibexpeak/thermal.c
7 files changed, 16 insertions(+), 10 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/44371/4

Change in coreboot[master]: src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers

[HAOUAS Elyes (Code Review)]

Hello build bot (Jenkins), Damien Zammit, Angel Pons, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44371

to look at the new patch set (#5).

Change subject: src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers
......................................................................

src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers

Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c
Signed-off-by: Elyes HAOUAS 
---
M src/drivers/aspeed/common/ast_main.c
M src/drivers/aspeed/common/ast_mode_corebootfb.c
M src/drivers/uart/oxpcie.c
M src/northbridge/intel/pineview/gma.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/common/pciehp.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
12 files changed, 35 insertions(+), 24 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/44371/5

Change in coreboot[master]: src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers

[Patrick Rudolph (Code Review)]

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44371 )

Change subject: src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers
......................................................................

Patch Set 6: Code-Review+2

Change in coreboot[master]: src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44371 )

Change subject: src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers
......................................................................

src: Use PCI_BASE_ADDRESS_* macros instead of magic numbers

Change-Id: Id3390c5ac6a9517ffc2d202f41802e6f4d2e314c
Signed-off-by: Elyes HAOUAS 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44371
Reviewed-by: Patrick Rudolph 
Tested-by: build bot (Jenkins) 
---
M src/drivers/aspeed/common/ast_main.c
M src/drivers/aspeed/common/ast_mode_corebootfb.c
M src/drivers/uart/oxpcie.c
M src/northbridge/intel/pineview/gma.c
M src/southbridge/intel/bd82x6x/smbus.c
M src/southbridge/intel/common/pciehp.c
M src/southbridge/intel/i82801gx/smbus.c
M src/southbridge/intel/i82801gx/usb_ehci.c
M src/southbridge/intel/i82801ix/smbus.c
M src/southbridge/intel/i82801jx/smbus.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/ibexpeak/thermal.c
12 files changed, 35 insertions(+), 24 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Patrick Rudolph: Looks good to me, approved

diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c
index 5143e6d..8ed1eaa 100644
--- a/src/drivers/aspeed/common/ast_main.c
+++ b/src/drivers/aspeed/common/ast_main.c
@@ -4,6 +4,7 @@
  */

#include <delay.h>
+#include <device/pci_def.h>

#include "ast_drv.h"
 #include "ast_dram_tables.h"
@@ -329,7 +330,7 @@
    ast->dev = dev;

/* PCI BAR 1 */
-	res = find_resource(dev->pdev, 0x14);
+	res = find_resource(dev->pdev, PCI_BASE_ADDRESS_1);
    if (!res) {
    	dev_err(dev->pdev, "BAR1 resource not found.\n");
    	ret = -EIO;
@@ -343,7 +344,7 @@

/* PCI BAR 2 */
    ast->io_space_uses_mmap = false;
-	res = find_resource(dev->pdev, 0x18);
+	res = find_resource(dev->pdev, PCI_BASE_ADDRESS_2);
    if (!res) {
    	dev_err(dev->pdev, "BAR2 resource not found.\n");
    	ret = -EIO;
diff --git a/src/drivers/aspeed/common/ast_mode_corebootfb.c b/src/drivers/aspeed/common/ast_mode_corebootfb.c
index 2a033a0..8418b01 100644
--- a/src/drivers/aspeed/common/ast_mode_corebootfb.c
+++ b/src/drivers/aspeed/common/ast_mode_corebootfb.c
@@ -3,6 +3,7 @@
  * Copied from Linux drivers/gpu/drm/ast/ast_mode.c
  */
 #include <edid.h>
+#include <device/pci_def.h>

#include "ast_drv.h"

@@ -18,7 +19,7 @@
    struct drm_framebuffer *fb = crtc->primary->fb;

/* PCI BAR 0 */
-	struct resource *res = find_resource(crtc->dev->pdev, 0x10);
+	struct resource *res = find_resource(crtc->dev->pdev, PCI_BASE_ADDRESS_0);
    if (!res) {
    	printk(BIOS_ERR, "BAR0 resource not found.\n");
    	return -EIO;
diff --git a/src/drivers/uart/oxpcie.c b/src/drivers/uart/oxpcie.c
index d8a8b91..17e0d26 100644
--- a/src/drivers/uart/oxpcie.c
+++ b/src/drivers/uart/oxpcie.c
@@ -12,7 +12,7 @@
 {
    printk(BIOS_DEBUG, "Initializing Oxford OXPCIe952\n");

-	struct resource *res = find_resource(dev, 0x10);
+	struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0);
    if (!res) {
    	printk(BIOS_WARNING, "OXPCIe952: No UART resource found.\n");
    	return;
diff --git a/src/northbridge/intel/pineview/gma.c b/src/northbridge/intel/pineview/gma.c
index e46bd7c..e0ed0f0 100644
--- a/src/northbridge/intel/pineview/gma.c
+++ b/src/northbridge/intel/pineview/gma.c
@@ -6,6 +6,7 @@
 #include <delay.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <drivers/intel/gma/i915_reg.h>
@@ -234,9 +235,9 @@
    	int vga_disable = (pci_read_config16(dev, GGC) & 2) >> 1;

/* Find base addresses */
-		mmio_res = find_resource(dev, 0x10);
-		gtt_res  = find_resource(dev, 0x1c);
-		pio_res  = find_resource(dev, 0x14);
+		mmio_res = find_resource(dev, PCI_BASE_ADDRESS_0);
+		gtt_res  = find_resource(dev, PCI_BASE_ADDRESS_3);
+		pio_res  = find_resource(dev, PCI_BASE_ADDRESS_1);
    	physbase = pci_read_config32(dev, 0x5c) & ~0xf;

if (gtt_res && gtt_res->base && physbase && pio_res && pio_res->base) {
diff --git a/src/southbridge/intel/bd82x6x/smbus.c b/src/southbridge/intel/bd82x6x/smbus.c
index 7a00cf4..b251596 100644
--- a/src/southbridge/intel/bd82x6x/smbus.c
+++ b/src/southbridge/intel/bd82x6x/smbus.c
@@ -4,6 +4,7 @@
 #include <device/path.h>
 #include <device/smbus.h>
 #include <device/pci.h>
+#include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <device/smbus_host.h>
@@ -34,7 +35,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);

return do_smbus_read_byte(res->base, device, address);
 }
@@ -47,7 +48,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);

return do_smbus_write_byte(res->base, device, address, val);
 }
diff --git a/src/southbridge/intel/common/pciehp.c b/src/southbridge/intel/common/pciehp.c
index 5556aba..247bf5d 100644
--- a/src/southbridge/intel/common/pciehp.c
+++ b/src/southbridge/intel/common/pciehp.c
@@ -5,6 +5,7 @@
 #include <acpi/acpigen.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_def.h>

#include "pciehp.h"

@@ -121,7 +122,7 @@
 {
    struct resource *resource;

-	resource = new_resource(dev, 0x10);
+	resource = new_resource(dev, PCI_BASE_ADDRESS_0);
    resource->size = 1 << 23;
    resource->align = 22;
    resource->gran = 22;
diff --git a/src/southbridge/intel/i82801gx/smbus.c b/src/southbridge/intel/i82801gx/smbus.c
index 6b63959..9624b98 100644
--- a/src/southbridge/intel/i82801gx/smbus.c
+++ b/src/southbridge/intel/i82801gx/smbus.c
@@ -4,6 +4,7 @@
 #include <device/path.h>
 #include <device/smbus.h>
 #include <device/pci.h>
+#include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/smbus_host.h>
 #include "i82801gx.h"
@@ -16,7 +17,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);

return do_smbus_read_byte(res->base, device, address);
 }
@@ -29,7 +30,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
    return do_smbus_write_byte(res->base, device, address, data);
 }

@@ -41,7 +42,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
    return do_smbus_block_write(res->base, device, cmd, bytes, buf);
 }

@@ -53,7 +54,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
    return do_smbus_block_read(res->base, device, cmd, bytes, buf);
 }

diff --git a/src/southbridge/intel/i82801gx/usb_ehci.c b/src/southbridge/intel/i82801gx/usb_ehci.c
index 0a66136..b01af96 100644
--- a/src/southbridge/intel/i82801gx/usb_ehci.c
+++ b/src/southbridge/intel/i82801gx/usb_ehci.c
@@ -7,6 +7,7 @@
 #include "i82801gx.h"
 #include <device/pci_ehci.h>
 #include <device/mmio.h>
+#include <device/pci_def.h>
 #include <device/pci_ops.h>

static void usb_ehci_init(struct device *dev)
@@ -23,7 +24,7 @@
    pci_update_config32(dev, 0xfc, ~(3 << 2), (2 << 2) | (1 << 29) | (1 << 17));

/* Clear any pending port changes */
-	res = find_resource(dev, 0x10);
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
    base = res2mmio(res, 0, 0);
    reg32 = read32(base + 0x24) | (1 << 2);
    write32(base + 0x24, reg32);
diff --git a/src/southbridge/intel/i82801ix/smbus.c b/src/southbridge/intel/i82801ix/smbus.c
index 815705d..72c3110 100644
--- a/src/southbridge/intel/i82801ix/smbus.c
+++ b/src/southbridge/intel/i82801ix/smbus.c
@@ -4,6 +4,7 @@
 #include <device/path.h>
 #include <device/smbus.h>
 #include <device/pci.h>
+#include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <device/smbus_host.h>
@@ -23,7 +24,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);

return do_smbus_read_byte(res->base, device, address);
 }
@@ -36,7 +37,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);

return do_smbus_write_byte(res->base, device, address, val);
 }
diff --git a/src/southbridge/intel/i82801jx/smbus.c b/src/southbridge/intel/i82801jx/smbus.c
index 6595635..c92a286 100644
--- a/src/southbridge/intel/i82801jx/smbus.c
+++ b/src/southbridge/intel/i82801jx/smbus.c
@@ -4,6 +4,7 @@
 #include <device/path.h>
 #include <device/smbus.h>
 #include <device/pci.h>
+#include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <device/smbus_host.h>
@@ -23,7 +24,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);

return do_smbus_read_byte(res->base, device, address);
 }
@@ -36,7 +37,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);

return do_smbus_write_byte(res->base, device, address, val);
 }
@@ -50,7 +51,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
    return do_smbus_block_write(res->base, device, cmd, bytes, buf);
 }

@@ -62,7 +63,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);
    return do_smbus_block_read(res->base, device, cmd, bytes, buf);
 }

diff --git a/src/southbridge/intel/ibexpeak/smbus.c b/src/southbridge/intel/ibexpeak/smbus.c
index 01001c3..7c9ac82 100644
--- a/src/southbridge/intel/ibexpeak/smbus.c
+++ b/src/southbridge/intel/ibexpeak/smbus.c
@@ -4,6 +4,7 @@
 #include <device/path.h>
 #include <device/smbus.h>
 #include <device/pci.h>
+#include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <device/smbus_host.h>
@@ -33,7 +34,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);

return do_smbus_read_byte(res->base, device, address);
 }
@@ -46,7 +47,7 @@

device = dev->path.i2c.device;
    pbus = get_pbus_smbus(dev);
-	res = find_resource(pbus->dev, 0x20);
+	res = find_resource(pbus->dev, PCI_BASE_ADDRESS_4);

return do_smbus_write_byte(res->base, device, address, val);
 }
diff --git a/src/southbridge/intel/ibexpeak/thermal.c b/src/southbridge/intel/ibexpeak/thermal.c
index 0b496da..142d3c7 100644
--- a/src/southbridge/intel/ibexpeak/thermal.c
+++ b/src/southbridge/intel/ibexpeak/thermal.c
@@ -3,6 +3,7 @@
 #include <console/console.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <device/pci_def.h>
 #include <device/pci_ids.h>
 #include "pch.h"
 #include <device/mmio.h>
@@ -13,7 +14,7 @@
    u8 *base;
    printk(BIOS_DEBUG, "Thermal init start.\n");

-	res = find_resource(dev, 0x10);
+	res = find_resource(dev, PCI_BASE_ADDRESS_0);
    if (!res)
    	return;