coreboot-gerrit August 2020

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Change in coreboot[master]: soc/amd/stoneyridge: use new ACPI helper functions from common
by Aaron Durbin (Code Review) 17 Aug '20

17 Aug '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44483 ) Change subject: soc/amd/stoneyridge: use new ACPI helper functions from common ...................................................................... soc/amd/stoneyridge: use new ACPI helper functions from common Transition the current call sequence to using the newly added common ACPI helper functions. Semantically, the expectations are that this sequence is the equivalent of previous acpi_clear_pm1_status(). BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Id3ae19013c68d2c97b084046f600596ecc462374 --- M src/soc/amd/stoneyridge/southbridge.c 1 file changed, 14 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/44483/1 diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 628aea9..c801036 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -501,59 +501,36 @@ PM_ACPI_TIMER_EN_EN); } -static int get_index_bit(uint32_t value, uint16_t limit) -{ - uint16_t i; - uint32_t t; - - if (limit >= TOTAL_BITS(uint32_t)) - return -1; - - /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ - t = (1 << limit) - 1; - if ((value & t) == 0) - return -1; - t = 1; - for (i = 0; i < limit; i++) { - if (value & t) - break; - t <<= 1; - } - return i; -} - static void set_nvs_sws(void *unused) { - struct soc_power_reg *sws; + struct acpi_pm_gpe_state *state; struct global_nvs *gnvs; - int index; - sws = cbmem_find(CBMEM_ID_POWER_STATE); - if (sws == NULL) + state = cbmem_find(CBMEM_ID_POWER_STATE); + if (state == NULL) return; gnvs = acpi_get_gnvs(); if (gnvs == NULL) return; - index = get_index_bit(sws->pm1_sts & sws->pm1_en, PM1_LIMIT); - if (index < 0) - gnvs->pm1i = ~0ULL; - else - gnvs->pm1i = index; - - index = get_index_bit(sws->gpe0_sts & sws->gpe0_en, GPE0_LIMIT); - if (index < 0) - gnvs->gpei = ~0ULL; - else - gnvs->gpei = index; + acpi_fill_gnvs(gnvs, state); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); void southbridge_init(void *chip_info) { + struct acpi_pm_gpe_state *state; + sb_init_acpi_ports(); - acpi_clear_pm1_status(); + + state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); + if (state) { + acpi_fill_pm_gpe_state(state); + acpi_pm_gpe_add_events_print_events(); + } + + acpi_clear_pm_gpe_status(); } static void set_sb_final_nvs(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/44483 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3ae19013c68d2c97b084046f600596ecc462374 Gerrit-Change-Number: 44483 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: add acpi_fill_gnvs()
by Aaron Durbin (Code Review) 17 Aug '20

17 Aug '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44482 ) Change subject: soc/amd/common: add acpi_fill_gnvs() ...................................................................... soc/amd/common: add acpi_fill_gnvs() In order to reduce code duplication provide an acpi_fill_gnvs() helper function. Intent is to move stoneyridge and picasso over to using this common implementation instead of duplicating it. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I21c6e2c24eaf42f31ae57c05df7f633d7dc266d9 --- M src/soc/amd/common/block/acpi/acpi.c M src/soc/amd/common/block/include/amdblocks/acpi.h 2 files changed, 41 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/44482/1 diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index be331e3..0e6dabf 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -113,6 +113,44 @@ acpi_write32(MMIO_ACPI_GPE0_STS, acpi_read32(MMIO_ACPI_GPE0_STS)); } +static int get_index_bit(uint32_t value, uint16_t limit) +{ + uint16_t i; + uint32_t t; + + if (limit >= TOTAL_BITS(uint32_t)) + return -1; + + /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ + t = (1 << limit) - 1; + if ((value & t) == 0) + return -1; + t = 1; + for (i = 0; i < limit; i++) { + if (value & t) + break; + t <<= 1; + } + return i; +} + +void acpi_fill_gnvs(struct global_nvs *gnvs, const struct acpi_pm_gpe_state *state) +{ + int index; + + index = get_index_bit(state->pm1_sts & state->pm1_en, PM1_LIMIT); + if (index < 0) + gnvs->pm1i = ~0ULL; + else + gnvs->pm1i = index; + + index = get_index_bit(state->gpe0_sts & state->gpe0_en, GPE0_LIMIT); + if (index < 0) + gnvs->gpei = ~0ULL; + else + gnvs->gpei = index; +} + static void save_sws(uint16_t pm1_status) { struct soc_power_reg *sws; diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 8f16054..8d0e5f6 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -4,6 +4,7 @@ #define __AMDBLOCKS_ACPI_H__ #include <types.h> +#include <soc/nvs.h> /* ACPI MMIO registers 0xfed80800 */ #define MMIO_ACPI_PM1_STS 0x00 @@ -32,6 +33,8 @@ void acpi_pm_gpe_add_events_print_events(const struct acpi_pm_gpe_state *state); /* Clear PM and GPE status registers. */ void acpi_clear_pm_gpe_status(void); +/* Fill GNVS object from PM GPE object. */ +void acpi_fill_gnvs(struct global_nvs *gnvs, const struct acpi_pm_gpe_state *state); void acpi_clear_pm1_status(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/44482 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21c6e2c24eaf42f31ae57c05df7f633d7dc266d9 Gerrit-Change-Number: 44482 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: add single function ACPI PM1 GPE helpers
by Aaron Durbin (Code Review) 17 Aug '20

17 Aug '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44481 ) Change subject: soc/amd/common: add single function ACPI PM1 GPE helpers ...................................................................... soc/amd/common: add single function ACPI PM1 GPE helpers The existing code in common/block/acpi is mixing multiple operations: saving things to cbmem in common code but then soc code uses that information, reliant upon soc-specific struct soc_power_reg object, and only saving/snapshotting ACPI registers very deep in ramsatage. To unwind the above provide some functions that are more targeted: - Add struct acpi_pm_gpe_state object - Add acpi_fill_pm_gpe_state() - Add acpi_pm_gpe_add_events_print_events() - Add acpi_clear_pm_gpe_status() BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ia7afed2861343802b3c78728784f7cfaf6f53f62 --- M src/soc/amd/common/block/acpi/acpi.c M src/soc/amd/common/block/include/amdblocks/acpi.h 2 files changed, 39 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/44481/1 diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 2be9b9e..be331e3 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -91,6 +91,28 @@ elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); } +void acpi_fill_pm_gpe_state(struct acpi_pm_gpe_state *state) +{ + state->pm1_sts = acpi_read16(MMIO_ACPI_PM1_STS); + state->pm1_en = acpi_read16(MMIO_ACPI_PM1_EN); + state->gpe0_sts = acpi_read32(MMIO_ACPI_GPE0_STS); + state->gpe0_en = acpi_read32(MMIO_ACPI_GPE0_EN); + state->previous_sx_state = acpi_get_sleep_type(); + state->aligning_field = 0; +} + +void acpi_pm_gpe_add_events_print_events(const struct acpi_pm_gpe_state *state) +{ + log_pm1_status(state->pm1_sts); + print_pm1_status(state->pm1_sts); +} + +void acpi_clear_pm_gpe_status(void) +{ + acpi_write16(MMIO_ACPI_PM1_STS, acpi_read16(MMIO_ACPI_PM1_STS)); + acpi_write32(MMIO_ACPI_GPE0_STS, acpi_read32(MMIO_ACPI_GPE0_STS)); +} + static void save_sws(uint16_t pm1_status) { struct soc_power_reg *sws; diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 4d22735..8f16054 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -16,6 +16,23 @@ #define MMIO_ACPI_GPE0_STS 0x14 #define MMIO_ACPI_GPE0_EN 0x18 +/* Structure to maintain standard ACPI register state for reporting purposes. */ +struct acpi_pm_gpe_state { + uint16_t pm1_sts; + uint16_t pm1_en; + uint32_t gpe0_sts; + uint32_t gpe0_en; + uint16_t previous_sx_state; + uint16_t aligning_field; +}; + +/* Fill object with the ACPI PM and GPE state. */ +void acpi_fill_pm_gpe_state(struct acpi_pm_gpe_state *state); +/* Save events to eventlog log and also print information on console. */ +void acpi_pm_gpe_add_events_print_events(const struct acpi_pm_gpe_state *state); +/* Clear PM and GPE status registers. */ +void acpi_clear_pm_gpe_status(void); + void acpi_clear_pm1_status(void); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/44481 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia7afed2861343802b3c78728784f7cfaf6f53f62 Gerrit-Change-Number: 44481 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: Documentation: Discuss how we use language
by Patrick Georgi (Code Review) 17 Aug '20

17 Aug '20

Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43420 ) Change subject: Documentation: Discuss how we use language ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/43420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44fa30af538c78760821401c8d3c52029d95b72b Gerrit-Change-Number: 43420 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 17 Aug 2020 16:27:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Allow fine grained control of S0iX states
by Jes Klinke (Code Review) 17 Aug '20

17 Aug '20

Hello Jes Klinke, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44355 to review the following change. Change subject: soc/intel/tigerlake: Allow fine grained control of S0iX states ...................................................................... soc/intel/tigerlake: Allow fine grained control of S0iX states Expose FSP parameter to enable/disable each individual substate. See https://review.coreboot.org/c/coreboot/+/43741 for context. Change-Id: I8a0cf820e20961486813067c6945fe07bc4899f7 Signed-off-by: jbk(a)chromium.org --- M src/soc/intel/tigerlake/chip.h M src/soc/intel/tigerlake/fsp_params.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/44355/1 diff --git a/src/soc/intel/tigerlake/chip.h b/src/soc/intel/tigerlake/chip.h index dc910ff..6c5daa5 100644 --- a/src/soc/intel/tigerlake/chip.h +++ b/src/soc/intel/tigerlake/chip.h @@ -78,6 +78,9 @@ /* Enable S0iX support */ int s0ix_enable; + /* S0iX: Selectively enable individual sub-states */ + uint8_t LpmStateEnableMask; + /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ uint8_t TcssD3HotDisable; /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index a61a025..53ca11e 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -204,6 +204,13 @@ sizeof(params->SataPortsDevSlp)); } + /* S0iX: Selectively enable individual sub-states. + * + * LPM0-s0i2.0, LPM1-s0i2.1, LPM2-s0i2.2, LPM3-s0i3.0, + * LPM4-s0i3.1, LPM5-s0i3.2, LPM6-s0i3.3, LPM7-s0i3.4 + */ + params->LpmStateEnableMask = config->LpmStateEnableMask; + /* * Power Optimizer for DMI and SATA. * DmiPwrOptimizeDisable and SataPwrOptimizeDisable is default to 0. -- To view, visit https://review.coreboot.org/c/coreboot/+/44355 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8a0cf820e20961486813067c6945fe07bc4899f7 Gerrit-Change-Number: 44355 Gerrit-PatchSet: 1 Gerrit-Owner: Jes Klinke <jbk(a)chromium.org> Gerrit-Reviewer: Jes Klinke <jbk(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/arm: Enable booting Linux payloads
by Sam Lewis (Code Review) 17 Aug '20

17 Aug '20

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44376 ) Change subject: arch/arm: Enable booting Linux payloads ...................................................................... arch/arm: Enable booting Linux payloads Enables booting in a Linux kernel payload with the calling convention the kernel requires. As there is no method in coreboot to check the type of payload being booted (Linux or otherwise) this assumes any payload is a Linux payload. Change-Id: If50c834c8f434bc02dee8f84370d1dbf8f9b69e2 Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- M src/arch/arm/boot.c 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/44376/1 diff --git a/src/arch/arm/boot.c b/src/arch/arm/boot.c index 8c876de..fc87f2c 100644 --- a/src/arch/arm/boot.c +++ b/src/arch/arm/boot.c @@ -3,12 +3,28 @@ #include <arch/cache.h> #include <program_loading.h> +static void run_linux_payload(struct prog *prog) +{ + void (*kernel_entry)(void *sbz, void *sbo, void *dtb); + void *fdt; + + kernel_entry = prog_entry(prog); + fdt = prog_entry_arg(prog); + kernel_entry(0, (void *)~0, fdt); +} + void arch_prog_run(struct prog *prog) { void (*doit)(void *); cache_sync_instructions(); + if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { + dcache_mmu_disable(); + run_linux_payload(prog); + return; + } + doit = prog_entry(prog); doit(prog_entry_arg(prog)); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44376 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If50c834c8f434bc02dee8f84370d1dbf8f9b69e2 Gerrit-Change-Number: 44376 Gerrit-PatchSet: 1 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/jasperlake: Disable multiphase SI init
by Ronak Kanabar (Code Review) 17 Aug '20

17 Aug '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Subrata Banik, Krishna P Bhat D, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43816 to look at the new patch set (#8). Change subject: soc/intel/jasperlake: Disable multiphase SI init ...................................................................... soc/intel/jasperlake: Disable multiphase SI init Jasper Lake does not have any use case for multiphase SI init so Disable it. BUG=b:162184827 BRANCH=None TEST=Build and boot JSLRVP Change-Id: I2d591b46c403e68ff0b41ac8f87c742ae774111e Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43816/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/43816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d591b46c403e68ff0b41ac8f87c742ae774111e Gerrit-Change-Number: 43816 Gerrit-PatchSet: 8 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Disable multiphase SI init
by build bot (Jenkins) (Code Review) 17 Aug '20

17 Aug '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43816 ) Change subject: soc/intel/jasperlake: Disable multiphase SI init ...................................................................... Patch Set 7: (2 comments) https://review.coreboot.org/c/coreboot/+/43816/7/src/soc/intel/jasperlake/f… File src/soc/intel/jasperlake/fsp_params.c: https://review.coreboot.org/c/coreboot/+/43816/7/src/soc/intel/jasperlake/f… PS7, Line 355: return 0; code indent should use tabs where possible https://review.coreboot.org/c/coreboot/+/43816/7/src/soc/intel/jasperlake/f… PS7, Line 355: return 0; please, no spaces at the start of a line -- To view, visit https://review.coreboot.org/c/coreboot/+/43816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d591b46c403e68ff0b41ac8f87c742ae774111e Gerrit-Change-Number: 43816 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 17 Aug 2020 11:21:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback.
by Paul Menzel (Code Review) 17 Aug '20

17 Aug '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback. ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/44430/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44430/3//COMMIT_MSG@7 PS3, Line 7: cse_lite: Move global reset after MRC writeback. Please remove the dot/period at the end of the commit message summary. -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 17 Aug 2020 10:24:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback.
by Sridhar Siricilla (Code Review) 17 Aug '20

17 Aug '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback. ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/c/coreboot/+/44430/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44430/3//COMMIT_MSG@10 PS3, Line 10: on the initial power-on boot after SPI flash update? -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 3 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 17 Aug 2020 10:19:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2020