coreboot-gerrit August 2020

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Change in coreboot[master]: soc/intel/cannonlake: Add support for UART2 on PCH-H
by Patrick Rudolph (Code Review) 18 Aug '20

18 Aug '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40405 ) Change subject: soc/intel/cannonlake: Add support for UART2 on PCH-H ...................................................................... soc/intel/cannonlake: Add support for UART2 on PCH-H On PCH-H the UART2 can't be used as PCI device as the parent multi function device isn't available. As workaround add an ACPI driver for PCH-H UART2 that generates ACPI code for the Intel LPSS ACPI driver. Tested on Linux with Sunrise Point ACPI ID for UART2. Change-Id: I838d16322be38f5421c1f63b457a0af552e0ed96 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/cannonlake/acpi/serialio.asl A src/soc/intel/cannonlake/pch_h.c M src/soc/intel/common/block/include/intelblocks/uart.h M src/soc/intel/common/block/uart/uart.c 5 files changed, 98 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/40405/1 diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index c744e99..e263264 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -54,6 +54,11 @@ ramstage-y += vr_config.c ramstage-y += sd.c ramstage-y += xhci.c +ifeq ($(CONFIG_HAVE_ACPI_TABLES),y) +ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_LPSS),y) +ramstage-$(CONFIG_SOC_INTEL_CANNONLAKE_PCH_H) += pch_h.c +endif +endif smm-y += elog.c smm-y += p2sb.c diff --git a/src/soc/intel/cannonlake/acpi/serialio.asl b/src/soc/intel/cannonlake/acpi/serialio.asl index 2785e3d..5e28b98 100644 --- a/src/soc/intel/cannonlake/acpi/serialio.asl +++ b/src/soc/intel/cannonlake/acpi/serialio.asl @@ -69,8 +69,11 @@ Name (_DDN, "Serial IO UART Controller 1") } + +#if !CONFIG(SOC_INTEL_CANNONLAKE_PCH_H) Device (UAR2) { Name (_ADR, 0x00190002) Name (_DDN, "Serial IO UART Controller 2") } +#endif diff --git a/src/soc/intel/cannonlake/pch_h.c b/src/soc/intel/cannonlake/pch_h.c new file mode 100644 index 0000000..84a75e8 --- /dev/null +++ b/src/soc/intel/cannonlake/pch_h.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* This file is part of the coreboot project. */ +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <soc/irq.h> +#include <intelblocks/uart.h> +#include <console/console.h> + +/* + * On PCH-H the I2C4 0:19.0 device isn't usable and thus 0:19.2 isn't detected + * using standard PCI probing. + * Generate an ACPI entry if the device is enabled in devicetree for the ACPI + * LPSS driver. + */ +static void pch_h_uart2_fill_ssdt(struct device *dev) +{ + struct acpi_irq irq = ACPI_IRQ_LEVEL_LOW(LPSS_UART2_IRQ); + const char *scope = acpi_device_scope(dev); + printk(BIOS_ERR, "ACPIGEN: %s\n", acpi_device_name(dev)); + struct resource *res; + if (!scope) + return; + + res = find_resource(dev, PCI_BASE_ADDRESS_0); + if (!res) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", acpi_device_hid(dev)); + /* + * INT344A is the Sunrise Point HID, as the Linux kernel doesn't support + * CannonPoint yet... + */ + acpigen_write_name_string("_CID", "INT344A"); + acpi_device_write_uid(dev); + acpigen_write_name_string("_DDN", "LPSS ACPI UART"); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + + acpi_device_write_interrupt(&irq); + acpigen_write_mem32fixed(1, res->base, res->size); + + acpigen_write_resourcetemplate_footer(); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *pch_h_uart2_acpi_hid(const struct device *dev) +{ + return "INT34BA"; +} + +static struct device_operations device_ops_cnp_h = { + .read_resources = uart_common_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = uart_common_enable_resources, + .ops_pci = &pci_dev_ops_pci, + .acpi_hid = pch_h_uart2_acpi_hid, + .acpi_fill_ssdt_generator = pch_h_uart2_fill_ssdt, +}; + +static const struct pci_driver pch_h_uart __pci_driver = { + .ops = &device_ops_cnp_h, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_INTEL_CNP_H_UART2, +}; diff --git a/src/soc/intel/common/block/include/intelblocks/uart.h b/src/soc/intel/common/block/include/intelblocks/uart.h index cc27f0e..a51a739 100644 --- a/src/soc/intel/common/block/include/intelblocks/uart.h +++ b/src/soc/intel/common/block/include/intelblocks/uart.h @@ -31,6 +31,16 @@ void uart_common_init(const struct device *dev, uintptr_t baseaddr); /* + * Common routine to enable UART resources in PCI config space. + */ +void uart_common_enable_resources(struct device *dev); + +/* + * Common routine to read UART resources in PCI config space. + */ +void uart_common_read_resources(struct device *dev); + +/* * Check if UART debug controller is initialized * Returns: * true = If debug controller PCI config space is initialized and device is diff --git a/src/soc/intel/common/block/uart/uart.c b/src/soc/intel/common/block/uart/uart.c index 7d75bdd..3464571 100644 --- a/src/soc/intel/common/block/uart/uart.c +++ b/src/soc/intel/common/block/uart/uart.c @@ -143,7 +143,7 @@ #if ENV_RAMSTAGE -static void uart_read_resources(struct device *dev) +void uart_common_read_resources(struct device *dev) { pci_dev_read_resources(dev); @@ -213,7 +213,7 @@ return pch_uart_init_debug_controller_on_resume(); } -static void uart_common_enable_resources(struct device *dev) +void uart_common_enable_resources(struct device *dev) { pci_dev_enable_resources(dev); @@ -227,7 +227,7 @@ } static struct device_operations device_ops = { - .read_resources = uart_read_resources, + .read_resources = uart_common_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = uart_common_enable_resources, .ops_pci = &pci_dev_ops_pci, @@ -256,7 +256,6 @@ PCI_DEVICE_ID_INTEL_GLK_UART3, PCI_DEVICE_ID_INTEL_CNP_H_UART0, PCI_DEVICE_ID_INTEL_CNP_H_UART1, - PCI_DEVICE_ID_INTEL_CNP_H_UART2, PCI_DEVICE_ID_INTEL_ICP_UART0, PCI_DEVICE_ID_INTEL_ICP_UART1, PCI_DEVICE_ID_INTEL_ICP_UART2, -- To view, visit https://review.coreboot.org/c/coreboot/+/40405 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I838d16322be38f5421c1f63b457a0af552e0ed96 Gerrit-Change-Number: 40405 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/volteer/var/voxel: disable AUX orientation swap
by Sheng-Liang Pan (Code Review) 18 Aug '20

18 Aug '20

Sheng-Liang Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44324 ) Change subject: mb/google/volteer/var/voxel: disable AUX orientation swap ...................................................................... mb/google/volteer/var/voxel: disable AUX orientation swap fix C0 DP issue when cable is flipped. BUG=b:162376062 BRANCH=master TEST=build and verify C0 can display out with cable flipped. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan(a)quanta.corp-partner.google.com> Change-Id: I5915ab127d4c3e34c91c4b8b1c5147ddfcf5deac --- M src/mainboard/google/volteer/variants/voxel/overridetree.cb 1 file changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/44324/1 diff --git a/src/mainboard/google/volteer/variants/voxel/overridetree.cb b/src/mainboard/google/volteer/variants/voxel/overridetree.cb index 43296d5..ab75bcd 100644 --- a/src/mainboard/google/volteer/variants/voxel/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voxel/overridetree.cb @@ -1,4 +1,8 @@ chip soc/intel/tigerlake + register "TcssAuxOri" = "0" + register "IomTypeCPortPadCfg[0]" = "0x09000000" + register "IomTypeCPortPadCfg[1]" = "0x09000000" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/44324 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5915ab127d4c3e34c91c4b8b1c5147ddfcf5deac Gerrit-Change-Number: 44324 Gerrit-PatchSet: 1 Gerrit-Owner: Sheng-Liang Pan <sheng-liang.pan(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: trogdor: SoC makefile blob support
by Julius Werner (Code Review) 17 Aug '20

17 Aug '20

Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35508 ) Change subject: trogdor: SoC makefile blob support ...................................................................... Patch Set 88: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/35508 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I85a20ef31ec91c6f22221d16fd4c3097c5cb97d1 Gerrit-Change-Number: 35508 Gerrit-PatchSet: 88 Gerrit-Owner: mturney mturney <mturney(a)codeaurora.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Ravi kumar <rbokka(a)codeaurora.org> Gerrit-Reviewer: ashk(a)codeaurora.org Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: mturney mturney <mturney(a)codeaurora.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Ravi Kumar Bokka <c_rbokka(a)qualcomm.corp-partner.google.com> Gerrit-CC: Saurabh Gorecha Gerrit-Comment-Date: Mon, 17 Aug 2020 23:35:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add ASan support to ramstage on x86 arch
by Harshit Sharma (Code Review) 17 Aug '20

17 Aug '20

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42496 ) Change subject: lib: Add ASan support to ramstage on x86 arch ...................................................................... Patch Set 27: (1 comment) https://review.coreboot.org/c/coreboot/+/42496/27/src/lib/asan.c File src/lib/asan.c: https://review.coreboot.org/c/coreboot/+/42496/27/src/lib/asan.c@12 PS27, Line 12: * it under the terms of the GNU General Public License version 2 as > Needs to be a spdx license header I copied this header verbatim from Linux's kasan code. Can I remove this comment block completely and just add a simple spdx header like the one in asan.h? -- To view, visit https://review.coreboot.org/c/coreboot/+/42496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Gerrit-Change-Number: 42496 Gerrit-PatchSet: 27 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Mon, 17 Aug 2020 19:49:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/amd/common: add GPE event logs
by Aaron Durbin (Code Review) 17 Aug '20

17 Aug '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44489 ) Change subject: soc/amd/common: add GPE event logs ...................................................................... soc/amd/common: add GPE event logs GPE events were not be recorded in the eventlog. Add those to the eventlog when the status register indicates those events. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ifb3167fd24f2171b2baf1a65eb81a318eb3e7a86 --- M src/soc/amd/common/block/acpi/acpi.c 1 file changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/44489/1 diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 17c0ed1..28fa678 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -83,6 +83,17 @@ elog_add_event_wake(ELOG_WAKE_SOURCE_PCIE, 0); } +static void log_and_gpe_events(const struct acpi_pm_gpe_state *state) +{ + int i; + uint32_t valid_gpe = state->gpe0_sts & state->gpe0_en; + + for (i = 0; i <= 31; i++) { + if (valid_gpe & (1U << i)) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + } +} + void acpi_fill_pm_gpe_state(struct acpi_pm_gpe_state *state) { state->pm1_sts = acpi_read16(MMIO_ACPI_PM1_STS); @@ -97,6 +108,7 @@ { log_pm1_status(state->pm1_sts); print_pm1_status(state->pm1_sts); + log_and_gpe_events(state); } void acpi_clear_pm_gpe_status(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/44489 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifb3167fd24f2171b2baf1a65eb81a318eb3e7a86 Gerrit-Change-Number: 44489 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: snapshot chipset state early in boot sequence
by Aaron Durbin (Code Review) 17 Aug '20

17 Aug '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44488 ) Change subject: soc/amd/picasso: snapshot chipset state early in boot sequence ...................................................................... soc/amd/picasso: snapshot chipset state early in boot sequence Previously the chipset state was snapshotted very late in the boot (ramstage). Instead start gathering the state early in romstage prior to calling any FSP routines so there's a clean snapshot. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Id41686e6cdf5bebc9633b514b4121b0447f9be2d --- M src/soc/amd/picasso/romstage.c M src/soc/amd/picasso/southbridge.c 2 files changed, 26 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/44488/1 diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index e7b4b3d..6178220 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -2,6 +2,8 @@ #include <arch/cpu.h> #include <acpi/acpi.h> +#include <amdblocks/acpi.h> +#include <cbmem.h> #include <cpu/x86/cache.h> #include <cpu/amd/mtrr.h> #include <console/uart.h> @@ -15,6 +17,25 @@ #include "chip.h" #include <fsp/api.h> +static struct acpi_pm_gpe_state chipset_state; + +static void fill_chipset_state(void) +{ + acpi_fill_pm_gpe_state(&chipset_state); +} + +static void add_chipset_state_cbmem(int unused) +{ + struct acpi_pm_gpe_state *state; + + state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); + + if (state) + acpi_fill_pm_gpe_state(state); +} + +ROMSTAGE_CBMEM_INIT_HOOK(add_chipset_state_cbmem); + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { FSP_M_CONFIG *mcfg = &mupd->FspmConfig; @@ -81,6 +102,9 @@ u32 val = cpuid_eax(1); printk(BIOS_DEBUG, "Family_Model: %08x\n", val); + /* Snapshot chipset state prior to any FSP call. */ + fill_chipset_state(); + post_code(0x43); fsp_memory_init(s3_resume); soc_update_mrc_cache(); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index ff8e436..df2d0d0 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -314,11 +314,9 @@ i2c_soc_init(); sb_init_acpi_ports(); - state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); - if (state) { - acpi_fill_pm_gpe_state(state); + state = cbmem_find(CBMEM_ID_POWER_STATE); + if (state) acpi_pm_gpe_add_events_print_events(state); - } acpi_clear_pm_gpe_status(); al2ahb_clock_gate(); -- To view, visit https://review.coreboot.org/c/coreboot/+/44488 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id41686e6cdf5bebc9633b514b4121b0447f9be2d Gerrit-Change-Number: 44488 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge: remove unused soc_power_reg object
by Aaron Durbin (Code Review) 17 Aug '20

17 Aug '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44487 ) Change subject: soc/amd/stoneyridge: remove unused soc_power_reg object ...................................................................... soc/amd/stoneyridge: remove unused soc_power_reg object Now that no one is consuming this object, remove its definition. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ib5aeec1733b6c9fa49569e30c4c369f70af0939c --- M src/soc/amd/stoneyridge/include/soc/southbridge.h 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/44487/1 diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index 80c258f..85df0b3 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -318,14 +318,6 @@ unsigned int :4; } __packed aoac_devs_t; -struct soc_power_reg { - uint16_t pm1_sts; - uint16_t pm1_en; - uint32_t gpe0_sts; - uint32_t gpe0_en; - uint16_t wake_from; -}; - #define XHCI_FW_SIG_OFFSET 0xc #define XHCI_FW_ADDR_OFFSET 0x6 #define XHCI_FW_SIZE_OFFSET 0x8 -- To view, visit https://review.coreboot.org/c/coreboot/+/44487 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib5aeec1733b6c9fa49569e30c4c369f70af0939c Gerrit-Change-Number: 44487 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: remove unused soc_power_reg object
by Aaron Durbin (Code Review) 17 Aug '20

17 Aug '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44486 ) Change subject: soc/amd/picasso: remove unused soc_power_reg object ...................................................................... soc/amd/picasso: remove unused soc_power_reg object Now that no one is consuming this object, remove its definition. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I60e4a9bfdf2752923f46a35aaab7034f9fa9b309 --- M src/soc/amd/picasso/include/soc/southbridge.h 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/44486/1 diff --git a/src/soc/amd/picasso/include/soc/southbridge.h b/src/soc/amd/picasso/include/soc/southbridge.h index e9f7e2e..e4ae8dc 100644 --- a/src/soc/amd/picasso/include/soc/southbridge.h +++ b/src/soc/amd/picasso/include/soc/southbridge.h @@ -268,14 +268,6 @@ unsigned int :4; } __packed aoac_devs_t; -struct soc_power_reg { - uint16_t pm1_sts; - uint16_t pm1_en; - uint32_t gpe0_sts; - uint32_t gpe0_en; - uint16_t wake_from; -}; - void enable_aoac_devices(void); bool is_aoac_device_enabled(int dev); void power_on_aoac_device(int dev); -- To view, visit https://review.coreboot.org/c/coreboot/+/44486 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60e4a9bfdf2752923f46a35aaab7034f9fa9b309 Gerrit-Change-Number: 44486 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common: removed unused functions
by Aaron Durbin (Code Review) 17 Aug '20

17 Aug '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44485 ) Change subject: soc/amd/common: removed unused functions ...................................................................... soc/amd/common: removed unused functions Now that all users of the functions manipulating global state and using soc-specific objects are removed remove those functions. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I18c4c8b0c7852dde8cf0b6b3f11e43e15c3ce155 --- M src/soc/amd/common/block/acpi/acpi.c M src/soc/amd/common/block/include/amdblocks/acpi.h 2 files changed, 0 insertions(+), 39 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/44485/1 diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 0e6dabf..17c0ed1 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -4,7 +4,6 @@ #include <amdblocks/acpi.h> #include <acpi/acpi.h> #include <bootmode.h> -#include <cbmem.h> #include <console/console.h> #include <elog.h> #include <halt.h> @@ -25,13 +24,6 @@ halt(); } -static uint16_t reset_pm1_status(void) -{ - uint16_t pm1_sts = acpi_read16(MMIO_ACPI_PM1_STS); - acpi_write16(MMIO_ACPI_PM1_STS, pm1_sts); - return pm1_sts; -} - static void print_num_status_bits(int num_bits, uint32_t status, const char *const bit_names[]) { @@ -151,35 +143,6 @@ gnvs->gpei = index; } -static void save_sws(uint16_t pm1_status) -{ - struct soc_power_reg *sws; - uint32_t reg32; - uint16_t reg16; - - sws = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(struct soc_power_reg)); - if (sws == NULL) - return; - sws->pm1_sts = pm1_status; - sws->pm1_en = acpi_read16(MMIO_ACPI_PM1_EN); - reg32 = acpi_read32(MMIO_ACPI_GPE0_STS); - acpi_write32(MMIO_ACPI_GPE0_STS, reg32); - sws->gpe0_sts = reg32; - sws->gpe0_en = acpi_read32(MMIO_ACPI_GPE0_EN); - reg16 = acpi_read16(MMIO_ACPI_PM1_CNT_BLK); - reg16 &= SLP_TYP; - sws->wake_from = reg16 >> SLP_TYP_SHIFT; -} - -void acpi_clear_pm1_status(void) -{ - uint16_t pm1_sts = reset_pm1_status(); - - save_sws(pm1_sts); - log_pm1_status(pm1_sts); - print_pm1_status(pm1_sts); -} - int acpi_get_sleep_type(void) { return acpi_sleep_from_pm1(acpi_read16(MMIO_ACPI_PM1_CNT_BLK)); diff --git a/src/soc/amd/common/block/include/amdblocks/acpi.h b/src/soc/amd/common/block/include/amdblocks/acpi.h index 8d0e5f6..b6244cb 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpi.h +++ b/src/soc/amd/common/block/include/amdblocks/acpi.h @@ -36,8 +36,6 @@ /* Fill GNVS object from PM GPE object. */ void acpi_fill_gnvs(struct global_nvs *gnvs, const struct acpi_pm_gpe_state *state); -void acpi_clear_pm1_status(void); - /* * If a system reset is about to be requested, modify the PM1 register so it * will never be misinterpreted as an S3 resume. -- To view, visit https://review.coreboot.org/c/coreboot/+/44485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I18c4c8b0c7852dde8cf0b6b3f11e43e15c3ce155 Gerrit-Change-Number: 44485 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/picasso: use new ACPI helper functions from common
by Aaron Durbin (Code Review) 17 Aug '20

17 Aug '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44484 ) Change subject: soc/amd/picasso: use new ACPI helper functions from common ...................................................................... soc/amd/picasso: use new ACPI helper functions from common Transition the current call sequence to using the newly added common ACPI helper functions. Semantically, the expectations are that this sequence is the equivalent of previous acpi_clear_pm1_status(). However, in subsequent patches picasso will be snapshotting state way sooner than ramstage. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I34e2ba7c5cd123b98c39291537e74175ec043e85 --- M src/soc/amd/picasso/southbridge.c 1 file changed, 14 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/44484/1 diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 0b45c10..ff8e436 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -273,51 +273,19 @@ PM_ACPI_TIMER_EN_EN); } -static int get_index_bit(uint32_t value, uint16_t limit) -{ - uint16_t i; - uint32_t t; - - if (limit >= TOTAL_BITS(uint32_t)) - return -1; - - /* get a mask of valid bits. Ex limit = 3, set bits 0-2 */ - t = (1 << limit) - 1; - if ((value & t) == 0) - return -1; - t = 1; - for (i = 0; i < limit; i++) { - if (value & t) - break; - t <<= 1; - } - return i; -} - static void set_nvs_sws(void *unused) { - struct soc_power_reg *sws; + struct acpi_pm_gpe_state *state; struct global_nvs *gnvs; - int index; - sws = cbmem_find(CBMEM_ID_POWER_STATE); - if (sws == NULL) + state = cbmem_find(CBMEM_ID_POWER_STATE); + if (state == NULL) return; gnvs = acpi_get_gnvs(); if (gnvs == NULL) return; - index = get_index_bit(sws->pm1_sts & sws->pm1_en, PM1_LIMIT); - if (index < 0) - gnvs->pm1i = ~0ULL; - else - gnvs->pm1i = index; - - index = get_index_bit(sws->gpe0_sts & sws->gpe0_en, GPE0_LIMIT); - if (index < 0) - gnvs->gpei = ~0ULL; - else - gnvs->gpei = index; + acpi_fill_gnvs(gnvs, state); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); @@ -341,9 +309,18 @@ void southbridge_init(void *chip_info) { + struct acpi_pm_gpe_state *state; + i2c_soc_init(); sb_init_acpi_ports(); - acpi_clear_pm1_status(); + + state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); + if (state) { + acpi_fill_pm_gpe_state(state); + acpi_pm_gpe_add_events_print_events(state); + } + acpi_clear_pm_gpe_status(); + al2ahb_clock_gate(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34e2ba7c5cd123b98c39291537e74175ec043e85 Gerrit-Change-Number: 44484 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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