coreboot-gerrit August 2020

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Change in coreboot[master]: src: Remove unused 'include <lib.h>'
by HAOUAS Elyes (Code Review) 18 Aug '20

18 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44100 ) Change subject: src: Remove unused 'include <lib.h>' ...................................................................... src: Remove unused 'include <lib.h>' Change-Id: Ic09fc4ff4ee5524d89366e28d1d22900dd0c5b4d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/intel/fsp2_0/util.c M src/northbridge/intel/ironlake/raminit.c M src/security/intel/txt/ramstage.c M src/soc/intel/common/block/cse/cse_lite.c 4 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/44100/1 diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index cfa83d7..acc3f4b 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -8,7 +8,6 @@ #include <commonlib/fsp.h> #include <console/console.h> #include <fsp/util.h> -#include <lib.h> #include <string.h> #include <types.h> diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index f50adb1..17901b0 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -82,8 +82,6 @@ u32 reg_6e8; }; -#include <lib.h> /* Prototypes */ - typedef struct _u128 { u64 lo; u64 hi; diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 8627a2b..145182f 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -10,7 +10,6 @@ #include <cpu/intel/common/common.h> #include <cpu/x86/msr.h> -#include <lib.h> #include <device/pci_ops.h> #include "txt.h" diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index a12f2d0..a2ff4a8 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -7,7 +7,6 @@ #include <commonlib/region.h> #include <fmap.h> #include <intelblocks/cse.h> -#include <lib.h> #include <security/vboot/vboot_common.h> #include <security/vboot/misc.h> #include <vb2_api.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/44100 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic09fc4ff4ee5524d89366e28d1d22900dd0c5b4d Gerrit-Change-Number: 44100 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Remove unuse '<timestamp.h>
by HAOUAS Elyes (Code Review) 18 Aug '20

18 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44099 ) Change subject: src: Remove unuse '<timestamp.h> ...................................................................... src: Remove unuse '<timestamp.h> Change-Id: I4fa03c4576bb0256b73f1d36ca840e120b750a74 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/amd/agesa/bootblock.c M src/soc/amd/picasso/psp_verstage/fch.c M src/soc/qualcomm/sc7180/aop_load_reset.c M src/soc/qualcomm/sc7180/gpio.c 4 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/44099/1 diff --git a/src/drivers/amd/agesa/bootblock.c b/src/drivers/amd/agesa/bootblock.c index 4ef3f40..df9876a 100644 --- a/src/drivers/amd/agesa/bootblock.c +++ b/src/drivers/amd/agesa/bootblock.c @@ -2,7 +2,6 @@ #include <bootblock_common.h> #include <halt.h> -#include <timestamp.h> #include <amdblocks/amd_pci_mmconf.h> #include <amdblocks/biosram.h> #include <arch/bootblock.h> diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 499f4e2..89e7014 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -14,7 +14,6 @@ #include <soc/i2c.h> #include <soc/southbridge.h> #include <stdint.h> -#include <timestamp.h> static void i2c3_set_bar(void *bar) { diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c index b88a097..eb90f86 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -2,7 +2,6 @@ #include <cbfs.h> #include <console/console.h> -#include <timestamp.h> #include <soc/mmu.h> #include <soc/aop.h> #include <soc/clock.h> diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c index f175ce5..67204e8 100644 --- a/src/soc/qualcomm/sc7180/gpio.c +++ b/src/soc/qualcomm/sc7180/gpio.c @@ -2,7 +2,6 @@ #include <assert.h> #include <device/mmio.h> -#include <timestamp.h> #include <types.h> #include <gpio.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/44099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4fa03c4576bb0256b73f1d36ca840e120b750a74 Gerrit-Change-Number: 44099 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Remove unused '<halt.h>'
by HAOUAS Elyes (Code Review) 18 Aug '20

18 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44098 ) Change subject: src: Remove unused '<halt.h>' ...................................................................... src: Remove unused '<halt.h>' Change-Id: I3037edf89c933f4f136ca61d6a5bce41126ec6b9 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/qualcomm/sc7180/aop_load_reset.c M src/southbridge/intel/bd82x6x/me.c M src/southbridge/intel/bd82x6x/me_8.x.c M src/southbridge/intel/lynxpoint/me_9.x.c 4 files changed, 0 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/44098/1 diff --git a/src/soc/qualcomm/sc7180/aop_load_reset.c b/src/soc/qualcomm/sc7180/aop_load_reset.c index 85ea67e..b88a097 100644 --- a/src/soc/qualcomm/sc7180/aop_load_reset.c +++ b/src/soc/qualcomm/sc7180/aop_load_reset.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbfs.h> -#include <halt.h> #include <console/console.h> #include <timestamp.h> #include <soc/mmu.h> diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 03b954f..1c56e5e 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -19,7 +19,6 @@ #include <string.h> #include <delay.h> #include <elog.h> -#include <halt.h> #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index ff94a88..d60a09c 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -19,7 +19,6 @@ #include <string.h> #include <delay.h> #include <elog.h> -#include <halt.h> #include "me.h" #include "pch.h" diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index d182e31..051c3e9 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -19,7 +19,6 @@ #include <string.h> #include <delay.h> #include <elog.h> -#include <halt.h> #include <stdlib.h> #include "chip.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/44098 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3037edf89c933f4f136ca61d6a5bce41126ec6b9 Gerrit-Change-Number: 44098 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Remove unused '<option.h>'
by HAOUAS Elyes (Code Review) 18 Aug '20

18 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44097 ) Change subject: src: Remove unused '<option.h>' ...................................................................... src: Remove unused '<option.h>' Change-Id: Icb79d60e9ec70a0780d5231698b88cff1db72c9b Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/pc80/rtc/mc146818rtc.c M src/drivers/pc80/rtc/mc146818rtc_boot.c M src/mainboard/lenovo/t430s/variants/t431s/romstage.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/44097/1 diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index d58a999..21d3c00 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -6,7 +6,6 @@ #include <fallback.h> #include <version.h> #include <console/console.h> -#include <option.h> #include <pc80/mc146818rtc.h> #include <rtc.h> #include <security/vboot/vbnv.h> diff --git a/src/drivers/pc80/rtc/mc146818rtc_boot.c b/src/drivers/pc80/rtc/mc146818rtc_boot.c index fbcf387..550a602 100644 --- a/src/drivers/pc80/rtc/mc146818rtc_boot.c +++ b/src/drivers/pc80/rtc/mc146818rtc_boot.c @@ -2,7 +2,6 @@ #include <stdint.h> #include <console/console.h> -#include <option.h> #include <pc80/mc146818rtc.h> #include <fallback.h> diff --git a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c index 923e379..60a1b01 100644 --- a/src/mainboard/lenovo/t430s/variants/t431s/romstage.c +++ b/src/mainboard/lenovo/t430s/variants/t431s/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <option.h> #include <console/console.h> #include <cbfs.h> #include <northbridge/intel/sandybridge/raminit_native.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/44097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb79d60e9ec70a0780d5231698b88cff1db72c9b Gerrit-Change-Number: 44097 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/block/pmc/pmclib.c: Remove unused '<pc80/mc146818rtc...
by HAOUAS Elyes (Code Review) 18 Aug '20

18 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44096 ) Change subject: soc/intel/common/block/pmc/pmclib.c: Remove unused '<pc80/mc146818rtc.h>' ...................................................................... soc/intel/common/block/pmc/pmclib.c: Remove unused '<pc80/mc146818rtc.h>' Change-Id: If7e99e1b1be38694ad2fedb528a5c1725b968943 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/common/block/pmc/pmclib.c 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/44096/1 diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 12eb38e..40d407b 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -10,7 +10,6 @@ #include <intelblocks/gpio.h> #include <intelblocks/tco.h> #include <option.h> -#include <pc80/mc146818rtc.h> #include <security/vboot/vboot_common.h> #include <soc/pm.h> #include <stdint.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/44096 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If7e99e1b1be38694ad2fedb528a5c1725b968943 Gerrit-Change-Number: 44096 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/amd/agesa/hudson: Add missing '#include <stddef.h>'
by HAOUAS Elyes (Code Review) 18 Aug '20

18 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43939 ) Change subject: sb/amd/agesa/hudson: Add missing '#include <stddef.h>' ...................................................................... sb/amd/agesa/hudson: Add missing '#include <stddef.h>' size_t needs <stddef.h>. Change-Id: I9ccf526df44dbad8568f75bd0506ac686fdb7860 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/smbus_spd.c M src/southbridge/amd/agesa/hudson/spi.c 2 files changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/43939/1 diff --git a/src/southbridge/amd/agesa/hudson/smbus_spd.c b/src/southbridge/amd/agesa/hudson/smbus_spd.c index e0f36ca..7dcbbf9 100644 --- a/src/southbridge/amd/agesa/hudson/smbus_spd.c +++ b/src/southbridge/amd/agesa/hudson/smbus_spd.c @@ -4,6 +4,7 @@ #include <device/pci_def.h> #include <device/device.h> #include <console/console.h> +#include <stddef.h> /* warning: Porting.h includes an open #pragma pack(1) */ #include <Porting.h> #include <AGESA.h> diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index cce11dc..b2f9ff2 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -1,4 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + #include <stdint.h> #include <device/mmio.h> #include <console/console.h> @@ -7,6 +8,7 @@ #include <device/device.h> #include <device/pci.h> #include <device/pci_ops.h> +#include <stddef.h> #include <Proc/Fch/FchPlatform.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/43939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9ccf526df44dbad8568f75bd0506ac686fdb7860 Gerrit-Change-Number: 43939 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Remove unused 'include <stddef.h>
by HAOUAS Elyes (Code Review) 18 Aug '20

18 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/41912 ) Change subject: src: Remove unused 'include <stddef.h> ...................................................................... src: Remove unused 'include <stddef.h> Also replace it by <stdint.h> when 'stdint' is missing. Change-Id: Iae1e875b466f8a195653d897efa1b297c61ad0a5 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/arch/riscv/arch_timer.c M src/arch/riscv/misaligned.c M src/arch/riscv/smp.c M src/console/printk.c M src/drivers/usb/ehci_debug.c M src/drivers/usb/gadget.c M src/lib/timer_queue.c M src/lib/timestamp.c M src/mainboard/google/daisy/memory.c M src/mainboard/google/zork/variants/dalboz/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/soc/intel/baytrail/northcluster.c M src/soc/intel/baytrail/romstage/pmc.c M src/soc/intel/baytrail/romstage/raminit.c M src/soc/intel/baytrail/romstage/romstage.c M src/soc/intel/braswell/romstage/romstage.c M src/soc/nvidia/tegra124/dma.c M src/soc/nvidia/tegra210/dma.c M src/soc/rockchip/rk3399/display.c M src/southbridge/intel/lynxpoint/pcie.c 20 files changed, 9 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/41912/1 diff --git a/src/arch/riscv/arch_timer.c b/src/arch/riscv/arch_timer.c index 7e9072b..ad678b7 100644 --- a/src/arch/riscv/arch_timer.c +++ b/src/arch/riscv/arch_timer.c @@ -3,7 +3,6 @@ #include <device/mmio.h> #include <arch/encoding.h> #include <console/console.h> -#include <stddef.h> #include <timer.h> #include <mcall.h> diff --git a/src/arch/riscv/misaligned.c b/src/arch/riscv/misaligned.c index eff51fc..244081f 100644 --- a/src/arch/riscv/misaligned.c +++ b/src/arch/riscv/misaligned.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stddef.h> #include <stdint.h> #include <vm.h> #include <arch/exception.h> diff --git a/src/arch/riscv/smp.c b/src/arch/riscv/smp.c index b3e13ff..1d58602 100644 --- a/src/arch/riscv/smp.c +++ b/src/arch/riscv/smp.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stddef.h> #include <arch/encoding.h> #include <arch/smp/smp.h> #include <arch/smp/spinlock.h> diff --git a/src/console/printk.c b/src/console/printk.c index c5e5f97..4a3de47 100644 --- a/src/console/printk.c +++ b/src/console/printk.c @@ -10,7 +10,6 @@ #include <console/vtxprintf.h> #include <smp/spinlock.h> #include <smp/node.h> -#include <stddef.h> #include <trace.h> #include <timer.h> diff --git a/src/drivers/usb/ehci_debug.c b/src/drivers/usb/ehci_debug.c index 739e599..3463741 100644 --- a/src/drivers/usb/ehci_debug.c +++ b/src/drivers/usb/ehci_debug.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stddef.h> +#include <stdint.h> #include <console/console.h> #include <console/usb.h> #include <arch/io.h> diff --git a/src/drivers/usb/gadget.c b/src/drivers/usb/gadget.c index 48a83d2..b7aad23 100644 --- a/src/drivers/usb/gadget.c +++ b/src/drivers/usb/gadget.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stddef.h> +#include <stdint.h> #include <console/console.h> #include <string.h> diff --git a/src/lib/timer_queue.c b/src/lib/timer_queue.c index f368409..badc600 100644 --- a/src/lib/timer_queue.c +++ b/src/lib/timer_queue.c @@ -1,5 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stddef.h> + #include <timer.h> #define MAX_TIMER_QUEUE_ENTRIES 64 diff --git a/src/lib/timestamp.c b/src/lib/timestamp.c index d10b138..e621629 100644 --- a/src/lib/timestamp.c +++ b/src/lib/timestamp.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <stddef.h> #include <stdint.h> #include <console/console.h> #include <cbmem.h> diff --git a/src/mainboard/google/daisy/memory.c b/src/mainboard/google/daisy/memory.c index a5b7d3c..5dc9c3e 100644 --- a/src/mainboard/google/daisy/memory.c +++ b/src/mainboard/google/daisy/memory.c @@ -5,7 +5,6 @@ #include <soc/setup.h> #include <soc/dmc.h> #include <soc/clk.h> -#include <stddef.h> const struct mem_timings mem_timings[] = { { diff --git a/src/mainboard/google/zork/variants/dalboz/romstage.c b/src/mainboard/google/zork/variants/dalboz/romstage.c index 42e36c4..e903686 100644 --- a/src/mainboard/google/zork/variants/dalboz/romstage.c +++ b/src/mainboard/google/zork/variants/dalboz/romstage.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include <stddef.h> +#include <stdint.h> #include <soc/romstage.h> #include <baseboard/variants.h> #include <ec/google/chromeec/ec.h> diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index a628105..d6b6c1e 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <stdint.h> -#include <stddef.h> #include <arch/romstage.h> #include <cpu/intel/haswell/haswell.h> #include <northbridge/intel/haswell/haswell.h> diff --git a/src/soc/intel/baytrail/northcluster.c b/src/soc/intel/baytrail/northcluster.c index 32b1385..9c4b528 100644 --- a/src/soc/intel/baytrail/northcluster.c +++ b/src/soc/intel/baytrail/northcluster.c @@ -5,7 +5,7 @@ #include <device/pci_ids.h> #include <vendorcode/google/chromeos/chromeos.h> #include <acpi/acpi.h> -#include <stddef.h> +#include <stdint.h> #include <soc/iomap.h> #include <soc/iosf.h> #include <soc/pci_devs.h> diff --git a/src/soc/intel/baytrail/romstage/pmc.c b/src/soc/intel/baytrail/romstage/pmc.c index 48a8e71..b4ea555 100644 --- a/src/soc/intel/baytrail/romstage/pmc.c +++ b/src/soc/intel/baytrail/romstage/pmc.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stddef.h> +#include <stdint.h> #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 1d1bd30..c853f35 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stddef.h> +#include <stdint.h> #include <acpi/acpi.h> #include <assert.h> #include <cbfs.h> diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index fa17351..2da7d69 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stddef.h> #include <arch/io.h> #include <arch/romstage.h> #include <device/mmio.h> diff --git a/src/soc/intel/braswell/romstage/romstage.c b/src/soc/intel/braswell/romstage/romstage.c index 77d13c4..b6b20b9 100644 --- a/src/soc/intel/braswell/romstage/romstage.c +++ b/src/soc/intel/braswell/romstage/romstage.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <cbmem.h> -#include <stddef.h> +#include <stdint.h> #include <arch/io.h> #include <device/mmio.h> #include <console/console.h> diff --git a/src/soc/nvidia/tegra124/dma.c b/src/soc/nvidia/tegra124/dma.c index a6fa93b..167f4a1 100644 --- a/src/soc/nvidia/tegra124/dma.c +++ b/src/soc/nvidia/tegra124/dma.c @@ -5,7 +5,6 @@ #include <stdint.h> #include <soc/addressmap.h> #include <soc/dma.h> -#include <stddef.h> struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; diff --git a/src/soc/nvidia/tegra210/dma.c b/src/soc/nvidia/tegra210/dma.c index db57191..26b64c8 100644 --- a/src/soc/nvidia/tegra210/dma.c +++ b/src/soc/nvidia/tegra210/dma.c @@ -5,7 +5,6 @@ #include <stdint.h> #include <soc/addressmap.h> #include <soc/dma.h> -#include <stddef.h> struct apb_dma * const apb_dma = (struct apb_dma *)TEGRA_APB_DMA_BASE; diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index b47fabc..70e8c7c 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -7,7 +7,7 @@ #include <delay.h> #include <edid.h> #include <gpio.h> -#include <stddef.h> +#include <stdint.h> #include <soc/addressmap.h> #include <soc/clock.h> #include <soc/display.h> diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index e11a0b7..8a233da 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -11,7 +11,6 @@ #include <device/pci_ops.h> #include "pch.h" #include <southbridge/intel/common/gpio.h> -#include <stddef.h> #include <stdint.h> #include "chip.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/41912 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iae1e875b466f8a195653d897efa1b297c61ad0a5 Gerrit-Change-Number: 41912 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src: Remove unused 'include <boot_device.h>'
by HAOUAS Elyes (Code Review) 18 Aug '20

18 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42349 ) Change subject: src: Remove unused 'include <boot_device.h>' ...................................................................... src: Remove unused 'include <boot_device.h>' Change-Id: I5589fdeade7f69995adf1c983ced13773472be74 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/security/vboot/vboot_common.c M src/soc/nvidia/tegra124/spi.c M src/soc/nvidia/tegra210/spi.c 3 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/42349/1 diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 1cddeeb..9a49510 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <boot_device.h> #include <cbmem.h> #include <console/cbmem_console.h> #include <reset.h> diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index adf0248..18ea626 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -4,7 +4,6 @@ #include <arch/cache.h> #include <device/mmio.h> #include <assert.h> -#include <boot_device.h> #include <console/console.h> #include <delay.h> #include <soc/addressmap.h> diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index 8fde9c2..067d77e 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -4,7 +4,6 @@ #include <arch/cache.h> #include <device/mmio.h> #include <assert.h> -#include <boot_device.h> #include <console/console.h> #include <delay.h> #include <spi-generic.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/42349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5589fdeade7f69995adf1c983ced13773472be74 Gerrit-Change-Number: 42349 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/early_pch.c: Use common 'write_pmbase16()'
by HAOUAS Elyes (Code Review) 18 Aug '20

18 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44413 ) Change subject: sb/intel/lynxpoint/early_pch.c: Use common 'write_pmbase16()' ...................................................................... sb/intel/lynxpoint/early_pch.c: Use common 'write_pmbase16()' Change-Id: I1a70eea8c4f835e5673e75282c9cecb24b150e3d Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/intel/lynxpoint/early_pch.c 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44413/1 diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index e74fdc5..85f9f33 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -6,6 +6,7 @@ #include <device/device.h> #include <device/pci_def.h> #include <device/smbus_host.h> +#include <southbridge/intel/common/pmbase.h> #include <southbridge/intel/common/pmclib.h> #include <elog.h> #include "pch.h" @@ -57,7 +58,7 @@ { printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ - outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + write_pmbase16(0x60 | 0x08, (1 << 11)); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44413 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1a70eea8c4f835e5673e75282c9cecb24b150e3d Gerrit-Change-Number: 44413 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/southbridge/amd/*/*/fadt.c: Use macro for access_size
by HAOUAS Elyes (Code Review) 18 Aug '20

18 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44519 ) Change subject: src/southbridge/amd/*/*/fadt.c: Use macro for access_size ...................................................................... src/southbridge/amd/*/*/fadt.c: Use macro for access_size Change-Id: I316abf6626adabeecdf9639712ab3bf64e3cbe83 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/southbridge/amd/agesa/hudson/fadt.c M src/southbridge/amd/cimx/sb800/fadt.c M src/southbridge/amd/pi/hudson/fadt.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/44519/1 diff --git a/src/southbridge/amd/agesa/hudson/fadt.c b/src/southbridge/amd/agesa/hudson/fadt.c index 220b327..ef11c86 100644 --- a/src/southbridge/amd/agesa/hudson/fadt.c +++ b/src/southbridge/amd/agesa/hudson/fadt.c @@ -77,7 +77,7 @@ fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; diff --git a/src/southbridge/amd/cimx/sb800/fadt.c b/src/southbridge/amd/cimx/sb800/fadt.c index 3868d24..a5c27d6 100644 --- a/src/southbridge/amd/cimx/sb800/fadt.c +++ b/src/southbridge/amd/cimx/sb800/fadt.c @@ -101,7 +101,7 @@ fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_pm1a_cnt_blk.addrl = PM1_CNT_BLK_ADDRESS; fadt->x_pm1a_cnt_blk.addrh = 0x0; diff --git a/src/southbridge/amd/pi/hudson/fadt.c b/src/southbridge/amd/pi/hudson/fadt.c index 0b73921..319bdf3 100644 --- a/src/southbridge/amd/pi/hudson/fadt.c +++ b/src/southbridge/amd/pi/hudson/fadt.c @@ -79,7 +79,7 @@ fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; fadt->x_pm1a_cnt_blk.bit_width = 16; fadt->x_pm1a_cnt_blk.bit_offset = 0; - fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.access_size = ACPI_ACCESS_SIZE_UNDEFINED; fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; fadt->x_pm1a_cnt_blk.addrh = 0x0; -- To view, visit https://review.coreboot.org/c/coreboot/+/44519 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I316abf6626adabeecdf9639712ab3bf64e3cbe83 Gerrit-Change-Number: 44519 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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