coreboot-gerrit August 2020

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Change in coreboot[master]: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
by Subrata Banik (Code Review) 18 Aug '20

18 Aug '20

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/29667 ) Change subject: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support ...................................................................... Patch Set 41: (1 comment) https://review.coreboot.org/c/coreboot/+/29667/41/Documentation/arch/x86/in… File Documentation/arch/x86/index.md: https://review.coreboot.org/c/coreboot/+/29667/41/Documentation/arch/x86/in… PS41, Line 52: Identity map memory above 4GiB in ramstag isn't this done https://review.coreboot.org/c/coreboot/+/39488 https://review.coreboot.org/c/coreboot/+/39487/18 -- To view, visit https://review.coreboot.org/c/coreboot/+/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 41 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Tue, 18 Aug 2020 10:05:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: xeon_sp/cpx: Fix get_system_memory_map to return the correct address
by Johnny Lin (Code Review) 18 Aug '20

18 Aug '20

Johnny Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44502 ) Change subject: xeon_sp/cpx: Fix get_system_memory_map to return the correct address ...................................................................... xeon_sp/cpx: Fix get_system_memory_map to return the correct address Similar to CB:43336, the HOB structure is actually a 8 byte address pointing to the HOB data. Tested=Verified the values of the hob fields are the same printed by soc_display_memmap_hob(). Change-Id: I348d3cd80a56e86d22f20fcadf0316b462b86829 Signed-off-by: Johnny Lin <johnny_lin(a)wiwynn.com> --- M src/soc/intel/xeon_sp/cpx/soc_util.c 1 file changed, 7 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/44502/1 diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index fb78910a1..4153104 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -29,14 +29,17 @@ { size_t hob_size; const uint8_t mem_hob_guid[16] = FSP_SYSTEM_MEMORYMAP_HOB_GUID; + const struct SystemMemoryMapHob **memmap_addr; - const void *memmap_addr = fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); - assert(memmap_addr != NULL && hob_size != 0); - printk(BIOS_DEBUG, "FSP_SYSTEM_MEMORYMAP_HOB_GUID hob_size: %ld\n", hob_size); + memmap_addr = (const struct SystemMemoryMapHob **) + fsp_find_extension_hob_by_guid(mem_hob_guid, &hob_size); + /* hob_size is the size of the 8-byte address not the hob data */ + assert(memmap_addr != NULL && *memmap_addr != NULL && hob_size != 0); - return (const struct SystemMemoryMapHob *) memmap_addr; + return (const struct SystemMemoryMapHob *)*memmap_addr; } + void get_cpu_info_from_apicid(uint32_t apicid, uint32_t core_bits, uint32_t thread_bits, uint8_t *package, uint8_t *core, uint8_t *thread) { -- To view, visit https://review.coreboot.org/c/coreboot/+/44502 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I348d3cd80a56e86d22f20fcadf0316b462b86829 Gerrit-Change-Number: 44502 Gerrit-PatchSet: 1 Gerrit-Owner: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-MessageType: newchange

4 8

Change in coreboot[master]: util/intelp2m: Add support for Cannonlake-LP SoCs
by Matt DeVillier (Code Review) 18 Aug '20

18 Aug '20

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44457 ) Change subject: util/intelp2m: Add support for Cannonlake-LP SoCs ...................................................................... util/intelp2m: Add support for Cannonlake-LP SoCs Add support for Cannonlake-LP SoCs (Whiskeylake-U, Coffeelake-U, Cometlake-U) as a separate parsing profile, copying the existing 'Sunrise' profile and adjusting for differences in reset mapping and GPIO macro generation Test: convert inteltool GPIO log dump into coreboot macros for an out-of-tree CML-U board. Change-Id: I86296697ee892af7aa0818fb608b6d68fad2f307 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M util/intelp2m/config/config.go M util/intelp2m/description.md M util/intelp2m/main.go M util/intelp2m/parser/parser.go A util/intelp2m/platforms/cnl/macro.go A util/intelp2m/platforms/cnl/template.go 6 files changed, 302 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/44457/1 diff --git a/util/intelp2m/config/config.go b/util/intelp2m/config/config.go index 9f0b757..724de8c 100644 --- a/util/intelp2m/config/config.go +++ b/util/intelp2m/config/config.go @@ -27,6 +27,7 @@ SunriseType uint8 = 0 LewisburgType uint8 = 1 ApolloType uint8 = 2 + CannonType uint8 = 3 ) var key uint8 = SunriseType @@ -34,7 +35,8 @@ var platform = map[string]uint8{ "snr": SunriseType, "lbg": LewisburgType, - "apl": ApolloType} + "apl": ApolloType, + "cnl": CannonType} func PlatformSet(name string) int { if platformType, valid := platform[name]; valid { key = platformType @@ -57,6 +59,9 @@ func IsPlatformLewisburg() bool { return IsPlatform(LewisburgType) } +func IsPlatformCannonLake() bool { + return IsPlatform(CannonType) +} var InputRegDumpFile *os.File = nil var OutputGenFile *os.File = nil diff --git a/util/intelp2m/description.md b/util/intelp2m/description.md index 3008c04..19a7e76 100644 --- a/util/intelp2m/description.md +++ b/util/intelp2m/description.md @@ -37,6 +37,7 @@ snr - Sunrise PCH with Skylake/Kaby Lake CPU lbg - Lewisburg PCH with Xeon SP CPU apl - Apollo Lake SoC + cnp - CannonPoint-LP PCH or Whiskeylake/Coffelake/Cometlake-U SoC (default "snr") (shell)$ ./intelp2m -p <platform> -file path/to/inteltool.log @@ -198,4 +199,4 @@ ``` ### Supports Chipsets - Sunrise PCH, Lewisburg PCH, Apollo Lake SoC + Sunrise PCH, Lewisburg PCH, Apollo Lake SoC, CannonPoint-LP PCH diff --git a/util/intelp2m/main.go b/util/intelp2m/main.go index 6c6dc343..8527c54 100644 --- a/util/intelp2m/main.go +++ b/util/intelp2m/main.go @@ -81,7 +81,8 @@ platform := flag.String("p", "snr", "set platform:\n"+ "\tsnr - Sunrise PCH or Skylake/Kaby Lake SoC\n"+ "\tlbg - Lewisburg PCH with Xeon SP\n"+ - "\tapl - Apollo Lake SoC\n") + "\tapl - Apollo Lake SoC\n"+ + "\tcnl - CannonLake-LP or Whiskeylake/Coffelake/Cometlake-U SoC\n") filedstyle := flag.String("fld", "none", "set fileds macros style:\n"+ "\tcb - use coreboot style for bit fields macros\n"+ diff --git a/util/intelp2m/parser/parser.go b/util/intelp2m/parser/parser.go index f002cc9..8941487 100644 --- a/util/intelp2m/parser/parser.go +++ b/util/intelp2m/parser/parser.go @@ -10,6 +10,7 @@ import "../platforms/snr" import "../platforms/lbg" import "../platforms/apl" +import "../platforms/cnl" import "../config" // PlatformSpecific - platform-specific interface @@ -141,6 +142,7 @@ InheritanceTemplate : snr.PlatformSpecific{}, }, config.ApolloType : apl.PlatformSpecific{}, + config.CannonType : cnl.PlatformSpecific{}, } parser.platform = platform[config.PlatformGet()] } @@ -198,7 +200,7 @@ // padConfigurationExtract - reads GPIO configuration registers and returns true if the // information from the inteltool log was successfully parsed. func (parser *ParserData) padConfigurationExtract() bool { - // Only for Sunrise PCH and only for inteltool.log file template + // Only for Sunrise or CannonLake, and only for inteltool.log file template if config.TemplateGet() != config.TempInteltool || config.IsPlatformApollo() { return false } diff --git a/util/intelp2m/platforms/cnl/macro.go b/util/intelp2m/platforms/cnl/macro.go new file mode 100644 index 0000000..a86ddd4 --- /dev/null +++ b/util/intelp2m/platforms/cnl/macro.go @@ -0,0 +1,254 @@ +package cnl + +import "strings" +import "fmt" + +// Local packages +import "../common" +import "../../config" +import "../../fields" + +const ( + PAD_CFG_DW0_RO_FIELDS = (0x1 << 27) | (0x1 << 24) | (0x3 << 21) | (0xf << 16) | 0xfc + PAD_CFG_DW1_RO_FIELDS = 0xfdffc3ff +) + +const ( + PAD_CFG_DW0 = common.PAD_CFG_DW0 + PAD_CFG_DW1 = common.PAD_CFG_DW1 + MAX_DW_NUM = common.MAX_DW_NUM +) + +type PlatformSpecific struct {} + +// RemmapRstSrc - remmap Pad Reset Source Config +func (PlatformSpecific) RemmapRstSrc() { + macro := common.GetMacro() + if config.TemplateGet() != config.TempInteltool { + // Use reset source remapping only if the input file is inteltool.log dump + return + } + if strings.Contains(macro.PadIdGet(), "GPP_A") || + strings.Contains(macro.PadIdGet(), "GPP_B") || + strings.Contains(macro.PadIdGet(), "GPP_G") { + // See reset map for the Cannonlake Groups the Community 0: + // https://github.com/coreboot/coreboot/blob/master/src/soc/intel/cannonlake/g… + // remmap is not required because it is the same as common. + return + } + + dw0 := macro.Register(PAD_CFG_DW0) + var remapping = map[uint8]uint32{ + 0: common.RST_RSMRST << common.PadRstCfgShift, + 1: common.RST_DEEP << common.PadRstCfgShift, + 2: common.RST_PLTRST << common.PadRstCfgShift, + } + resetsrc, valid := remapping[dw0.GetResetConfig()] + if valid { + // dw0.SetResetConfig(resetsrc) + ResetConfigFieldVal := (dw0.ValueGet() & 0x3fffffff) | remapping[dw0.GetResetConfig()] + dw0.ValueSet(ResetConfigFieldVal) + } else { + fmt.Println("Invalid Pad Reset Config [ 0x", resetsrc ," ] for ", macro.PadIdGet()) + } + dw0.CntrMaskFieldsClear(common.PadRstCfgMask) +} + +// Adds The Pad Termination (TERM) parameter from PAD_CFG_DW1 to the macro +// as a new argument +func (PlatformSpecific) Pull() { + macro := common.GetMacro() + dw1 := macro.Register(PAD_CFG_DW1) + var pull = map[uint8]string{ + 0x0: "NONE", + 0x2: "DN_5K", + 0x4: "DN_20K", + 0x9: "UP_1K", + 0xa: "UP_5K", + 0xb: "UP_2K", + 0xc: "UP_20K", + 0xd: "UP_667", + 0xf: "NATIVE", + } + str, valid := pull[dw1.GetTermination()] + if !valid { + str = "INVALID" + fmt.Println("Error", + macro.PadIdGet(), + " invalid TERM value = ", + int(dw1.GetTermination())) + } + macro.Separator().Add(str) +} + +// Generate macro to cause peripheral IRQ when configured in GPIO input mode +func ioApicRoute() bool { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + if dw0.GetGPIOInputRouteIOxAPIC() == 0 { + return false + } + + macro.Add("_APIC") + // PAD_CFG_GPI_APIC(pad, pull, rst, trig, inv) + macro.Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") + return true + +} + +// Generate macro to cause NMI when configured in GPIO input mode +func nmiRoute() bool { + macro := common.GetMacro() + if macro.Register(PAD_CFG_DW0).GetGPIOInputRouteNMI() == 0 { + return false + } + // PAD_CFG_GPI_NMI(GPIO_24, UP_20K, DEEP, LEVEL, INVERT), + macro.Add("_NMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") + return true +} + +// Generate macro to cause SCI when configured in GPIO input mode +func sciRoute() bool { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + if dw0.GetGPIOInputRouteSCI() == 0 { + return false + } + // PAD_CFG_GPI_SCI(pad, pull, rst, trig, inv) + macro.Add("_SCI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") + return true +} + + +// Generate macro to cause SMI when configured in GPIO input mode +func smiRoute() bool { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + if dw0.GetGPIOInputRouteSMI() == 0 { + return false + } + // PAD_CFG_GPI_SMI(pad, pull, rst, trig, inv) + macro.Add("_SMI").Add("(").Id().Pull().Rstsrc().Trig().Invert().Add("),") + return true +} + +// Adds PAD_CFG_GPI macro with arguments +func (PlatformSpecific) GpiMacroAdd() { + macro := common.GetMacro() + var ids []string + macro.Set("PAD_CFG_GPI") + for routeid, isRoute := range map[string]func() (bool) { + "IOAPIC": ioApicRoute, + "SCI": sciRoute, + "SMI": smiRoute, + "NMI": nmiRoute, + } { + if isRoute() { + ids = append(ids, routeid) + } + } + + switch argc := len(ids); argc { + case 0: + // e.g. PAD_CFG_GPI_TRIG_OWN(pad, pull, rst, trig, own) + macro.Add("_TRIG_OWN").Add("(").Id().Pull().Rstsrc().Trig().Own().Add("),") + case 1: + // GPI with IRQ route + if config.AreFieldsIgnored() { + // Set Host Software Ownership to ACPI mode + macro.SetPadOwnership(common.PAD_OWN_ACPI) + } + + case 2: + // PAD_CFG_GPI_DUAL_ROUTE(pad, pull, rst, trig, inv, route1, route2) + macro.Set("PAD_CFG_GPI_DUAL_ROUTE(").Id().Pull().Rstsrc().Trig().Invert() + macro.Add(", " + ids[0] + ", " + ids[1] + "),") + if config.AreFieldsIgnored() { + // Set Host Software Ownership to ACPI mode + macro.SetPadOwnership(common.PAD_OWN_ACPI) + } + default: + // Clear the control mask so that the check fails and "Advanced" macro is + // generated + macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields) + } +} + +// Adds PAD_CFG_GPO macro with arguments +func (PlatformSpecific) GpoMacroAdd() { + macro := common.GetMacro() + dw0 := macro.Register(PAD_CFG_DW0) + term := macro.Register(PAD_CFG_DW1).GetTermination() + + // #define PAD_CFG_GPO(pad, val, rst) \ + // _PAD_CFG_STRUCT(pad, \ + // PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + // PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ + // PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE)) + if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF { + dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask) + } + macro.Set("PAD_CFG") + if macro.IsOwnershipDriver() { + // PAD_CFG_GPO_GPIO_DRIVER(pad, val, rst, pull) + macro.Add("_GPO_GPIO_DRIVER").Add("(").Id().Val().Rstsrc().Pull().Add("),") + return + } + if term != 0 { + // e.g. PAD_CFG_TERM_GPO(GPP_B23, 1, DN_20K, DEEP), + macro.Add("_TERM") + } + macro.Add("_GPO").Add("(").Id().Val() + if term != 0 { + macro.Pull() + } + macro.Rstsrc().Add("),") +} + +// Adds PAD_CFG_NF macro with arguments +func (PlatformSpecific) NativeFunctionMacroAdd() { + macro := common.GetMacro() + // e.g. PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1) + macro.Set("PAD_CFG_NF") + if macro.Register(PAD_CFG_DW1).GetPadTol() != 0 { + macro.Add("_1V8") + } + macro.Add("(").Id().Pull().Rstsrc().Padfn().Add("),") +} + +// Adds PAD_NC macro +func (PlatformSpecific) NoConnMacroAdd() { + macro := common.GetMacro() + // #define PAD_NC(pad, pull) + // _PAD_CFG_STRUCT(pad, + // PAD_FUNC(GPIO) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), + // PAD_PULL(pull) | PAD_IOSSTATE(TxDRxE)), + dw0 := macro.Register(PAD_CFG_DW0) + + // Some fields of the configuration registers are hidden inside the macros, + // we should check them to update the corresponding bits in the control mask. + if dw0.GetRXLevelEdgeConfiguration() != common.TRIG_OFF { + dw0.CntrMaskFieldsClear(common.RxLevelEdgeConfigurationMask) + } + if dw0.GetResetConfig() != 1 { // 1 = RST_DEEP + dw0.CntrMaskFieldsClear(common.PadRstCfgMask) + } + + macro.Set("PAD_NC").Add("(").Id().Pull().Add("),") +} + +// GenMacro - generate pad macro +// dw0 : DW0 config register value +// dw1 : DW1 config register value +// return: string of macro +// error +func (PlatformSpecific) GenMacro(id string, dw0 uint32, dw1 uint32, ownership uint8) string { + macro := common.GetInstanceMacro(PlatformSpecific{}, fields.InterfaceGet()) + macro.Clear() + macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields) + macro.Register(PAD_CFG_DW0).CntrMaskFieldsClear(common.AllFields) + macro.PadIdSet(id).SetPadOwnership(ownership) + macro.Register(PAD_CFG_DW0).ValueSet(dw0).ReadOnlyFieldsSet(PAD_CFG_DW0_RO_FIELDS) + macro.Register(PAD_CFG_DW1).ValueSet(dw1).ReadOnlyFieldsSet(PAD_CFG_DW1_RO_FIELDS) + return macro.Generate() +} diff --git a/util/intelp2m/platforms/cnl/template.go b/util/intelp2m/platforms/cnl/template.go new file mode 100644 index 0000000..9221109 --- /dev/null +++ b/util/intelp2m/platforms/cnl/template.go @@ -0,0 +1,35 @@ +package cnl + +import "strings" + +// GroupNameExtract - This function extracts the group ID, if it exists in a row +// line : string from the configuration file +// return +// bool : true if the string contains a group identifier +// string : group identifier +func (PlatformSpecific) GroupNameExtract(line string) (bool, string) { + for _, groupKeyword := range []string{ + "GPP_A", "GPP_B", "GPP_G", + "GPP_D", "GPP_F", "GPP_H", + "GPD", "GPP_C", "GPP_E", + } { + if strings.Contains(line, groupKeyword) { + return true, groupKeyword + } + } + return false, "" +} + +// KeywordCheck - This function is used to filter parsed lines of the configuration file and +// returns true if the keyword is contained in the line. +// line : string from the configuration file +func (PlatformSpecific) KeywordCheck(line string) bool { + for _, keyword := range []string{ + "GPP_", "GPD", + } { + if strings.Contains(line, keyword) { + return true + } + } + return false +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44457 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I86296697ee892af7aa0818fb608b6d68fad2f307 Gerrit-Change-Number: 44457 Gerrit-PatchSet: 1 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: mb/purism/librem_whl: Add new board Librem Mini (WHL-U)
by Patrick Georgi (Code Review) 18 Aug '20

18 Aug '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40278 ) Change subject: mb/purism/librem_whl: Add new board Librem Mini (WHL-U) ...................................................................... mb/purism/librem_whl: Add new board Librem Mini (WHL-U) Add new librem_whl baseboard and Librem Mini variant. Tested with SeaBIOS, Tianocore, and Heads payloads. All functions working normally except SATA, which is limited via a FSP UPD to 3Gbps until the correct HSIO PHY settings can be determined. https://puri.sm/products/librem-mini/ Signed-off-by: Matt DeVillier <matt.devillier(a)puri.sm> Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40278 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- A src/mainboard/purism/librem_whl/Kconfig A src/mainboard/purism/librem_whl/Kconfig.name A src/mainboard/purism/librem_whl/Makefile.inc A src/mainboard/purism/librem_whl/acpi/mainboard.asl A src/mainboard/purism/librem_whl/board_info.txt A src/mainboard/purism/librem_whl/devicetree.cb A src/mainboard/purism/librem_whl/dsdt.asl A src/mainboard/purism/librem_whl/ramstage.c A src/mainboard/purism/librem_whl/romstage.c A src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt A src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c A src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c A src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h 13 files changed, 780 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Duncan Laurie: Looks good to me, approved Angel Pons: Looks good to me, approved diff --git a/src/mainboard/purism/librem_whl/Kconfig b/src/mainboard/purism/librem_whl/Kconfig new file mode 100644 index 0000000..bc25fb5 --- /dev/null +++ b/src/mainboard/purism/librem_whl/Kconfig @@ -0,0 +1,62 @@ +config BOARD_PURISM_BASEBOARD_LIBREM_WHL + def_bool n + select BOARD_ROMSIZE_KB_16384 + select DRIVERS_GENERIC_CBFS_SERIAL + select DRIVERS_USB_ACPI + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select NO_UART_ON_SUPERIO + select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_WHISKEYLAKE + select SPD_READ_BY_WORD + select USE_LEGACY_8254_TIMER + +if BOARD_PURISM_BASEBOARD_LIBREM_WHL + +config MAINBOARD_DIR + string + default "purism/librem_whl" + +config MAINBOARD_FAMILY + string + default "Librem Mini" if BOARD_PURISM_LIBREM_MINI + +config MAINBOARD_PART_NUMBER + string + default "Librem Mini" if BOARD_PURISM_LIBREM_MINI + +config VARIANT_DIR + string + default "librem_mini" if BOARD_PURISM_LIBREM_MINI + +config CBFS_SIZE + hex + default 0x800000 + +config MAX_CPUS + int + default 8 + +config DIMM_MAX + int + default 2 + +config DIMM_SPD_SIZE + int + default 512 + +config VGA_BIOS_ID + string + default "8086,3ea0" + +config PXE_ROM_ID + string + default "10ec,8168" + +# This platform has limited means to display POST codes +config NO_POST + default y + +endif diff --git a/src/mainboard/purism/librem_whl/Kconfig.name b/src/mainboard/purism/librem_whl/Kconfig.name new file mode 100644 index 0000000..41a4003 --- /dev/null +++ b/src/mainboard/purism/librem_whl/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_PURISM_LIBREM_MINI + bool "Librem Mini" + select BOARD_PURISM_BASEBOARD_LIBREM_WHL diff --git a/src/mainboard/purism/librem_whl/Makefile.inc b/src/mainboard/purism/librem_whl/Makefile.inc new file mode 100644 index 0000000..ba157df --- /dev/null +++ b/src/mainboard/purism/librem_whl/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += ramstage.c + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/purism/librem_whl/acpi/mainboard.asl b/src/mainboard/purism/librem_whl/acpi/mainboard.asl new file mode 100644 index 0000000..0c9a76b --- /dev/null +++ b/src/mainboard/purism/librem_whl/acpi/mainboard.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.LPCB) +{ + Device (AC) + { + Name (_HID, "ACPI0003") + Name (_PCL, Package () { LPCB }) + Name (ACFG, One) + + Method (_PSR, 0, NotSerialized) + { + Return (ACFG) + } + } +} diff --git a/src/mainboard/purism/librem_whl/board_info.txt b/src/mainboard/purism/librem_whl/board_info.txt new file mode 100644 index 0000000..e72dcdf2 --- /dev/null +++ b/src/mainboard/purism/librem_whl/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Purism +Board name: librem_whl +Category: desktop +Release year: 2020 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/purism/librem_whl/devicetree.cb b/src/mainboard/purism/librem_whl/devicetree.cb new file mode 100644 index 0000000..c122bb8 --- /dev/null +++ b/src/mainboard/purism/librem_whl/devicetree.cb @@ -0,0 +1,317 @@ +chip soc/intel/cannonlake + # Lock Down + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + }" + + # Send an extra VR mailbox command for the PS4 exit issue + register "SendVrMbxCmd" = "2" + +# ACPI (soc/intel/cannonlake/acpi.c) + # Disable s0ix + register "s0ix_enable" = "0" + + # PM Timer Enabled + register "PmTimerDisabled" = "0" + + # Disable DPTF + register "dptf_enable" = "0" + +# CPU (soc/intel/cannonlake/cpu.c) + # Power limit + register "power_limits_config" = "{ + .tdp_pl1_override = 25, + .tdp_pl2_override = 28, + }" + + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + +# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c) + register "SaGv" = "SaGv_Enabled" + +# FSP Silicon (soc/intel/cannonlake/fsp_params.c) + # Serial I/O + register "SerialIoDevMode" = "{ + [PchSerialIoIndexI2C0] = PchSerialIoDisabled, + [PchSerialIoIndexI2C1] = PchSerialIoDisabled, + [PchSerialIoIndexI2C2] = PchSerialIoDisabled, + [PchSerialIoIndexI2C3] = PchSerialIoDisabled, + [PchSerialIoIndexI2C4] = PchSerialIoDisabled, + [PchSerialIoIndexI2C5] = PchSerialIoDisabled, + [PchSerialIoIndexSPI0] = PchSerialIoDisabled, + [PchSerialIoIndexSPI1] = PchSerialIoDisabled, + [PchSerialIoIndexSPI2] = PchSerialIoDisabled, + [PchSerialIoIndexUART0] = PchSerialIoDisabled, + [PchSerialIoIndexUART1] = PchSerialIoDisabled, + [PchSerialIoIndexUART2] = PchSerialIoDisabled, + }" + + # SATA + register "SataMode" = "Sata_AHCI" + register "SataSalpSupport" = "0" + register "SataPortsEnable[0]" = "1" # 2.5" + register "SataPortsEnable[2]" = "1" # m.2 + register "SataPortsDevSlp[0]" = "0" + register "SataPortsDevSlp[2]" = "0" + + # Audio + register "PchHdaDspEnable" = "0" + register "PchHdaAudioLinkHda" = "1" + register "PchHdaAudioLinkDmic0" = "0" + register "PchHdaAudioLinkDmic1" = "0" + register "PchHdaAudioLinkSsp0" = "0" + register "PchHdaAudioLinkSsp1" = "0" + register "PchHdaAudioLinkSsp2" = "0" + register "PchHdaAudioLinkSndw1" = "0" + register "PchHdaAudioLinkSndw2" = "0" + register "PchHdaAudioLinkSndw3" = "0" + register "PchHdaAudioLinkSndw4" = "0" + + # USB + register "SsicPortEnable" = "0" + + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left upper + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front left lower + register "usb2_ports[2]" = "USB2_PORT_MID(OC2)" # Type-A rear upper + register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right lower + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Type-A front right upper + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC3)" # Type-C rear + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # m.2-2230/Bluetooth + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[8]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[9]" = "USB2_PORT_MID(OC2)" # Type-A rear lower + register "usb2_ports[10]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[11]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[12]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[13]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[14]" = "USB2_PORT_EMPTY" # NC + register "usb2_ports[15]" = "USB2_PORT_EMPTY" # NC + + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left upper + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A front left lower + register "usb3_ports[2]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC3)" # Type-C rear + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper + register "usb3_ports[6]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[7]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[8]" = "USB3_PORT_EMPTY" # NC + register "usb3_ports[9]" = "USB3_PORT_EMPTY" # NC + + # All SRCCLKREQ pins mapped directly + register "PcieClkSrcClkReq[0]" = "0" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieClkSrcClkReq[2]" = "2" + register "PcieClkSrcClkReq[3]" = "3" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieClkSrcClkReq[5]" = "5" + + # Set all SRCCLKREQ pins as free-use + register "PcieClkSrcUsage[0]" = "0x80" + register "PcieClkSrcUsage[1]" = "0x80" + register "PcieClkSrcUsage[2]" = "0x80" + register "PcieClkSrcUsage[3]" = "0x80" + register "PcieClkSrcUsage[4]" = "0x80" + register "PcieClkSrcUsage[5]" = "0x80" + + # PCI Express Root Port #8 x1, Clock 2 (WLAN) + register "PcieRpEnable[7]" = "1" + register "PcieRpLtrEnable[7]" = "1" + + # PCI Express Root Port #10 x1, Clock 3 (LAN) + register "PcieRpEnable[9]" = "1" + register "PcieRpLtrEnable[9]" = "0" + + # PCI Express Root port #13 x4, Clock 1 (NVMe) + register "PcieRpEnable[12]" = "1" + register "PcieRpLtrEnable[12]" = "1" + + # Misc + register "AcousticNoiseMitigation" = "1" + register "satapwroptimize" = "1" + + # Power + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "2" # 500ms + register "PchPmSlpAMinAssert" = "4" # 2s + + # Thermal + register "tcc_offset" = "12" + + # Serial IRQ Mode + register "serirq_mode" = "SERIRQ_CONTINUOUS" + +# PMC (soc/intel/cannonlake/pmc.c) + # Disable deep Sx states + register "deep_sx_config" = "0" + +# PM Util (soc/intel/cannonlake/pmutil.c) + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route. i.e. If this route changes then the affected GPE + # offset bits also need to be changed. + # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG) + register "gpe0_dw0" = "PMC_GPP_C" + register "gpe0_dw1" = "PMC_GPP_D" + register "gpe0_dw2" = "PMC_GPP_E" + +# Actual device tree + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 on # SA Thermal device + register "Device4Enable" = "1" + end + device pci 12.0 on end # Thermal Subsystem + device pci 13.0 off end # Integrated Sensor Hub + device pci 14.0 on # USB xHCI + chip drivers/usb/acpi + device usb 0.0 on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left Upper"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 2.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Left Lower"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 2.1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Upper"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 2.2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right Lower"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 2)" + device usb 2.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Front Right Upper"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(0, 3)" + device usb 2.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 2.5 on end + end + chip drivers/usb/acpi + device usb 2.6 off end + end + chip drivers/usb/acpi + device usb 2.7 off end + end + chip drivers/usb/acpi + device usb 2.8 off end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Rear Lower"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 2.9 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left Upper"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 0)" + device usb 3.0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Front Left Lower"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(0, 1)" + device usb 3.1 on end + end + chip drivers/usb/acpi + device usb 3.2 off end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Rear"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device usb 3.3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Lower"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device usb 3.4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Rear Upper"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 0)" + device usb 3.5 on end + end + end + end + end + device pci 14.1 off end # USB xDCI (OTG) + device pci 15.0 off end # I2C #0 + device pci 15.1 off end # I2C #1 + device pci 15.2 off end # I2C #2 + device pci 15.3 off end # I2C #3 + device pci 16.0 off # Management Engine Interface 1 + # HECI must be enabled w/HAP disable else S3 issues + register "HeciEnabled" = "1" + end + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT Redirection + device pci 16.4 off # Management Engine Interface 3 + register "Heci3Enabled" = "0" + end + device pci 16.5 off end # Management Engine Interface 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C #4 + device pci 19.1 off end # I2C #5 + device pci 19.2 off end # UART #2 + device pci 1a.0 off end # eMMC + device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.1 off end # PCI Express Port 2 + device pci 1c.2 off end # PCI Express Port 3 + device pci 1c.3 off end # PCI Express Port 4 + device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.5 off end # PCI Express Port 6 + device pci 1c.6 off end # PCI Express Port 7 + device pci 1c.7 on end # PCI Express Port 8 (WLAN) + device pci 1d.0 off end # PCI Express Port 9 + device pci 1d.1 on end # PCI Express Port 10 (LAN) + device pci 1d.2 off end # PCI Express Port 11 + device pci 1d.3 off end # PCI Express Port 12 + device pci 1d.4 on end # PCI Express Port 13 (NVMe) + device pci 1d.5 off end # PCI Express Port 14 + device pci 1d.6 off end # PCI Express Port 15 + device pci 1d.7 off end # PCI Express Port 16 + device pci 1e.0 off end # UART #0 + device pci 1e.1 off end # UART #1 + device pci 1e.2 off end # GSPI #0 + device pci 1e.3 off end # GSPI #1 + device pci 1f.0 on end # LPC Bridge + device pci 1f.1 off end # P2SB + device pci 1f.2 off end # Power Management Controller + device pci 1f.3 on end # Intel HDA + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.6 off end # GbE + end +end diff --git a/src/mainboard/purism/librem_whl/dsdt.asl b/src/mainboard/purism/librem_whl/dsdt.asl new file mode 100644 index 0000000..296be17 --- /dev/null +++ b/src/mainboard/purism/librem_whl/dsdt.asl @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <acpi/acpi.h> +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 and up */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 /* OEM revision */ +) +{ + #include <soc/intel/cannonlake/acpi/platform.asl> + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + #include <cpu/intel/common/acpi/cpu.asl> + + Device (\_SB.PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/cannonlake/acpi/southbridge.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/purism/librem_whl/ramstage.c b/src/mainboard/purism/librem_whl/ramstage.c new file mode 100644 index 0000000..07ede66 --- /dev/null +++ b/src/mainboard/purism/librem_whl/ramstage.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/ramstage.h> +#include <variant/gpio.h> + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + /* Configure pads prior to SiliconInit() in case there's any + * dependencies during hardware initialization. */ + size_t num_gpios; + const struct pad_config *gpio_table = variant_gpio_table(&num_gpios); + cnl_configure_pads(gpio_table, num_gpios); + + /* Limit SATA speed to 3Gbps until correct HSIO PHY settings determined */ + params->SataSpeedLimit = 2; +} diff --git a/src/mainboard/purism/librem_whl/romstage.c b/src/mainboard/purism/librem_whl/romstage.c new file mode 100644 index 0000000..9f8d600 --- /dev/null +++ b/src/mainboard/purism/librem_whl/romstage.c @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/cnl_memcfg_init.h> +#include <soc/romstage.h> + +static const struct cnl_mb_cfg memcfg = { + + /* Parameters required to access SPD for CH0D0/CH0D1/CH1D0/CH1D1. */ + .spd[0] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa0}, + }, + .spd[1] = {.read_type = NOT_EXISTING}, + .spd[2] = { + .read_type = READ_SMBUS, + .spd_spec = {.spd_smbus_address = 0xa4}, + }, + .spd[3] = {.read_type = NOT_EXISTING}, + + /* + * Rcomp resistor values. These values represent the resistance in + * ohms of the three rcomp resistors attached to the DDR_COMP_0, + * DDR_COMP_1, and DDR_COMP_2 pins on the DRAM. + */ + .rcomp_resistor = { 121, 81, 100 }, + + /* Rcomp target values */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* + * Indicates whether memory is interleaved. + * Set to 1 for an interleaved design, + * set to 0 for non-interleaved design. + */ + .dq_pins_interleaved = 1, + + /* + * VREF_CA configuration. + * Set to 0 VREF_CA goes to both CH_A and CH_B, + * set to 1 VREF_CA goes to CH_A and VREF_DQ_A goes to CH_B, + * set to 2 VREF_CA goes to CH_A and VREF_DQ_B goes to CH_B. + */ + .vref_ca_config = 2, + + /* Early Command Training */ + .ect = 0, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); +} diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt b/src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt new file mode 100644 index 0000000..2e657d1 --- /dev/null +++ b/src/mainboard/purism/librem_whl/variants/librem_mini/data.vbt Binary files differ diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c b/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c new file mode 100644 index 0000000..492d978 --- /dev/null +++ b/src/mainboard/purism/librem_whl/variants/librem_mini/gpio.c @@ -0,0 +1,229 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <variant/gpio.h> + +/* Pad configuration in ramstage. */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Group GPP_A ------- */ + + _PAD_CFG_STRUCT(GPP_A0, 0x44000702, 0x0000), /* RCIN# */ + _PAD_CFG_STRUCT(GPP_A1, 0x44000702, 0x3c00), /* LAD0 */ + _PAD_CFG_STRUCT(GPP_A2, 0x44000702, 0x3c00), /* LAD1 */ + _PAD_CFG_STRUCT(GPP_A3, 0x44000702, 0x3c00), /* LAD2 */ + _PAD_CFG_STRUCT(GPP_A4, 0x44000702, 0x3c00), /* LAD3 */ + _PAD_CFG_STRUCT(GPP_A5, 0x44000700, 0x0000), /* LFRAME# */ + _PAD_CFG_STRUCT(GPP_A6, 0x44000700, 0x0000), /* SERIRQ */ + _PAD_CFG_STRUCT(GPP_A7, 0x84000200, 0x0000), /* PIRQA# */ + _PAD_CFG_STRUCT(GPP_A8, 0x44000700, 0x0000), /* CLKRUN# */ + _PAD_CFG_STRUCT(GPP_A9, 0x44000700, 0x1000), /* CLKOUT_LPC0 */ + _PAD_CFG_STRUCT(GPP_A10, 0x44000700, 0x1000), /* CLKOUT_LPC1 */ + _PAD_CFG_STRUCT(GPP_A11, 0x40880201, 0x0000), /* PME# */ + _PAD_CFG_STRUCT(GPP_A12, 0x84000201, 0x0000), /* BM_BUSY# */ + _PAD_CFG_STRUCT(GPP_A13, 0x84000201, 0x0000), /* SUSWARN#/SUSPWRDNACK*/ + _PAD_CFG_STRUCT(GPP_A14, 0x44000700, 0x0000), /* SUS_STAT# */ + _PAD_CFG_STRUCT(GPP_A15, 0x84000201, 0x0000), /* SUSACK# */ + _PAD_CFG_STRUCT(GPP_A16, 0x84000200, 0x3000), /* SD_1P8_SEL */ + _PAD_CFG_STRUCT(GPP_A17, 0x84000201, 0x0000), /* SD_VDD1_PWR_EN# */ + _PAD_CFG_STRUCT(GPP_A18, 0x44000300, 0x3000), /* ISH_GP0 */ + _PAD_CFG_STRUCT(GPP_A19, 0x44000300, 0x3000), /* ISH_GP1 */ + _PAD_CFG_STRUCT(GPP_A20, 0x44000300, 0x3000), /* ISH_GP2 */ + _PAD_CFG_STRUCT(GPP_A21, 0x44000300, 0x3000), /* ISH_GP3 */ + _PAD_CFG_STRUCT(GPP_A22, 0x44000300, 0x3000), /* ISH_GP4 */ + _PAD_CFG_STRUCT(GPP_A23, 0x44000300, 0x3000), /* ISH_GP5 */ + + /* ------- GPIO Group GPP_B ------- */ + + _PAD_CFG_STRUCT(GPP_B0, 0x84000700, 0x0000), /* Reserved */ + _PAD_CFG_STRUCT(GPP_B1, 0x84000700, 0x0000), /* Reserved */ + _PAD_CFG_STRUCT(GPP_B2, 0x84000201, 0x0000), /* VRALERT# */ + _PAD_CFG_STRUCT(GPP_B3, 0x84000201, 0x0000), /* CPU_GP2 */ + _PAD_CFG_STRUCT(GPP_B4, 0x84000201, 0x0000), /* CPU_GP3 */ + _PAD_CFG_STRUCT(GPP_B5, 0x44000300, 0x0000), /* SRCCLKREQ0# */ + _PAD_CFG_STRUCT(GPP_B6, 0x44000300, 0x0000), /* SRCCLKREQ1# */ + _PAD_CFG_STRUCT(GPP_B7, 0x44000300, 0x0000), /* SRCCLKREQ2# */ + _PAD_CFG_STRUCT(GPP_B8, 0x44000300, 0x0000), /* SRCCLKREQ3# */ + _PAD_CFG_STRUCT(GPP_B9, 0x44000300, 0x0000), /* SRCCLKREQ4# */ + _PAD_CFG_STRUCT(GPP_B10, 0x44000300, 0x0000), /* SRCCLKREQ5# */ + _PAD_CFG_STRUCT(GPP_B11, 0x84000201, 0x0000), /* EXT_PWR_GATE# */ + _PAD_CFG_STRUCT(GPP_B12, 0x44000700, 0x0000), /* SLP_S0# */ + _PAD_CFG_STRUCT(GPP_B13, 0x44000700, 0x0000), /* PLTRST# */ + _PAD_CFG_STRUCT(GPP_B14, 0x84000201, 0x0000), /* SPKR */ + _PAD_CFG_STRUCT(GPP_B15, 0x80000701, 0x0000), /* GSPI0_CS0# */ + _PAD_CFG_STRUCT(GPP_B16, 0x84000601, 0x0000), /* GSPI0_CLK */ + _PAD_CFG_STRUCT(GPP_B17, 0x44000502, 0x0000), /* GSPI0_MISO */ + _PAD_CFG_STRUCT(GPP_B18, 0x84000601, 0x0000), /* GSPI0_MOSI */ + _PAD_CFG_STRUCT(GPP_B19, 0x84000400, 0x0000), /* GSPI1_CS0# */ + _PAD_CFG_STRUCT(GPP_B20, 0x84000400, 0x0000), /* GSPI1_CLK */ + _PAD_CFG_STRUCT(GPP_B21, 0x84000402, 0x0000), /* GSPI1_MISO */ + _PAD_CFG_STRUCT(GPP_B22, 0x84000400, 0x0000), /* GSPI1_MOSI */ + _PAD_CFG_STRUCT(GPP_B23, 0x44000201, 0x0000), /* SML1ALERT# */ + + /* ------- GPIO Group GPP_G ------- */ + + _PAD_CFG_STRUCT(GPP_G0, 0x84000200, 0x0000), /* SD_CMD */ + _PAD_CFG_STRUCT(GPP_G1, 0x84000300, 0x0000), /* SD_DATA0 */ + _PAD_CFG_STRUCT(GPP_G2, 0x84000300, 0x0000), /* SD_DATA1 */ + _PAD_CFG_STRUCT(GPP_G3, 0x84000300, 0x0000), /* SD_DATA2 */ + _PAD_CFG_STRUCT(GPP_G4, 0x84000300, 0x0000), /* SD_DATA3 */ + _PAD_CFG_STRUCT(GPP_G5, 0x84000300, 0x3000), /* SD3_CD# */ + _PAD_CFG_STRUCT(GPP_G6, 0x84000300, 0x0000), /* SD3_CLK */ + _PAD_CFG_STRUCT(GPP_G7, 0x84000300, 0x1000), /* SD3_WP */ + + /* ------- GPIO Group GPP_D ------- */ + + _PAD_CFG_STRUCT(GPP_D0, 0x44000300, 0x0000), /* SPI1_CS# */ + _PAD_CFG_STRUCT(GPP_D1, 0x44000300, 0x0000), /* SPI1_CLK */ + _PAD_CFG_STRUCT(GPP_D2, 0x44000300, 0x0000), /* SPI1_MISO */ + _PAD_CFG_STRUCT(GPP_D3, 0x44000300, 0x0000), /* SPI1_MOSI */ + _PAD_CFG_STRUCT(GPP_D4, 0x44000300, 0x0000), /* IMGCLKOUT0 */ + _PAD_CFG_STRUCT(GPP_D5, 0x44000700, 0x0000), /* ISH_I2C0_SDA */ + _PAD_CFG_STRUCT(GPP_D6, 0x44000700, 0x0000), /* ISH_I2C0_SCL */ + _PAD_CFG_STRUCT(GPP_D7, 0x84000201, 0x0000), /* ISH_I2C1_SDA */ + _PAD_CFG_STRUCT(GPP_D8, 0x84000200, 0x0000), /* ISH_I2C1_SCL */ + _PAD_CFG_STRUCT(GPP_D9, 0x84000201, 0x0000), /* ISH_SPI_CS# */ + _PAD_CFG_STRUCT(GPP_D10, 0x84000201, 0x0000), /* ISH_SPI_CLK */ + _PAD_CFG_STRUCT(GPP_D11, 0x44000201, 0x3000), /* ISH_SPI_MISO */ + _PAD_CFG_STRUCT(GPP_D12, 0x42100102, 0x3000), /* ISH_SPI_MOSI */ + _PAD_CFG_STRUCT(GPP_D13, 0x44000201, 0x0000), /* ISH_UART0_RXD */ + _PAD_CFG_STRUCT(GPP_D14, 0x84000201, 0x0000), /* ISH_UART0_TXD */ + _PAD_CFG_STRUCT(GPP_D15, 0x84000201, 0x0000), /* ISH_UART0_RTS# */ + _PAD_CFG_STRUCT(GPP_D16, 0x44000200, 0x0000), /* ISH_UART0_CTS# */ + _PAD_CFG_STRUCT(GPP_D17, 0x44000700, 0x0000), /* DMIC_CLK1 */ + _PAD_CFG_STRUCT(GPP_D18, 0x44000700, 0x0000), /* DMIC_DATA1 */ + _PAD_CFG_STRUCT(GPP_D19, 0x44000700, 0x0000), /* DMIC_CLK0 */ + _PAD_CFG_STRUCT(GPP_D20, 0x44000700, 0x0000), /* DMIC_DATA0 */ + _PAD_CFG_STRUCT(GPP_D21, 0x44000300, 0x0000), /* SPI1_IO2 */ + _PAD_CFG_STRUCT(GPP_D22, 0x44000300, 0x0000), /* SPI1_IO3 */ + _PAD_CFG_STRUCT(GPP_D23, 0x44000300, 0x0000), /* I2S_MCLK */ + + /* ------- GPIO Group GPP_F ------- */ + + _PAD_CFG_STRUCT(GPP_F0, 0x84000301, 0x0000), /* CNV_PA_BLANKING */ + _PAD_CFG_STRUCT(GPP_F1, 0x84000200, 0x0000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F2, 0x84000201, 0x3000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F3, 0x84000200, 0x3000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F4, 0x44000700, 0x3000), /* CNV_BRI_DT */ + _PAD_CFG_STRUCT(GPP_F5, 0x44000702, 0x3000), /* CNV_BRI_RSP */ + _PAD_CFG_STRUCT(GPP_F6, 0x44000700, 0x3000), /* CNV_RGI_DT */ + _PAD_CFG_STRUCT(GPP_F7, 0x44000702, 0x3000), /* CNV_RGI_RSP */ + _PAD_CFG_STRUCT(GPP_F8, 0x44000300, 0x0000), /* CNV_MFUART2_RXD */ + _PAD_CFG_STRUCT(GPP_F9, 0x44000300, 0x0000), /* CNV_MFUART2_TXD */ + _PAD_CFG_STRUCT(GPP_F10, 0x84000201, 0x0000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_F11, 0x44000300, 0x0000), /* EMMC_CMD */ + _PAD_CFG_STRUCT(GPP_F12, 0x44000300, 0x0000), /* EMMC_DATA0 */ + _PAD_CFG_STRUCT(GPP_F13, 0x44000300, 0x0000), /* EMMC_DATA1 */ + _PAD_CFG_STRUCT(GPP_F14, 0x44000300, 0x0000), /* EMMC_DATA2 */ + _PAD_CFG_STRUCT(GPP_F15, 0x44000300, 0x0000), /* EMMC_DATA3 */ + _PAD_CFG_STRUCT(GPP_F16, 0x44000300, 0x0000), /* EMMC_DATA4 */ + _PAD_CFG_STRUCT(GPP_F17, 0x44000300, 0x0000), /* EMMC_DATA5 */ + _PAD_CFG_STRUCT(GPP_F18, 0x44000300, 0x0000), /* EMMC_DATA6 */ + _PAD_CFG_STRUCT(GPP_F19, 0x44000300, 0x0000), /* EMMC_DATA7 */ + _PAD_CFG_STRUCT(GPP_F20, 0x44000300, 0x0000), /* EMMC_RCLK */ + _PAD_CFG_STRUCT(GPP_F21, 0x44000300, 0x0000), /* EMMC_CLK */ + _PAD_CFG_STRUCT(GPP_F22, 0x44000300, 0x0000), /* EMMC_RESET# */ + _PAD_CFG_STRUCT(GPP_F23, 0x44000700, 0x1000), /* A4WP_PRESENT */ + + /* ------- GPIO Group GPP_H ------- */ + + _PAD_CFG_STRUCT(GPP_H0, 0x44000300, 0x3000), /* I2S2_SCLK */ + _PAD_CFG_STRUCT(GPP_H1, 0x44000f00, 0x3000), /* CNV_RF_RESET# */ + _PAD_CFG_STRUCT(GPP_H2, 0x84000f00, 0x3000), /* MODEM_CLKREQ */ + _PAD_CFG_STRUCT(GPP_H3, 0x84000300, 0x3000), /* I2S2_RXD */ + _PAD_CFG_STRUCT(GPP_H4, 0x84000300, 0x0000), /* I2C2_SDA */ + _PAD_CFG_STRUCT(GPP_H5, 0x84000300, 0x0000), /* I2C2_SCL */ + _PAD_CFG_STRUCT(GPP_H6, 0x84000702, 0x0000), /* I2C3_SDA */ + _PAD_CFG_STRUCT(GPP_H7, 0x84000702, 0x0000), /* I2C3_SCL */ + _PAD_CFG_STRUCT(GPP_H8, 0x84000702, 0x0000), /* I2C4_SDA */ + _PAD_CFG_STRUCT(GPP_H9, 0x84000702, 0x0000), /* I2C4_SCL */ + _PAD_CFG_STRUCT(GPP_H10, 0x84000603, 0x0000), /* I2C5_SDA */ + _PAD_CFG_STRUCT(GPP_H11, 0x84000603, 0x0000), /* I2C5_SCL */ + _PAD_CFG_STRUCT(GPP_H12, 0x84000201, 0x0000), /* M2_SKT2_CFG0 */ + _PAD_CFG_STRUCT(GPP_H13, 0x84000201, 0x0000), /* M2_SKT2_CFG1 */ + _PAD_CFG_STRUCT(GPP_H14, 0x84000200, 0x0000), /* M2_SKT2_CFG2 */ + _PAD_CFG_STRUCT(GPP_H15, 0x84000201, 0x0000), /* M2_SKT2_CFG3 */ + _PAD_CFG_STRUCT(GPP_H16, 0x84000201, 0x0000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H17, 0x84000201, 0x0000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H18, 0x84000700, 0x0000), /* CPU_C10_GATE# */ + _PAD_CFG_STRUCT(GPP_H19, 0x84000201, 0x0000), /* TIME_SYNC0 */ + _PAD_CFG_STRUCT(GPP_H20, 0x84000300, 0x0000), /* IMGCLKOUT1 */ + _PAD_CFG_STRUCT(GPP_H21, 0x84000200, 0x0000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H22, 0x84000201, 0x0000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_H23, 0x84000200, 0x0000), /* GPIO */ + + /* ------- GPIO Group GPD ------- */ + + _PAD_CFG_STRUCT(GPD0, 0x44000702, 0x0000), /* BATLOW# */ + _PAD_CFG_STRUCT(GPD1, 0x44000702, 0x3c00), /* ACPRESENT */ + _PAD_CFG_STRUCT(GPD2, 0x44000702, 0x3c00), /* LAN_WAKE# */ + _PAD_CFG_STRUCT(GPD3, 0x44000702, 0x3000), /* PRWBTN# */ + _PAD_CFG_STRUCT(GPD4, 0x44000600, 0x0000), /* SLP_S3# */ + _PAD_CFG_STRUCT(GPD5, 0x44000600, 0x0000), /* SLP_S4# */ + _PAD_CFG_STRUCT(GPD6, 0x44000600, 0x0000), /* SLP_A# */ + _PAD_CFG_STRUCT(GPD7, 0x44000200, 0x0000), /* GPIO */ + _PAD_CFG_STRUCT(GPD8, 0x44000700, 0x0000), /* SUSCLK */ + _PAD_CFG_STRUCT(GPD9, 0x44000700, 0x0000), /* SLP_WLAN# */ + _PAD_CFG_STRUCT(GPD10, 0x44000600, 0x0000), /* SLP_S5# */ + _PAD_CFG_STRUCT(GPD11, 0x44000600, 0x0000), /* LANPHYPC */ + + /* ------- GPIO Group GPP_C ------- */ + + _PAD_CFG_STRUCT(GPP_C0, 0x44000702, 0x0000), /* SMBCLK */ + _PAD_CFG_STRUCT(GPP_C1, 0x44000702, 0x0000), /* SMBDATA */ + _PAD_CFG_STRUCT(GPP_C2, 0x44000201, 0x0000), /* SMBALERT# */ + _PAD_CFG_STRUCT(GPP_C3, 0x44000702, 0x0000), /* SML0CLK */ + _PAD_CFG_STRUCT(GPP_C4, 0x44000702, 0x0000), /* SML0DATA */ + _PAD_CFG_STRUCT(GPP_C5, 0x84000201, 0x0000), /* SML0ALERT# */ + _PAD_CFG_STRUCT(GPP_C6, 0x44000300, 0x0000), /* SML1CLK */ + _PAD_CFG_STRUCT(GPP_C7, 0x44000300, 0x0000), /* SML1DATA */ + _PAD_CFG_STRUCT(GPP_C8, 0x84000201, 0x0000), /* UART0_RXD */ + _PAD_CFG_STRUCT(GPP_C9, 0x84000201, 0x0000), /* UART0_TXD */ + _PAD_CFG_STRUCT(GPP_C10, 0x84000200, 0x0000), /* UART0_RTS# */ + _PAD_CFG_STRUCT(GPP_C11, 0x84000201, 0x0000), /* UART0_CTS# */ + _PAD_CFG_STRUCT(GPP_C12, 0x84000603, 0x0000), /* UART1_RXD */ + _PAD_CFG_STRUCT(GPP_C13, 0x84000700, 0x0000), /* UART1_TXD */ + _PAD_CFG_STRUCT(GPP_C14, 0x84000700, 0x0000), /* UART1_RTS# */ + _PAD_CFG_STRUCT(GPP_C15, 0x84000702, 0x0000), /* UART1_CTS# */ + _PAD_CFG_STRUCT(GPP_C16, 0x84000402, 0x0000), /* I2C0_SDA */ + _PAD_CFG_STRUCT(GPP_C17, 0x84000402, 0x0000), /* I2C0_SCL */ + _PAD_CFG_STRUCT(GPP_C18, 0x44000702, 0x0000), /* I2C1_SDA */ + _PAD_CFG_STRUCT(GPP_C19, 0x44000702, 0x0000), /* I2C1_SCL */ + _PAD_CFG_STRUCT(GPP_C20, 0x44000300, 0x0000), /* UART2_RXD */ + _PAD_CFG_STRUCT(GPP_C21, 0x44000300, 0x0000), /* UART2_TXD */ + _PAD_CFG_STRUCT(GPP_C22, 0x84000201, 0x0000), /* UART2_RTS# */ + _PAD_CFG_STRUCT(GPP_C23, 0x40100102, 0x1000), /* UART2_CTS# */ + + /* ------- GPIO Group GPP_E ------- */ + + _PAD_CFG_STRUCT(GPP_E0, 0x84000300, 0x0000), /* SATAXPCIE0 */ + _PAD_CFG_STRUCT(GPP_E1, 0x84000300, 0x0000), /* SATAXPCIE1 */ + _PAD_CFG_STRUCT(GPP_E2, 0x84000502, 0x3000), /* SATAXPCIE2 */ + _PAD_CFG_STRUCT(GPP_E3, 0x82040102, 0x0000), /* CPU_GP0 */ + _PAD_CFG_STRUCT(GPP_E4, 0x84000201, 0x0000), /* SATA_DEVSLP0 */ + _PAD_CFG_STRUCT(GPP_E5, 0x84000300, 0x0000), /* SATA_DEVSLP1 */ + _PAD_CFG_STRUCT(GPP_E6, 0x84000300, 0x0000), /* SATA_DEVSLP2 */ + _PAD_CFG_STRUCT(GPP_E7, 0x82000102, 0x0000), /* CPU_GP1 */ + _PAD_CFG_STRUCT(GPP_E8, 0x84000700, 0x0000), /* SATALED# */ + _PAD_CFG_STRUCT(GPP_E9, 0x44001700, 0x0000), /* USB2_OC0# */ + _PAD_CFG_STRUCT(GPP_E10, 0x44001700, 0x0000), /* USB2_OC1# */ + _PAD_CFG_STRUCT(GPP_E11, 0x44000702, 0x0000), /* USB2_OC2# */ + _PAD_CFG_STRUCT(GPP_E12, 0x44000702, 0x0000), /* USB2_OC3# */ + _PAD_CFG_STRUCT(GPP_E13, 0x84000700, 0x0000), /* DDPB_HPD0 */ + _PAD_CFG_STRUCT(GPP_E14, 0x84000702, 0x0000), /* DDPC_HPD1 */ + _PAD_CFG_STRUCT(GPP_E15, 0x84000201, 0x0000), /* DDPD_HPD2 */ + _PAD_CFG_STRUCT(GPP_E16, 0x80880102, 0x3000), /* GPIO */ + _PAD_CFG_STRUCT(GPP_E17, 0x84000700, 0x0000), /* EDP_HPD */ + _PAD_CFG_STRUCT(GPP_E18, 0x84000702, 0x0000), /* DPPB_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_E19, 0x84000602, 0x0000), /* DPPB_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_E20, 0x84000700, 0x0000), /* DPPC_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_E21, 0x84000602, 0x0000), /* DPPC_CTRLDATA */ + _PAD_CFG_STRUCT(GPP_E22, 0x84000702, 0x0000), /* DPPD_CTRLCLK */ + _PAD_CFG_STRUCT(GPP_E23, 0x84000602, 0x0000), /* DPPD_CTRLDATA */ + +}; + +const struct pad_config *variant_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c b/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c new file mode 100644 index 0000000..c3daf3c --- /dev/null +++ b/src/mainboard/purism/librem_whl/variants/librem_mini/hda_verb.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/azalia_device.h> + +const u32 cim_verb_data[] = { + 0x10ec0269, /* Codec Vendor/Device ID: Realtek ALC293 */ + 0x10ec0000, /* Subsystem ID */ + 11, /* Number of entries */ + + AZALIA_SUBVENDOR(0, 0x10ec0000), + AZALIA_PIN_CFG(0, 0x12, 0x40000000), + AZALIA_PIN_CFG(0, 0x15, 0x01214010), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19130), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40422201), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + 0x8086280b, /* Codec Vendor/Device ID: Intel CannonPoint HDMI */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h b/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h new file mode 100644 index 0000000..9094b04 --- /dev/null +++ b/src/mainboard/purism/librem_whl/variants/librem_mini/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +#include <soc/gpe.h> +#include <soc/gpio.h> + +const struct pad_config *variant_gpio_table(size_t *num); + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/40278 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36af42766f85eb17f86f6ec9b48b87125fb911e6 Gerrit-Change-Number: 40278 Gerrit-PatchSet: 11 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <felixsinger(a)posteo.net> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: xeon_sp/cpx: Enable ACPI P-state support
by Patrick Georgi (Code Review) 18 Aug '20

18 Aug '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44404 ) Change subject: xeon_sp/cpx: Enable ACPI P-state support ...................................................................... xeon_sp/cpx: Enable ACPI P-state support Implement ACPI P-state support to enable driver acpi_cpufreq. This patch leverages code from the Skylake project. Tested=On OCP Delta Lake cat /sys/devices/system/cpu/cpu0/cpufreq/scaling_available_frequencies 1501000 1500000 1400000 1300000 1200000 1100000 1000000 900000 800000 Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc Signed-off-by: Jingle Hsu <jingle_hsu(a)wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44404 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Johnny Lin <Johnny_Lin(a)wiwynn.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/xeon_sp/cpx/Kconfig M src/soc/intel/xeon_sp/cpx/acpi.c M src/soc/intel/xeon_sp/cpx/cpu.c M src/soc/intel/xeon_sp/cpx/include/soc/acpi.h M src/soc/intel/xeon_sp/cpx/include/soc/cpu.h 5 files changed, 142 insertions(+), 5 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved Johnny Lin: Looks good to me, but someone else must approve diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index 0df9847..dcbadf8 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -72,6 +72,10 @@ config SOC_INTEL_COMMON_BLOCK_P2SB def_bool y +config CPU_BCLK_MHZ + int + default 100 + select CACHE_MRC_SETTINGS # CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel diff --git a/src/soc/intel/xeon_sp/cpx/acpi.c b/src/soc/intel/xeon_sp/cpx/acpi.c index 4c73363..1328257 100644 --- a/src/soc/intel/xeon_sp/cpx/acpi.c +++ b/src/soc/intel/xeon_sp/cpx/acpi.c @@ -8,6 +8,7 @@ #include <cbmem.h> #include <cf9_reset.h> #include <console/console.h> +#include <cpu/intel/turbo.h> #include <cpu/x86/smm.h> #include <device/pci.h> #include <intelblocks/acpi.h> @@ -16,6 +17,7 @@ #include <soc/acpi.h> #include <soc/cpu.h> #include <soc/iomap.h> +#include <soc/msr.h> #include <soc/nvs.h> #include <soc/pci_devs.h> #include <soc/pm.h> @@ -231,6 +233,133 @@ return acpi_madt_irq_overrides(current); } +static int calculate_power(int tdp, int p1_ratio, int ratio) +{ + u32 m; + u32 power; + + /* + * M = ((1.1 - ((p1_ratio - ratio) * 0.00625)) / 1.1) ^ 2 + * + * Power = (ratio / p1_ratio) * m * tdp + */ + + m = (110000 - ((p1_ratio - ratio) * 625)) / 11; + m = (m * m) / 1000; + + power = ((ratio * 100000 / p1_ratio) / 100); + power *= (m / 100) * (tdp / 1000); + power /= 1000; + + return (int)power; +} + +static void cpx_generate_p_state_entries(int core, int cores_per_package) +{ + int ratio_min, ratio_max, ratio_turbo, ratio_step; + int coord_type, power_max, power_unit, num_entries; + int ratio, power, clock, clock_max; + msr_t msr; + + /* Determine P-state coordination type from MISC_PWR_MGMT[0] */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + if (msr.lo & MISC_PWR_MGMT_EIST_HW_DIS) + coord_type = SW_ANY; + else + coord_type = HW_ALL; + + /* Get bus ratio limits and calculate clock speeds */ + msr = rdmsr(MSR_PLATFORM_INFO); + ratio_min = (msr.hi >> (40-32)) & 0xff; /* Max Efficiency Ratio */ + + /* Determine if this CPU has configurable TDP */ + if (cpu_config_tdp_levels()) { + /* Set max ratio to nominal TDP ratio */ + msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); + ratio_max = msr.lo & 0xff; + } else { + /* Max Non-Turbo Ratio */ + ratio_max = (msr.lo >> 8) & 0xff; + } + clock_max = ratio_max * CONFIG_CPU_BCLK_MHZ; + + /* Calculate CPU TDP in mW */ + msr = rdmsr(MSR_PKG_POWER_SKU_UNIT); + power_unit = 2 << ((msr.lo & 0xf) - 1); + msr = rdmsr(MSR_PKG_POWER_SKU); + power_max = ((msr.lo & 0x7fff) / power_unit) * 1000; + + /* Write _PCT indicating use of FFixedHW */ + acpigen_write_empty_PCT(); + + /* Write _PPC with no limit on supported P-state */ + acpigen_write_PPC_NVS(); + + /* Write PSD indicating configured coordination type */ + acpigen_write_PSD_package(core, 1, coord_type); + + /* Add P-state entries in _PSS table */ + acpigen_write_name("_PSS"); + + /* Determine ratio points */ + ratio_step = PSS_RATIO_STEP; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + if (num_entries > PSS_MAX_ENTRIES) { + ratio_step += 1; + num_entries = ((ratio_max - ratio_min) / ratio_step) + 1; + } + + /* P[T] is Turbo state if enabled */ + if (get_turbo_state() == TURBO_ENABLED) { + /* _PSS package count including Turbo */ + acpigen_write_package(num_entries + 2); + + msr = rdmsr(MSR_TURBO_RATIO_LIMIT); + ratio_turbo = msr.lo & 0xff; + + /* Add entry for Turbo ratio */ + acpigen_write_PSS_package( + clock_max + 1, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_turbo << 8, /* control */ + ratio_turbo << 8); /* status */ + } else { + /* _PSS package count without Turbo */ + acpigen_write_package(num_entries + 1); + } + + /* First regular entry is max non-turbo ratio */ + acpigen_write_PSS_package( + clock_max, /* MHz */ + power_max, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio_max << 8, /* control */ + ratio_max << 8); /* status */ + + /* Generate the remaining entries */ + for (ratio = ratio_min + ((num_entries - 1) * ratio_step); + ratio >= ratio_min; ratio -= ratio_step) { + + /* Calculate power at this ratio */ + power = calculate_power(power_max, ratio_max, ratio); + clock = ratio * CONFIG_CPU_BCLK_MHZ; + //clock = 1; + acpigen_write_PSS_package( + clock, /* MHz */ + power, /* mW */ + PSS_LATENCY_TRANSITION, /* lat1 */ + PSS_LATENCY_BUSMASTER, /* lat2 */ + ratio << 8, /* control */ + ratio << 8); /* status */ + } + + /* Fix package length */ + acpigen_pop_len(); +} + void generate_cpu_entries(const struct device *device) { int core_id, cpu_id, pcontrol_blk = ACPI_BASE_ADDRESS; @@ -255,7 +384,8 @@ /* NOTE: Intel idle driver doesn't use ACPI C-state tables */ - /* TODO: Soc specific power states generation */ + /* Generate P-state tables */ + cpx_generate_p_state_entries(core_id, threads_per_package); acpigen_pop_len(); } } diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index db9dd4b..6737bf0 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -132,7 +132,7 @@ wrmsr(IA32_PERF_CTL, perf_ctl); printk(BIOS_DEBUG, "cpu: frequency set to %d\n", - ((perf_ctl.lo >> 8) & 0xff) * CPU_BCLK); + ((perf_ctl.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ); FUNC_EXIT(); } diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h b/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h index 2f923d4..6a76ef2 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/acpi.h @@ -11,6 +11,12 @@ uint8_t buf[32]; } MEM_BLK; +/* P-state configuration */ +#define PSS_MAX_ENTRIES 16 +#define PSS_RATIO_STEP 1 +#define PSS_LATENCY_TRANSITION 10 +#define PSS_LATENCY_BUSMASTER 10 + unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h index 3e74064..19f6e4c 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/cpu.h @@ -9,9 +9,6 @@ #define CPUID_COOPERLAKE_SP_A0 0x05065a #define CPUID_COOPERLAKE_SP_A1 0x05065b -/* CPU bus clock is fixed at 100MHz */ -#define CPU_BCLK 100 - void cpx_init_cpus(struct device *dev); msr_t read_msr_ppin(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/44404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc Gerrit-Change-Number: 44404 Gerrit-PatchSet: 8 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jasperlake: Disable IPU based on devicetree
by Maulik V Vaghela (Code Review) 18 Aug '20

18 Aug '20

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44270 ) Change subject: soc/intel/jasperlake: Disable IPU based on devicetree ...................................................................... soc/intel/jasperlake: Disable IPU based on devicetree FSP enables IPU by default even if its disabled in devicetree. We need to fill FSP upd based on the device enablement in devicetree. BUG=None BRANCH=None TEST=IPU is disabled and doesn't show in lspci. Change-Id: I0f9a40e85427fd88bb12a40770ecf7b939b1d8cd Signed-off-by: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> --- M src/soc/intel/jasperlake/romstage/fsp_params.c 1 file changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/44270/1 diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 809ae80..9207a82 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -66,10 +66,16 @@ m_cfg->CpuTraceHubMode = config->TraceHubMode; } + /* IPU configuration */ + /* By default IPU is enabled, need to disable in FSP if pci device is disabled */ + dev = pcidev_path_on_root(SA_DEVFN_IPU); + if (!is_dev_enabled(dev)) { + m_cfg->SaIpuEnable = 0; + } + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - /* Enable SMBus controller based on config */ m_cfg->SmbusEnable = config->SmbusEnable; -- To view, visit https://review.coreboot.org/c/coreboot/+/44270 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f9a40e85427fd88bb12a40770ecf7b939b1d8cd Gerrit-Change-Number: 44270 Gerrit-PatchSet: 1 Gerrit-Owner: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/boot: Jump to payload in protected mode
by Arthur Heymans (Code Review) 18 Aug '20

18 Aug '20

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30118 ) Change subject: arch/x86/boot: Jump to payload in protected mode ...................................................................... Patch Set 33: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/30118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Gerrit-Change-Number: 30118 Gerrit-PatchSet: 33 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 18 Aug 2020 08:41:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback
by Caveh Jalali (Code Review) 18 Aug '20

18 Aug '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/44430/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44430/3//COMMIT_MSG@7 PS3, Line 7: cse_lite: Move global reset after MRC writeback. > Please remove the dot/period at the end of the commit message summary. Done https://review.coreboot.org/c/coreboot/+/44430/3//COMMIT_MSG@10 PS3, Line 10: on the initial power-on boot > after SPI flash update? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 18 Aug 2020 07:44:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Comment-In-Reply-To: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback
by Caveh Jalali (Code Review) 18 Aug '20

18 Aug '20

Hello V Sowmya, Shelley Chen, Shaunak Saha, build bot (Jenkins), Jamie Ryu, Furquan Shaikh, Rizwan Qureshi, Tim Wawrzynczak, Sridhar Siricilla, Nick Vaccaro, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44430 to look at the new patch set (#4). Change subject: cse_lite: Move global reset after MRC writeback ...................................................................... cse_lite: Move global reset after MRC writeback With CSE-lite enabled, we were going through the lengthy memory training procedure twice on the first power-on boot or after full BIOS SPI flash update. This moves the global reset performed to achieve the CSE-lite RO to RW reboot to a later boot phase so that it happens after the memory training data has been written to the MRC cache. Now, the 2nd (and subsequent) reboot can utilize the memory training data established during the 1st boot. This reduces the first boot time by about 20s on a 16GB system. Looking at the timing stats form cbmem, the normal boot penalty is about 300ms - mostly attributed to running FspSiliconInit a 2nd time. We will get this time back when the mrc_cache refactoring effort lands (cb:44196, et. al). BUG=b:162021048 TEST=Booted on volteer, confirmed 20s faster boot time. Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 5 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/44430/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/google/volteer: Add configuration table for terrador
by David Wu (Code Review) 18 Aug '20

18 Aug '20

David Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43439 ) Change subject: mb/google/volteer: Add configuration table for terrador ...................................................................... mb/google/volteer: Add configuration table for terrador Terrador is TGL-Y platform and uses audio MAX98373_ALC5682I, however GPIO settings are different from volteer(TGL-U), so needs to add configuration table for terrador. BUG=b:160704699,b:151978872 TEST=Test that GPIOs are configured as expected based on the current value of the fw_config field in cbi. Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Change-Id: Id22e50e3da3e2dc4ee4d01a4f71d8f651a0dcb32 --- M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/variants/baseboard/devicetree.cb 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/43439/1 diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 61e20f4..1982718 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -57,6 +57,17 @@ PAD_NC(GPP_R7, NONE), }; +static const struct pad_config tgl_y_i2s_enable_pads[] = { + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S0_SCLK */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S0_SFRM */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S0_TXD */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S0_RXD */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF2), /* I2S2_SCLK */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), /* I2S2_RXD */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), /* I2S2_TXD */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF2), /* I2S2_SFRM */ +}; + static void fw_config_handle(void *unused) { if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) { @@ -78,5 +89,11 @@ gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); } + if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682I_I2S_TGL_Y))) { + printk(BIOS_INFO, "Configure GPIOs for TGL-Y I2S audio.\n"); + gpio_configure_pads(tgl_y_i2s_enable_pads, ARRAY_SIZE(tgl_y_i2s_enable_pads)); + gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads)); + gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads)); + } } BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 322389d..c639c1b 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -13,6 +13,7 @@ option MAX98357_ALC5682I_I2S 1 option MAX98373_ALC5682I_I2S 2 option MAX98373_ALC5682_SNDW 3 + option MAX98373_ALC5682I_I2S_TGL_Y 4 end field TABLETMODE 11 option TABLETMODE_DISABLED 0 -- To view, visit https://review.coreboot.org/c/coreboot/+/43439 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id22e50e3da3e2dc4ee4d01a4f71d8f651a0dcb32 Gerrit-Change-Number: 43439 Gerrit-PatchSet: 1 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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