coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

1 participants
2457 discussions

Change in coreboot[master]: elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE
by Aaron Durbin (Code Review) 18 Aug '20

18 Aug '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44527 ) Change subject: elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE ...................................................................... elog: rename ELOG_WAKE_SOURCE_GPIO to ELOG_WAKE_SOURCE_GPE The wake source macro for GPE events was using 'GPIO'. However, current usage is really all GPEs. Therefore, provide clarity in the naming in order to allow for proper GPIO wake events that are separate from the ACPI GPE block. BUG=b:159947207 Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- M src/include/elog.h M src/soc/amd/common/block/acpi/acpi.c M src/soc/intel/apollolake/elog.c M src/soc/intel/baytrail/elog.c M src/soc/intel/braswell/elog.c M src/soc/intel/broadwell/elog.c M src/soc/intel/cannonlake/elog.c M src/soc/intel/icelake/elog.c M src/soc/intel/jasperlake/elog.c M src/soc/intel/skylake/elog.c M src/soc/intel/tigerlake/elog.c M src/southbridge/intel/bd82x6x/elog.c M src/southbridge/intel/lynxpoint/elog.c 13 files changed, 16 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/44527/1 diff --git a/src/include/elog.h b/src/include/elog.h index 6c2c531..89079de 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -79,7 +79,7 @@ #define ELOG_WAKE_SOURCE_PME 0x01 #define ELOG_WAKE_SOURCE_PME_INTERNAL 0x02 #define ELOG_WAKE_SOURCE_RTC 0x03 -#define ELOG_WAKE_SOURCE_GPIO 0x04 +#define ELOG_WAKE_SOURCE_GPE 0x04 #define ELOG_WAKE_SOURCE_SMBUS 0x05 #define ELOG_WAKE_SOURCE_PWRBTN 0x06 #define ELOG_WAKE_SOURCE_PME_HDA 0x07 diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 2d75ec0..4ca6599 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -90,7 +90,7 @@ for (i = 0; i <= 31; i++) { if (valid_gpe & (1U << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); } } diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index 408017f..3e82c32 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -18,7 +18,7 @@ for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } diff --git a/src/soc/intel/baytrail/elog.c b/src/soc/intel/baytrail/elog.c index 75c080d..7e92e90 100644 --- a/src/soc/intel/baytrail/elog.c +++ b/src/soc/intel/baytrail/elog.c @@ -68,7 +68,7 @@ i = 0; while (gpio_mask) { if (gpio_mask & gpe0_sts) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); gpio_mask <<= 1; i++; } diff --git a/src/soc/intel/braswell/elog.c b/src/soc/intel/braswell/elog.c index 75c080d..7e92e90 100644 --- a/src/soc/intel/braswell/elog.c +++ b/src/soc/intel/braswell/elog.c @@ -68,7 +68,7 @@ i = 0; while (gpio_mask) { if (gpio_mask & gpe0_sts) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); gpio_mask <<= 1; i++; } diff --git a/src/soc/intel/broadwell/elog.c b/src/soc/intel/broadwell/elog.c index f918958..9271e27 100644 --- a/src/soc/intel/broadwell/elog.c +++ b/src/soc/intel/broadwell/elog.c @@ -16,7 +16,7 @@ for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } @@ -48,7 +48,7 @@ /* GPIO27 */ if (ps->gpe0_sts[GPE_STD] & GP27_STS) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, 27); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, 27); /* Log GPIO events in set 1-3 */ pch_log_gpio_gpe(ps->gpe0_sts[GPE_31_0], ps->gpe0_en[GPE_31_0], 0); diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 9fa725e..3600d76 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -97,7 +97,7 @@ for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } diff --git a/src/soc/intel/icelake/elog.c b/src/soc/intel/icelake/elog.c index 4727fbf..235dc6e 100644 --- a/src/soc/intel/icelake/elog.c +++ b/src/soc/intel/icelake/elog.c @@ -16,7 +16,7 @@ for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } diff --git a/src/soc/intel/jasperlake/elog.c b/src/soc/intel/jasperlake/elog.c index 4727fbf..235dc6e 100644 --- a/src/soc/intel/jasperlake/elog.c +++ b/src/soc/intel/jasperlake/elog.c @@ -16,7 +16,7 @@ for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } diff --git a/src/soc/intel/skylake/elog.c b/src/soc/intel/skylake/elog.c index 550ee41..dee93d8 100644 --- a/src/soc/intel/skylake/elog.c +++ b/src/soc/intel/skylake/elog.c @@ -22,7 +22,7 @@ for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } diff --git a/src/soc/intel/tigerlake/elog.c b/src/soc/intel/tigerlake/elog.c index b38d316..84f0a7e 100644 --- a/src/soc/intel/tigerlake/elog.c +++ b/src/soc/intel/tigerlake/elog.c @@ -16,7 +16,7 @@ for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } diff --git a/src/southbridge/intel/bd82x6x/elog.c b/src/southbridge/intel/bd82x6x/elog.c index c130958..684f830 100644 --- a/src/southbridge/intel/bd82x6x/elog.c +++ b/src/southbridge/intel/bd82x6x/elog.c @@ -87,7 +87,7 @@ /* GPIO 0-15 */ for (i = 0; i < 16; i++) { if ((gpe0_sts & (1 << (16+i))) && (gpe0_en & (1 << (16+i)))) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); } /* SMBUS Wake */ diff --git a/src/southbridge/intel/lynxpoint/elog.c b/src/southbridge/intel/lynxpoint/elog.c index 2e4df72..8146794 100644 --- a/src/southbridge/intel/lynxpoint/elog.c +++ b/src/southbridge/intel/lynxpoint/elog.c @@ -36,7 +36,7 @@ for (i = 0; i <= 31; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i + start); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i + start); } } @@ -64,7 +64,7 @@ gpe0_sts = inw(pmbase + GPE0_STS + 2) & gpe0_en; for (i = 0; i <= 15; i++) { if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, i); + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, i); } /* @@ -78,7 +78,7 @@ if (!gpe0_high_gpios[i]) continue; if (gpe0_sts & (1 << i)) - elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, + elog_add_event_wake(ELOG_WAKE_SOURCE_GPE, gpe0_high_gpios[i]); } } -- To view, visit https://review.coreboot.org/c/coreboot/+/44527 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27d0ab439c58b1658ed39158eddb1213c24d328f Gerrit-Change-Number: 44527 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: xeon_sp/cpx: Enable ACPI P-state support
by HAOUAS Elyes (Code Review) 18 Aug '20

18 Aug '20

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44404 ) Change subject: xeon_sp/cpx: Enable ACPI P-state support ...................................................................... Patch Set 8: (1 comment) https://review.coreboot.org/c/coreboot/+/44404/8/src/soc/intel/xeon_sp/cpx/… File src/soc/intel/xeon_sp/cpx/Kconfig: https://review.coreboot.org/c/coreboot/+/44404/8/src/soc/intel/xeon_sp/cpx/… PS8, Line 75: config CPU_BCLK_MHZ : int : default 100 : : select CACHE_MRC_SETTINGS that gives: src/soc/intel/xeon_sp/cpx/Kconfig:79:warning: config symbol 'CPU_BCLK_MHZ' uses select, but is not boolean or tristate -- To view, visit https://review.coreboot.org/c/coreboot/+/44404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc Gerrit-Change-Number: 44404 Gerrit-PatchSet: 8 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 18 Aug 2020 15:44:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: mb/google/dedede: Map PMC_GPE_DW to PMC_GPP values
by Meera Ravindranath (Code Review) 18 Aug '20

18 Aug '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43949 ) Change subject: mb/google/dedede: Map PMC_GPE_DW to PMC_GPP values ...................................................................... mb/google/dedede: Map PMC_GPE_DW to PMC_GPP values PMC_GPE_DW values should be mapped to PMC_GPP values because of which S3 wake from Trackpad is not functional. Change-Id: I58ce3720e0fdeefb2c9440bb3006897ef80211ea Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/43949/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 7502489..e36d843 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -16,9 +16,9 @@ # - GPP_D0 - WWAN_HOST_WAKE # - GPP_D3 - WLAN_PCIE_WAKE_ODL # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3. - register "pmc_gpe0_dw0" = "GPP_B" - register "pmc_gpe0_dw1" = "GPP_C" - register "pmc_gpe0_dw2" = "GPP_D" + register "pmc_gpe0_dw0" = "PMC_GPP_B" + register "pmc_gpe0_dw1" = "PMC_GPP_C" + register "pmc_gpe0_dw2" = "PMC_GPP_D" # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f register "gen1_dec" = "0x00fc0801" -- To view, visit https://review.coreboot.org/c/coreboot/+/43949 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I58ce3720e0fdeefb2c9440bb3006897ef80211ea Gerrit-Change-Number: 43949 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

5 15

Change in coreboot[master]: soc/intel/jasperlake: Fix PMC_GPE_DW mapping
by Meera Ravindranath (Code Review) 18 Aug '20

18 Aug '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43673 ) Change subject: soc/intel/jasperlake: Fix PMC_GPE_DW mapping ...................................................................... soc/intel/jasperlake: Fix PMC_GPE_DW mapping PMC_GPE_DW mapping was not configured correctly and hence coreboot skipped programming Tier 1 GPIOs resulting in failure of S3 wake from Trackpad. TEST=System should wake from S3 via trackpad Change-Id: I59ce3720e0ffeefb2c9440bb300689def80211ea Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/jasperlake/gpio.c M src/soc/intel/jasperlake/include/soc/pmc.h 2 files changed, 11 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/43673/1 diff --git a/src/soc/intel/jasperlake/gpio.c b/src/soc/intel/jasperlake/gpio.c index 3b3b262..397d668 100644 --- a/src/soc/intel/jasperlake/gpio.c +++ b/src/soc/intel/jasperlake/gpio.c @@ -189,7 +189,8 @@ { PMC_GPD, GPP_GPD }, { PMC_GPP_C, GPP_C }, { PMC_GPP_E, GPP_E }, - { PMC_GPP_F, GPP_F } + { PMC_GPP_F, GPP_F }, + { PMC_GPP_G, GPP_G } }; *num = ARRAY_SIZE(routes); diff --git a/src/soc/intel/jasperlake/include/soc/pmc.h b/src/soc/intel/jasperlake/include/soc/pmc.h index 5954a31..9eaa812 100644 --- a/src/soc/intel/jasperlake/include/soc/pmc.h +++ b/src/soc/intel/jasperlake/include/soc/pmc.h @@ -102,16 +102,17 @@ #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4*(x)) -#define PMC_GPP_A 0x0 +#define PMC_GPP_G 0x0 #define PMC_GPP_B 0x1 -#define PMC_GPP_F 0x2 -#define PMC_GPD 0x3 -#define PMC_GPP_R 0x4 -#define PMC_GPP_S 0x6 +#define PMC_GPP_A 0x2 +#define PMC_GPP_R 0x3 +#define PMC_GPP_S 0x4 +#define PMC_GPD 0x5 +#define PMC_GPP_H 0x6 #define PMC_GPP_D 0x7 -#define PMC_GPP_C 0x8 -#define PMC_GPP_H 0xA -#define PMC_GPP_E 0xF +#define PMC_GPP_F 0x8 +#define PMC_GPP_C 0xA +#define PMC_GPP_E 0xB #define GBLRST_CAUSE0 0x1924 #define GBLRST_CAUSE0_THERMTRIP (1 << 5) -- To view, visit https://review.coreboot.org/c/coreboot/+/43673 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I59ce3720e0ffeefb2c9440bb300689def80211ea Gerrit-Change-Number: 43673 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

5 14

Change in coreboot[master]: soc/intel/jasperlake: Increase PRERAM_CBMEM_CONSOLE_SIZE
by Meera Ravindranath (Code Review) 18 Aug '20

18 Aug '20

Meera Ravindranath has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44326 ) Change subject: soc/intel/jasperlake: Increase PRERAM_CBMEM_CONSOLE_SIZE ...................................................................... soc/intel/jasperlake: Increase PRERAM_CBMEM_CONSOLE_SIZE Increase the cbmem console size in order to fix console overflow. Change-Id: Id7eb64feb91ec29df5402b2fb1bac3ff73cc5bb3 Signed-off-by: Meera Ravindranath <meera.ravindranath(a)intel.com> --- M src/soc/intel/jasperlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/44326/1 diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index f2922f5..7321425 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -209,5 +209,5 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex - default 0xe00 + default 0x1400 endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44326 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id7eb64feb91ec29df5402b2fb1bac3ff73cc5bb3 Gerrit-Change-Number: 44326 Gerrit-PatchSet: 1 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-MessageType: newchange

7 9

Change in coreboot[master]: UDK2017/IntelFsp2Pkg: Add FSP*_ARCH_UPD.
by Angel Pons (Code Review) 18 Aug '20

18 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44414 ) Change subject: UDK2017/IntelFsp2Pkg: Add FSP*_ARCH_UPD. ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/44414/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44414/7//COMMIT_MSG@7 PS7, Line 7: UDK2017/IntelFsp2Pkg: Add FSP*_ARCH_UPD. Does the Jasper Lake FSP use UDK2017 bindings? CB:42239 added edk2-stable202005 headers -- To view, visit https://review.coreboot.org/c/coreboot/+/44414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21b0a72eae49976a0e36b4ac69c2efec8aaffabc Gerrit-Change-Number: 44414 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 18 Aug 2020 13:51:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

1 0

Change in coreboot[master]: crossgcc: Upgrade LLVM to version 10.0.0
by HAOUAS Elyes (Code Review) 18 Aug '20

18 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39921 ) Change subject: crossgcc: Upgrade LLVM to version 10.0.0 ...................................................................... crossgcc: Upgrade LLVM to version 10.0.0 Change-Id: I1d96654fd66a5972c6c5cc24311ca2d889866331 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cfe-9.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-10.0.0.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-10.0.0.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-9.0.0.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-10.0.0.src.tar.xz.cksum D util/crossgcc/sum/compiler-rt-9.0.0.src.tar.xz.cksum A util/crossgcc/sum/llvm-10.0.0.src.tar.xz.cksum D util/crossgcc/sum/llvm-9.0.0.src.tar.xz.cksum 9 files changed, 9 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/39921/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 16151c0..3e14b9e 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -58,7 +58,7 @@ PYTHON_VERSION=3.8.2 EXPAT_VERSION=2.2.9 # CLANG version number -CLANG_VERSION=9.0.0 +CLANG_VERSION=10.0.0 MAKE_VERSION=4.3 CMAKE_VERSION=3.17.0 MAKE_VERSION=4.2.1 @@ -78,10 +78,10 @@ PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION…" EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.…" # CLANG toolchain archive locations -LLVM_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz" -CFE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src.tar.xz" -CRT_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src…" -CTE_ARCHIVE="https://releases.llvm.org/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSIO…" +LLVM_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" +CFE_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" +CRT_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" +CTE_ARCHIVE="https://github.com/llvm/llvm-project/releases/download/llvmorg-${CLANG_VERS…" MAKE_ARCHIVE="https://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.gz" CMAKE_ARCHIVE="https://cmake.org/files/v3.17/cmake-${CMAKE_VERSION}.tar.gz" NASM_ARCHIVE="https://www.nasm.us/pub/nasm/releasebuilds/${NASM_VERSION}/nasm-${NASM_VERS…" diff --git a/util/crossgcc/sum/cfe-9.0.0.src.tar.xz.cksum b/util/crossgcc/sum/cfe-9.0.0.src.tar.xz.cksum deleted file mode 100644 index e39bea1..0000000 --- a/util/crossgcc/sum/cfe-9.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -6977cf7a802a053c57fa74138d3648b563e71e88 tarballs/cfe-9.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-10.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-10.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..4d19617 --- /dev/null +++ b/util/crossgcc/sum/clang-10.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +cfaa4c4e89a45b604e6f3057f984d73365074727 tarballs/clang-10.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-10.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-10.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..0277d6a --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-10.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +e41467d4e8c6afe917c9f9c44b1d6a95a85adadb tarballs/clang-tools-extra-10.0.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-9.0.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-9.0.0.src.tar.xz.cksum deleted file mode 100644 index 47eba2c..0000000 --- a/util/crossgcc/sum/clang-tools-extra-9.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -ac64403321d8486699d8bea5376b2438663dbb41 tarballs/clang-tools-extra-9.0.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-10.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-10.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..0a41da1 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-10.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +4744490da9c1186ba7f730d8a8f4fa4b0d4ee0bc tarballs/compiler-rt-10.0.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-9.0.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-9.0.0.src.tar.xz.cksum deleted file mode 100644 index 15f1a61..0000000 --- a/util/crossgcc/sum/compiler-rt-9.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -4e00cb231ff87fd4f970f35b2da86185a612e0e2 tarballs/compiler-rt-9.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-10.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-10.0.0.src.tar.xz.cksum new file mode 100644 index 0000000..46fe8f4 --- /dev/null +++ b/util/crossgcc/sum/llvm-10.0.0.src.tar.xz.cksum @@ -0,0 +1 @@ +85f2d89205fb190c61c8a98dad2a58e27a1540da tarballs/llvm-10.0.0.src.tar.xz diff --git a/util/crossgcc/sum/llvm-9.0.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-9.0.0.src.tar.xz.cksum deleted file mode 100644 index 4fb1c2d..0000000 --- a/util/crossgcc/sum/llvm-9.0.0.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -7ef2527ba3da7603a41ce3592a8cd890f8d27ffa tarballs/llvm-9.0.0.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/39921 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1d96654fd66a5972c6c5cc24311ca2d889866331 Gerrit-Change-Number: 39921 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 12

Change in coreboot[master]: Documentation: Discuss how we use language
by Angel Pons (Code Review) 18 Aug '20

18 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43420 ) Change subject: Documentation: Discuss how we use language ...................................................................... Patch Set 2: Code-Review+1 +2, but I'd like to hear other people's opinions on this topic. -- To view, visit https://review.coreboot.org/c/coreboot/+/43420 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I44fa30af538c78760821401c8d3c52029d95b72b Gerrit-Change-Number: 43420 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 18 Aug 2020 13:43:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: crossgcc: Upgrade cmake to version 3.16.4
by Dhyey Patel (Code Review) 18 Aug '20

18 Aug '20

Dhyey Patel has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39258 ) Change subject: crossgcc: Upgrade cmake to version 3.16.4 ...................................................................... crossgcc: Upgrade cmake to version 3.16.4 Change-Id: I20b75b7c29be838c3c168547bcab25ea5c1af462 Signed-off-by: Griffin98 <griffin98(a)protonmail.com> --- M util/crossgcc/buildgcc D util/crossgcc/sum/cmake-3.16.2.tar.gz.cksum A util/crossgcc/sum/cmake-3.16.4.tar.gz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/39258/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 9920799..f1d7e66 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -60,7 +60,7 @@ # CLANG version number CLANG_VERSION=9.0.0 MAKE_VERSION=4.2.1 -CMAKE_VERSION=3.16.2 +CMAKE_VERSION=3.16.4 NASM_VERSION=2.14.02 # GCC toolchain archive locations diff --git a/util/crossgcc/sum/cmake-3.16.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.16.2.tar.gz.cksum deleted file mode 100644 index c5190b2..0000000 --- a/util/crossgcc/sum/cmake-3.16.2.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -f514dbd9aa8332a28ba62dd8ce97b0aa0b099491 tarballs/cmake-3.16.2.tar.gz diff --git a/util/crossgcc/sum/cmake-3.16.4.tar.gz.cksum b/util/crossgcc/sum/cmake-3.16.4.tar.gz.cksum new file mode 100644 index 0000000..95df652 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.16.4.tar.gz.cksum @@ -0,0 +1 @@ +3ae23da521d5c0e871dd820a0d3af5504f0bd6db tarballs/cmake-3.16.4.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/39258 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20b75b7c29be838c3c168547bcab25ea5c1af462 Gerrit-Change-Number: 39258 Gerrit-PatchSet: 1 Gerrit-Owner: Dhyey Patel Gerrit-MessageType: newchange

4 24

Change in coreboot[master]: src: Remove unused 'include <delay.h>'
by HAOUAS Elyes (Code Review) 18 Aug '20

18 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44093 ) Change subject: src: Remove unused 'include <delay.h>' ...................................................................... src: Remove unused 'include <delay.h>' Change-Id: I6afea5c102299e570378a1656d3dcd329a373399 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/drivers/crb/tpm.c M src/mainboard/getac/p470/early_init.c M src/mainboard/google/hatch/variants/nightfury/ramstage.c M src/mainboard/lenovo/t440p/smihandler.c M src/mainboard/supermicro/x11-lga1151-series/bootblock.c M src/northbridge/intel/ironlake/northbridge.c M src/soc/amd/picasso/psp_verstage/fch.c M src/soc/amd/picasso/southbridge.c M src/soc/intel/common/block/imc/imc.c M src/soc/mediatek/mt8173/i2c.c M src/soc/mediatek/mt8183/spm.c M src/soc/qualcomm/sc7180/gpio.c M src/soc/qualcomm/sc7180/qupv3_spi.c M src/soc/qualcomm/sc7180/usb.c M src/superio/aspeed/common/early_config.c 15 files changed, 0 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/44093/1 diff --git a/src/drivers/crb/tpm.c b/src/drivers/crb/tpm.c index 6436725..575f973 100644 --- a/src/drivers/crb/tpm.c +++ b/src/drivers/crb/tpm.c @@ -14,7 +14,6 @@ #include <timer.h> #include <console/console.h> -#include <delay.h> #include <device/mmio.h> #include <string.h> #include <soc/pci_devs.h> diff --git a/src/mainboard/getac/p470/early_init.c b/src/mainboard/getac/p470/early_init.c index 8550f69..087e279 100644 --- a/src/mainboard/getac/p470/early_init.c +++ b/src/mainboard/getac/p470/early_init.c @@ -3,7 +3,6 @@ #include <bootblock_common.h> #include <stdint.h> #include <arch/io.h> -#include <delay.h> #include <device/pnp_ops.h> #include <device/pci_ops.h> #include <option.h> diff --git a/src/mainboard/google/hatch/variants/nightfury/ramstage.c b/src/mainboard/google/hatch/variants/nightfury/ramstage.c index d5a57af..0e6eae6 100644 --- a/src/mainboard/google/hatch/variants/nightfury/ramstage.c +++ b/src/mainboard/google/hatch/variants/nightfury/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <delay.h> #include <gpio.h> #include <baseboard/variants.h> #include <soc/gpio.h> diff --git a/src/mainboard/lenovo/t440p/smihandler.c b/src/mainboard/lenovo/t440p/smihandler.c index e3da85d..8cc5135 100644 --- a/src/mainboard/lenovo/t440p/smihandler.c +++ b/src/mainboard/lenovo/t440p/smihandler.c @@ -5,7 +5,6 @@ #include <cpu/x86/smm.h> #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> -#include <delay.h> #include <southbridge/intel/lynxpoint/pch.h> #define GPE_EC_SCI 1 diff --git a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c index 94eeee7..3e5751c 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c +++ b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c @@ -5,7 +5,6 @@ #include <variant/gpio.h> #include <superio/aspeed/common/aspeed.h> #include <superio/aspeed/ast2400/ast2400.h> -#include <delay.h> #include <console/uart.h> static void early_config_gpio(void) diff --git a/src/northbridge/intel/ironlake/northbridge.c b/src/northbridge/intel/ironlake/northbridge.c index c1a2840..d70460f 100644 --- a/src/northbridge/intel/ironlake/northbridge.c +++ b/src/northbridge/intel/ironlake/northbridge.c @@ -4,7 +4,6 @@ #include <acpi/acpi.h> #include <device/pci_ops.h> #include <stdint.h> -#include <delay.h> #include <cpu/intel/model_2065x/model_2065x.h> #include <device/device.h> #include <device/pci.h> diff --git a/src/soc/amd/picasso/psp_verstage/fch.c b/src/soc/amd/picasso/psp_verstage/fch.c index 5096088..499f4e2 100644 --- a/src/soc/amd/picasso/psp_verstage/fch.c +++ b/src/soc/amd/picasso/psp_verstage/fch.c @@ -11,7 +11,6 @@ #include <bl_uapp/bl_errorcodes_public.h> #include <bl_uapp/bl_syscall_public.h> #include <console/console.h> -#include <delay.h> #include <soc/i2c.h> #include <soc/southbridge.h> #include <stdint.h> diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index 4cd24dd..6305e8e 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -24,7 +24,6 @@ #include <soc/smi.h> #include <soc/uart.h> #include <soc/amd_pci_int_defs.h> -#include <delay.h> #include <soc/pci_devs.h> #include <soc/nvs.h> #include <types.h> diff --git a/src/soc/intel/common/block/imc/imc.c b/src/soc/intel/common/block/imc/imc.c index 8c49dcd..57c7fa8 100644 --- a/src/soc/intel/common/block/imc/imc.c +++ b/src/soc/intel/common/block/imc/imc.c @@ -6,7 +6,6 @@ */ #include <console/console.h> -#include <delay.h> #include <device/pci_ops.h> #include <intelblocks/imc.h> #include <soc/pci_devs.h> diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index f80fb97..ff803c3 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -2,7 +2,6 @@ #include <assert.h> #include <console/console.h> -#include <delay.h> #include <device/i2c_simple.h> #include <device/mmio.h> #include <soc/addressmap.h> diff --git a/src/soc/mediatek/mt8183/spm.c b/src/soc/mediatek/mt8183/spm.c index 2aa10b4..01c6a2f 100644 --- a/src/soc/mediatek/mt8183/spm.c +++ b/src/soc/mediatek/mt8183/spm.c @@ -3,7 +3,6 @@ #include <assert.h> #include <cbfs.h> #include <console/console.h> -#include <delay.h> #include <device/mmio.h> #include <endian.h> #include <soc/emi.h> diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c index 51d9135..f175ce5 100644 --- a/src/soc/qualcomm/sc7180/gpio.c +++ b/src/soc/qualcomm/sc7180/gpio.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <delay.h> #include <device/mmio.h> #include <timestamp.h> #include <types.h> diff --git a/src/soc/qualcomm/sc7180/qupv3_spi.c b/src/soc/qualcomm/sc7180/qupv3_spi.c index a145417..d086a27 100644 --- a/src/soc/qualcomm/sc7180/qupv3_spi.c +++ b/src/soc/qualcomm/sc7180/qupv3_spi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <assert.h> -#include <delay.h> #include <lib.h> #include <soc/clock.h> #include <soc/gpio.h> diff --git a/src/soc/qualcomm/sc7180/usb.c b/src/soc/qualcomm/sc7180/usb.c index c4b65d6..41032b7 100644 --- a/src/soc/qualcomm/sc7180/usb.c +++ b/src/soc/qualcomm/sc7180/usb.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> -#include <delay.h> #include <device/mmio.h> #include <soc/usb.h> #include <soc/clock.h> diff --git a/src/superio/aspeed/common/early_config.c b/src/superio/aspeed/common/early_config.c index fe780ff..b0aab89 100644 --- a/src/superio/aspeed/common/early_config.c +++ b/src/superio/aspeed/common/early_config.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <arch/io.h> -#include <delay.h> #include <device/pnp_def.h> #include <device/pnp_ops.h> #include <stdint.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/44093 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6afea5c102299e570378a1656d3dcd329a373399 Gerrit-Change-Number: 44093 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

3 5

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2020