coreboot-gerrit August 2020

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Change in coreboot[master]: mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur
by V Sowmya (Code Review) 19 Aug '20

19 Aug '20

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44559 ) Change subject: mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f Gerrit-Change-Number: 44559 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Aug 2020 08:32:31 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths
by V Sowmya (Code Review) 19 Aug '20

19 Aug '20

V Sowmya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44557 ) Change subject: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f Gerrit-Change-Number: 44557 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Aug 2020 08:31:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur
by Sridhar Siricilla (Code Review) 19 Aug '20

19 Aug '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44559 ) Change subject: mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f Gerrit-Change-Number: 44559 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Aug 2020 07:50:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths
by Sridhar Siricilla (Code Review) 19 Aug '20

19 Aug '20

Sridhar Siricilla has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44557 ) Change subject: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f Gerrit-Change-Number: 44557 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Aug 2020 07:49:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/prodrive/hermes: Enable LPSS ACPI driver
by Patrick Rudolph (Code Review) 19 Aug '20

19 Aug '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44411 ) Change subject: mb/prodrive/hermes: Enable LPSS ACPI driver ...................................................................... mb/prodrive/hermes: Enable LPSS ACPI driver Enable the introduced LPSS ACPI uart driver. Tested on Hermes using Linux 5.6: The UART2 appears as /dev/ttyS2. Change-Id: Ic15be4a807012216e52c848120de7e39522f57b7 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/44411/1 diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb index d1694dc..c3d148d 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb +++ b/src/mainboard/prodrive/hermes/variants/baseboard/overridetree.cb @@ -176,8 +176,11 @@ # This device does not have any function on CNP-H, but it needs # to be here so that the resource allocator is aware of UART 2. device pci 19.0 hidden end - device pci 19.2 hidden end # UART #2, in ACPI mode - + chip soc/intel/common/block/uart + device pci 19.2 hidden + register "devid" = "PCI_DEVICE_ID_INTEL_CNP_H_UART2" + end # UART #2, in ACPI mode + end device pci 1b.4 on smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthOther" "SLOT1" "SlotDataBusWidth4X" end # PCIe Slot 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44411 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic15be4a807012216e52c848120de7e39522f57b7 Gerrit-Change-Number: 44411 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths
by Jamie Ryu (Code Review) 19 Aug '20

19 Aug '20

Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44557 ) Change subject: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths ...................................................................... Patch Set 1: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/44557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f Gerrit-Change-Number: 44557 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Aug 2020 07:28:14 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur
by Jamie Ryu (Code Review) 19 Aug '20

19 Aug '20

Jamie Ryu has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44559 ) Change subject: mb/google/volteer: Update SLP_Sx assertion widths and PwrCycDur ...................................................................... Patch Set 2: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/44559 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idf4e0c3a60b4ac59e31df1357f2ff28f195ff17f Gerrit-Change-Number: 44559 Gerrit-PatchSet: 2 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Aug 2020 07:27:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/ti/am335x: Move from cpu to soc in tree
by Sam Lewis (Code Review) 19 Aug '20

19 Aug '20

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44378 ) Change subject: cpu/ti/am335x: Move from cpu to soc in tree ...................................................................... cpu/ti/am335x: Move from cpu to soc in tree The AM335X is a SoC, so should be in the soc tree. This moves all the existing am335x code to soc/ and updates any references. It also adds a soc.c file as required for the ramstage. Change-Id: Ic1ccb0e9b9c24a8b211b723b5f4cc26cdd0eaaab Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- M MAINTAINERS D src/cpu/ti/Kconfig D src/cpu/ti/Makefile.inc M src/mainboard/ti/beaglebone/Kconfig M src/mainboard/ti/beaglebone/bootblock.c M src/mainboard/ti/beaglebone/devicetree.cb M src/mainboard/ti/beaglebone/leds.c A src/soc/ti/Kconfig A src/soc/ti/Makefile.inc R src/soc/ti/am335x/Kconfig R src/soc/ti/am335x/Makefile.inc R src/soc/ti/am335x/bootblock.c R src/soc/ti/am335x/bootblock_media.c R src/soc/ti/am335x/cbmem.c R src/soc/ti/am335x/clock.h R src/soc/ti/am335x/dmtimer.c R src/soc/ti/am335x/dmtimer.h R src/soc/ti/am335x/gpio.c R src/soc/ti/am335x/gpio.h R src/soc/ti/am335x/header.c R src/soc/ti/am335x/header.h R src/soc/ti/am335x/header.ld R src/soc/ti/am335x/memlayout.ld R src/soc/ti/am335x/monotonic_timer.c R src/soc/ti/am335x/nand.c R src/soc/ti/am335x/pinmux.c R src/soc/ti/am335x/pinmux.h A src/soc/ti/am335x/soc.c R src/soc/ti/am335x/uart.c R src/soc/ti/am335x/uart.h 30 files changed, 34 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/44378/1 diff --git a/MAINTAINERS b/MAINTAINERS index 924247e..e91bfc2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -550,7 +550,7 @@ ORPHANED ARM SOCS S: Orphaned F: src/cpu/armltd/ -F: src/cpu/ti/ +F: src/soc/ti/ F: src/soc/qualcomm/ F: src/soc/samsung/ F: util/exynos/ diff --git a/src/cpu/ti/Kconfig b/src/cpu/ti/Kconfig deleted file mode 100644 index 119e84b..0000000 --- a/src/cpu/ti/Kconfig +++ /dev/null @@ -1 +0,0 @@ -source "src/cpu/ti/am335x/Kconfig" diff --git a/src/cpu/ti/Makefile.inc b/src/cpu/ti/Makefile.inc deleted file mode 100644 index 64b22f6..0000000 --- a/src/cpu/ti/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -subdirs-$(CONFIG_CPU_TI_AM335X) += am335x diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone/Kconfig index 7399f22..5be310c 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select CPU_TI_AM335X + select SOC_TI_AM335X select BOARD_ROMSIZE_KB_4096 select MISSING_BOARD_RESET diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone/bootblock.c index 6e9538b..ca1a390 100644 --- a/src/mainboard/ti/beaglebone/bootblock.c +++ b/src/mainboard/ti/beaglebone/bootblock.c @@ -3,9 +3,9 @@ #include <device/mmio.h> #include <bootblock_common.h> #include <console/uart.h> -#include <cpu/ti/am335x/clock.h> -#include <cpu/ti/am335x/gpio.h> -#include <cpu/ti/am335x/pinmux.h> +#include <soc/ti/am335x/clock.h> +#include <soc/ti/am335x/gpio.h> +#include <soc/ti/am335x/pinmux.h> #include "leds.h" diff --git a/src/mainboard/ti/beaglebone/devicetree.cb b/src/mainboard/ti/beaglebone/devicetree.cb index dd999b4..217a201 100644 --- a/src/mainboard/ti/beaglebone/devicetree.cb +++ b/src/mainboard/ti/beaglebone/devicetree.cb @@ -1,5 +1,5 @@ ## SPDX-License-Identifier: GPL-2.0-only -chip cpu/ti/am335x +chip soc/ti/am335x device cpu_cluster 0 on end end diff --git a/src/mainboard/ti/beaglebone/leds.c b/src/mainboard/ti/beaglebone/leds.c index 99ae6d9..df58fea 100644 --- a/src/mainboard/ti/beaglebone/leds.c +++ b/src/mainboard/ti/beaglebone/leds.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <assert.h> -#include <cpu/ti/am335x/gpio.h> +#include <soc/ti/am335x/gpio.h> #include "leds.h" diff --git a/src/soc/ti/Kconfig b/src/soc/ti/Kconfig new file mode 100644 index 0000000..eb66519 --- /dev/null +++ b/src/soc/ti/Kconfig @@ -0,0 +1 @@ +source "src/soc/ti/am335x/Kconfig" diff --git a/src/soc/ti/Makefile.inc b/src/soc/ti/Makefile.inc new file mode 100644 index 0000000..357cc82 --- /dev/null +++ b/src/soc/ti/Makefile.inc @@ -0,0 +1 @@ +subdirs-$(CONFIG_SOC_TI_AM335X) += am335x diff --git a/src/cpu/ti/am335x/Kconfig b/src/soc/ti/am335x/Kconfig similarity index 76% rename from src/cpu/ti/am335x/Kconfig rename to src/soc/ti/am335x/Kconfig index 3684480..533a0de 100644 --- a/src/cpu/ti/am335x/Kconfig +++ b/src/soc/ti/am335x/Kconfig @@ -1,4 +1,4 @@ -config CPU_TI_AM335X +config SOC_TI_AM335X select ARCH_BOOTBLOCK_ARMV7 select ARCH_VERSTAGE_ARMV7 select ARCH_ROMSTAGE_ARMV7 @@ -9,10 +9,10 @@ bool default n -if CPU_TI_AM335X +if SOC_TI_AM335X config MEMLAYOUT_LD_FILE string - default "src/cpu/ti/am335x/memlayout.ld" + default "src/soc/ti/am335x/memlayout.ld" endif diff --git a/src/cpu/ti/am335x/Makefile.inc b/src/soc/ti/am335x/Makefile.inc similarity index 98% rename from src/cpu/ti/am335x/Makefile.inc rename to src/soc/ti/am335x/Makefile.inc index 6f414bc..dd9e093 100644 --- a/src/cpu/ti/am335x/Makefile.inc +++ b/src/soc/ti/am335x/Makefile.inc @@ -13,6 +13,7 @@ ramstage-y += dmtimer.c ramstage-y += monotonic_timer.c ramstage-y += nand.c +ramstage-y += soc.c bootblock-y += uart.c romstage-y += uart.c diff --git a/src/cpu/ti/am335x/bootblock.c b/src/soc/ti/am335x/bootblock.c similarity index 100% rename from src/cpu/ti/am335x/bootblock.c rename to src/soc/ti/am335x/bootblock.c diff --git a/src/cpu/ti/am335x/bootblock_media.c b/src/soc/ti/am335x/bootblock_media.c similarity index 100% rename from src/cpu/ti/am335x/bootblock_media.c rename to src/soc/ti/am335x/bootblock_media.c diff --git a/src/cpu/ti/am335x/cbmem.c b/src/soc/ti/am335x/cbmem.c similarity index 100% rename from src/cpu/ti/am335x/cbmem.c rename to src/soc/ti/am335x/cbmem.c diff --git a/src/cpu/ti/am335x/clock.h b/src/soc/ti/am335x/clock.h similarity index 98% rename from src/cpu/ti/am335x/clock.h rename to src/soc/ti/am335x/clock.h index aadd3f6..38b4ece 100644 --- a/src/cpu/ti/am335x/clock.h +++ b/src/soc/ti/am335x/clock.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __CPU_TI_AM335X_CLOCK_H__ -#define __CPU_TI_AM335X_CLOCK_H__ +#ifndef __SOC_TI_AM335X_CLOCK_H__ +#define __SOC_TI_AM335X_CLOCK_H__ #include <stdint.h> @@ -219,4 +219,4 @@ static struct am335x_cm_cefuse_regs * const am335x_cm_cefuse = (void *)0x44e00a00; -#endif /* __CPU_TI_AM335X_CLOCK_H__ */ +#endif /* __SOC_TI_AM335X_CLOCK_H__ */ diff --git a/src/cpu/ti/am335x/dmtimer.c b/src/soc/ti/am335x/dmtimer.c similarity index 100% rename from src/cpu/ti/am335x/dmtimer.c rename to src/soc/ti/am335x/dmtimer.c diff --git a/src/cpu/ti/am335x/dmtimer.h b/src/soc/ti/am335x/dmtimer.h similarity index 69% rename from src/cpu/ti/am335x/dmtimer.h rename to src/soc/ti/am335x/dmtimer.h index 7e93a0c..ad8515f 100644 --- a/src/cpu/ti/am335x/dmtimer.h +++ b/src/soc/ti/am335x/dmtimer.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef __CPU_TI_AM335X_DMTIMER_H__ -#define __CPU_TI_AM335X_DMTIMER_H__ +#ifndef __SOC_TI_AM335X_DMTIMER_H__ +#define __SOC_TI_AM335X_DMTIMER_H__ #include <stdint.h> diff --git a/src/cpu/ti/am335x/gpio.c b/src/soc/ti/am335x/gpio.c similarity index 97% rename from src/cpu/ti/am335x/gpio.c rename to src/soc/ti/am335x/gpio.c index de7f740..d3d3581 100644 --- a/src/cpu/ti/am335x/gpio.c +++ b/src/soc/ti/am335x/gpio.c @@ -2,7 +2,7 @@ #include <device/mmio.h> #include <console/console.h> -#include <cpu/ti/am335x/gpio.h> +#include <soc/ti/am335x/gpio.h> #include <stdint.h> static struct am335x_gpio_regs *gpio_regs_and_bit(unsigned int gpio, diff --git a/src/cpu/ti/am335x/gpio.h b/src/soc/ti/am335x/gpio.h similarity index 93% rename from src/cpu/ti/am335x/gpio.h rename to src/soc/ti/am335x/gpio.h index 62ad77a..0877a62 100644 --- a/src/cpu/ti/am335x/gpio.h +++ b/src/soc/ti/am335x/gpio.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __CPU_TI_AM335X_GPIO_H__ -#define __CPU_TI_AM335X_GPIO_H__ +#ifndef __SOC_TI_AM335X_GPIO_H__ +#define __SOC_TI_AM335X_GPIO_H__ #include <stdint.h> @@ -55,4 +55,4 @@ int gpio_get_value(unsigned int gpio); int gpio_set_value(unsigned int gpio, int value); -#endif /* __CPU_TI_AM335X_CLOCK_H__ */ +#endif /* __SOC_TI_AM335X_CLOCK_H__ */ diff --git a/src/cpu/ti/am335x/header.c b/src/soc/ti/am335x/header.c similarity index 100% rename from src/cpu/ti/am335x/header.c rename to src/soc/ti/am335x/header.c diff --git a/src/cpu/ti/am335x/header.h b/src/soc/ti/am335x/header.h similarity index 92% rename from src/cpu/ti/am335x/header.h rename to src/soc/ti/am335x/header.h index 578d213..a0a54ad 100644 --- a/src/cpu/ti/am335x/header.h +++ b/src/soc/ti/am335x/header.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __CPU_TI_AM335X_HEADER_H -#define __CPU_TI_AM335X_HEADER_H +#ifndef __SOC_TI_AM335X_HEADER_H +#define __SOC_TI_AM335X_HEADER_H #include <stdint.h> diff --git a/src/cpu/ti/am335x/header.ld b/src/soc/ti/am335x/header.ld similarity index 100% rename from src/cpu/ti/am335x/header.ld rename to src/soc/ti/am335x/header.ld diff --git a/src/cpu/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld similarity index 100% rename from src/cpu/ti/am335x/memlayout.ld rename to src/soc/ti/am335x/memlayout.ld diff --git a/src/cpu/ti/am335x/monotonic_timer.c b/src/soc/ti/am335x/monotonic_timer.c similarity index 100% rename from src/cpu/ti/am335x/monotonic_timer.c rename to src/soc/ti/am335x/monotonic_timer.c diff --git a/src/cpu/ti/am335x/nand.c b/src/soc/ti/am335x/nand.c similarity index 100% rename from src/cpu/ti/am335x/nand.c rename to src/soc/ti/am335x/nand.c diff --git a/src/cpu/ti/am335x/pinmux.c b/src/soc/ti/am335x/pinmux.c similarity index 100% rename from src/cpu/ti/am335x/pinmux.c rename to src/soc/ti/am335x/pinmux.c diff --git a/src/cpu/ti/am335x/pinmux.h b/src/soc/ti/am335x/pinmux.h similarity index 98% rename from src/cpu/ti/am335x/pinmux.h rename to src/soc/ti/am335x/pinmux.h index 0cb56a6..c46d03d 100644 --- a/src/cpu/ti/am335x/pinmux.h +++ b/src/soc/ti/am335x/pinmux.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#ifndef __CPU_TI_AM335X_PINMUX_H -#define __CPU_TI_AM335X_PINMUX_H +#ifndef __SOC_TI_AM335X_PINMUX_H +#define __SOC_TI_AM335X_PINMUX_H #include <stdint.h> diff --git a/src/soc/ti/am335x/soc.c b/src/soc/ti/am335x/soc.c new file mode 100644 index 0000000..0362ed9 --- /dev/null +++ b/src/soc/ti/am335x/soc.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/device.h> + +struct chip_operations soc_ti_am335x_ops = { + CHIP_NAME("TI AM335X") +}; diff --git a/src/cpu/ti/am335x/uart.c b/src/soc/ti/am335x/uart.c similarity index 99% rename from src/cpu/ti/am335x/uart.c rename to src/soc/ti/am335x/uart.c index a882340..90095d4 100644 --- a/src/cpu/ti/am335x/uart.c +++ b/src/soc/ti/am335x/uart.c @@ -4,7 +4,7 @@ #include <console/uart.h> #include <device/mmio.h> #include <boot/coreboot_tables.h> -#include <cpu/ti/am335x/uart.h> +#include <soc/ti/am335x/uart.h> #define EFR_ENHANCED_EN (1 << 4) #define FCR_FIFO_EN (1 << 0) diff --git a/src/cpu/ti/am335x/uart.h b/src/soc/ti/am335x/uart.h similarity index 100% rename from src/cpu/ti/am335x/uart.h rename to src/soc/ti/am335x/uart.h -- To view, visit https://review.coreboot.org/c/coreboot/+/44378 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic1ccb0e9b9c24a8b211b723b5f4cc26cdd0eaaab Gerrit-Change-Number: 44378 Gerrit-PatchSet: 1 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-MessageType: newchange

3 6

Change in coreboot[master]: arch/arm: Enable FIT payloads
by Sam Lewis (Code Review) 19 Aug '20

19 Aug '20

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44377 ) Change subject: arch/arm: Enable FIT payloads ...................................................................... arch/arm: Enable FIT payloads Implements fit_payload_arch for the arm (aarch32) architecture, so that FIT images can be used. The implementation is very similar to the existing implementations for arm64 and riscv, and has mostly been lifted from these other ports. TEST: Booted Beaglebone Black (in progress port, to be submitted soon!) with a FIT image containing a 5.4 kernel, dtb and initramfs. Change-Id: I6b50c6f06b83c00a5b3622b5bbafe67130b6d233 Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- M Documentation/lib/payloads/fit.md M payloads/Kconfig M src/arch/arm/Makefile.inc A src/arch/arm/fit_payload.c 4 files changed, 120 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/44377/1 diff --git a/Documentation/lib/payloads/fit.md b/Documentation/lib/payloads/fit.md index c6ccc7b..ef5e892 100644 --- a/Documentation/lib/payloads/fit.md +++ b/Documentation/lib/payloads/fit.md @@ -5,6 +5,7 @@ ## Supported architectures +* aarch32 * aarch64 * riscv @@ -26,6 +27,13 @@ The FIT parser needs architecure support. +### aarch32 +The source code can be found in `src/arch/arm/fit_payload.c`. + +On aarch32 the kernel (a section named 'kernel') must be in **Image** +format and it needs a devicetree (a section named 'fdt') to boot. +The kernel will be placed close to "*DRAMSTART*". + ### aarch64 The source code can be found in `src/arch/arm64/fit_payload.c`. diff --git a/payloads/Kconfig b/payloads/Kconfig index cfb28d6..627bb95 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -30,7 +30,7 @@ config PAYLOAD_FIT bool "A FIT payload" - depends on ARCH_ARM64 || ARCH_RISCV + depends on ARCH_ARM64 || ARCH_RISCV || ARCH_ARM select PAYLOAD_FIT_SUPPORT help Select this option if you have a payload image (a FIT file) which @@ -97,7 +97,7 @@ bool "FIT support" default n default y if PAYLOAD_LINUX && (ARCH_ARM || ARCH_ARM64 || ARCH_RISCV) - depends on ARCH_ARM64 || ARCH_RISCV + depends on ARCH_ARM64 || ARCH_RISCV || ARCH_ARM select FLATTENED_DEVICE_TREE help Select this option if your payload is of type FIT. diff --git a/src/arch/arm/Makefile.inc b/src/arch/arm/Makefile.inc index eef2650..241bfe5 100644 --- a/src/arch/arm/Makefile.inc +++ b/src/arch/arm/Makefile.inc @@ -119,6 +119,7 @@ ramstage-y += memcpy.S ramstage-y += memmove.S ramstage-y += clock.c +ramstage-$(CONFIG_PAYLOAD_FIT_SUPPORT) += fit_payload.c rmodules_arm-y += memset.S rmodules_arm-y += memcpy.S diff --git a/src/arch/arm/fit_payload.c b/src/arch/arm/fit_payload.c new file mode 100644 index 0000000..39cb0f2 --- /dev/null +++ b/src/arch/arm/fit_payload.c @@ -0,0 +1,109 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <console/console.h> +#include <bootmem.h> +#include <program_loading.h> +#include <fit.h> + +#define MAX_KERNEL_SIZE (64 * MiB) + +static size_t get_kernel_size(const struct fit_image_node *node) +{ + /* + * Since we don't have a way to determine the uncompressed size of the + * kernel, we have to keep as much memory as possible free for use by + * the kernel immediately after the end of the kernel image. The amount + * of space required will vary depending on selected features, and is + * effectively unbound. + */ + + printk(BIOS_INFO, "FIT: Leaving additional %u MiB of free space after kernel.\n", + MAX_KERNEL_SIZE >> 20); + + return node->size + MAX_KERNEL_SIZE; +} + + +/** + * Place the region in free memory range. + * + * The caller has to set region->offset to the minimum allowed address. + * The region->offset is usually 0 on kernel >v4.6 and kernel_base + kernel_size + * on kernel <v4.6. + */ +static bool fit_place_mem(const struct range_entry *r, void *arg) +{ + struct region *region = arg; + resource_t start; + + if (range_entry_tag(r) != BM_MEM_RAM) + return true; + + /* Linux 4.15 doesn't like 4KiB alignment. Align to 1 MiB for now. */ + start = ALIGN_UP(MAX(region->offset, range_entry_base(r)), 1 * MiB); + + if (start + region->size < range_entry_end(r)) { + region->offset = (size_t)start; + return false; + } + + return true; +} + + +bool fit_payload_arch(struct prog *payload, struct fit_config_node *config, + struct region *kernel, + struct region *fdt, + struct region *initrd) +{ + void *arg = NULL; + + kernel->size = get_kernel_size(config->kernel); + printk(BIOS_DEBUG, "FIT: Reserving 0x%zx bytes for kernel\n", kernel->size); + + /** + * The code assumes that bootmem_walk provides a sorted list of memory + * regions, starting from the lowest address. + * The order of the calls here doesn't matter, as the placement is + * enforced in the called functions. + * For details check code on top. + */ + + kernel->offset = 0; + if (!bootmem_walk(fit_place_mem, kernel)) { + printk(BIOS_DEBUG, "Couldnt find room for kernel\n"); + return false; + } + + /* Mark as reserved for future allocations. */ + bootmem_add_range(kernel->offset, kernel->size, BM_MEM_PAYLOAD); + + /* Place INITRD */ + if (config->ramdisk) { + initrd->offset = kernel->offset + kernel->size; + + if (!bootmem_walk(fit_place_mem, initrd)) + return false; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(initrd->offset, initrd->size, BM_MEM_PAYLOAD); + } + + + fdt->offset = kernel->offset + kernel->size; + + if (!bootmem_walk(fit_place_mem, fdt)) + return false; + + /* Mark as reserved for future allocations. */ + bootmem_add_range(fdt->offset, fdt->size, BM_MEM_PAYLOAD); + + /* Kernel expects FDT as argument */ + arg = (void *)fdt->offset; + + prog_set_entry(payload, (void *)kernel->offset, arg); + + bootmem_dump_ranges(); + + return true; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/44377 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6b50c6f06b83c00a5b3622b5bbafe67130b6d233 Gerrit-Change-Number: 44377 Gerrit-PatchSet: 1 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

4 10

Change in coreboot[master]: mb/google/volteer: Update settings for touchpad
by John Su (Code Review) 19 Aug '20

19 Aug '20

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44524 ) Change subject: mb/google/volteer: Update settings for touchpad ...................................................................... mb/google/volteer: Update settings for touchpad Configure gpio settings for touchpad BUG=b:153680359 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Change-Id: I525ba688f71b7a1893bcb64c77e02c8e2506d7b0 --- M src/mainboard/google/volteer/variants/halvor/gpio.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/44524/1 diff --git a/src/mainboard/google/volteer/variants/halvor/gpio.c b/src/mainboard/google/volteer/variants/halvor/gpio.c index 09e8081..85f956a 100644 --- a/src/mainboard/google/volteer/variants/halvor/gpio.c +++ b/src/mainboard/google/volteer/variants/halvor/gpio.c @@ -44,6 +44,10 @@ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* B8 : ISH_I2C1_SCL ==> I2C_SENSOR_SCL */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* C1 : SMBDATA ==> FPMCU_BOOT1 */ PAD_CFG_GPO(GPP_C1, 0, DEEP), @@ -87,6 +91,8 @@ PAD_NC(GPP_E12, NONE), /* E13 : SPI1_MOSI_IO0 ==> NC */ PAD_NC(GPP_E13, NONE), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), /* E16 : ISH_GP7 ==> SD_PRSNT# */ PAD_CFG_GPI(GPP_E16, NONE, DEEP), /* E17 : THC0_SPI1_INT# ==> NC */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44524 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I525ba688f71b7a1893bcb64c77e02c8e2506d7b0 Gerrit-Change-Number: 44524 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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