coreboot-gerrit August 2020

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Change in coreboot[master]: soc/intel/jasperlake: Disable multiphase SI init
by Ronak Kanabar (Code Review) 19 Aug '20

19 Aug '20

Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Maulik V Vaghela, Subrata Banik, Krishna P Bhat D, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43816 to look at the new patch set (#9). Change subject: soc/intel/jasperlake: Disable multiphase SI init ...................................................................... soc/intel/jasperlake: Disable multiphase SI init Jasper Lake does not have any use case for multiphase SI init so Disable it. BUG=b:162184827 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3221772 Change-Id: I2d591b46c403e68ff0b41ac8f87c742ae774111e Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/jasperlake/fsp_params.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43816/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/43816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d591b46c403e68ff0b41ac8f87c742ae774111e Gerrit-Change-Number: 43816 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: soc/intel/jasperlake: Select PLATFORM_USES_FSP2_2
by Ronak Kanabar (Code Review) 19 Aug '20

19 Aug '20

Hello build bot (Jenkins), Patrick Georgi, Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Krishna P Bhat D, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43815 to look at the new patch set (#7). Change subject: soc/intel/jasperlake: Select PLATFORM_USES_FSP2_2 ...................................................................... soc/intel/jasperlake: Select PLATFORM_USES_FSP2_2 Add support for FSP 2.2 for jasperlake by selecting PLATFORM_USES_FSP2_2 config. BUG=b:162184827 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3221772 Change-Id: Ia606ec26da93242ecdd602a9b3badbece5dcd034 Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/soc/intel/jasperlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/43815/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/43815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia606ec26da93242ecdd602a9b3badbece5dcd034 Gerrit-Change-Number: 43815 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2295
by Ronak Kanabar (Code Review) 19 Aug '20

19 Aug '20

Hello build bot (Jenkins), Furquan Shaikh, Maulik V Vaghela, Subrata Banik, Aamir Bohra, Patrick Rudolph, Karthik Ramasubramanian, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/44415 to look at the new patch set (#6). Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2295 ...................................................................... vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2295 The FSP-M/S headers added are generated as per FSP v2295. BUG=b:162184827 BRANCH=None TEST=Build and boot JSLRVP Cq-Depend: chrome-internal:3221772 Change-Id: I569987427cccefc1c5015bdabb10b41f29f2624a Signed-off-by: Ronak Kanabar <ronak.kanabar(a)intel.com> --- M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspmUpd.h M src/vendorcode/intel/fsp/fsp2_0/jasperlake/FspsUpd.h 2 files changed, 536 insertions(+), 536 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44415/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/44415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I569987427cccefc1c5015bdabb10b41f29f2624a Gerrit-Change-Number: 44415 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/ti/beaglebone: Rename beaglebone to beaglebone-black
by Sam Lewis (Code Review) 19 Aug '20

19 Aug '20

Sam Lewis has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44379 ) Change subject: mb/ti/beaglebone: Rename beaglebone to beaglebone-black ...................................................................... mb/ti/beaglebone: Rename beaglebone to beaglebone-black Retargets the Beaglebone port to be a Beaglebone Black port. The original Beaglebone (sometimes referred to as the Beaglebone White) has been mostly superseded by the Beaglebone Black and is no longer available for purchase. This port currently is unfinished, so it makes sense to retarget it towards available hardware. The original Beaglebone and Beaglebone Black are very similar in any case (biggest material difference is 256MB of RAM in the original vs. 512MB in the Black) so, if there were interest, it probably would not be very difficult to get the port to work on the original Beaglebone. Change-Id: Ied0632badf19c20b37411375f0bce652453aef6e Signed-off-by: Sam Lewis <sam.vr.lewis(a)gmail.com> --- R src/mainboard/ti/beaglebone-black/Kconfig A src/mainboard/ti/beaglebone-black/Kconfig.name R src/mainboard/ti/beaglebone-black/Makefile.inc R src/mainboard/ti/beaglebone-black/board_info.txt R src/mainboard/ti/beaglebone-black/bootblock.c R src/mainboard/ti/beaglebone-black/devicetree.cb R src/mainboard/ti/beaglebone-black/leds.c R src/mainboard/ti/beaglebone-black/leds.h R src/mainboard/ti/beaglebone-black/romstage.c D src/mainboard/ti/beaglebone/Kconfig.name 10 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/44379/1 diff --git a/src/mainboard/ti/beaglebone/Kconfig b/src/mainboard/ti/beaglebone-black/Kconfig similarity index 73% rename from src/mainboard/ti/beaglebone/Kconfig rename to src/mainboard/ti/beaglebone-black/Kconfig index 5be310c..5ff844e 100644 --- a/src/mainboard/ti/beaglebone/Kconfig +++ b/src/mainboard/ti/beaglebone-black/Kconfig @@ -1,6 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only -if BOARD_TI_BEAGLEBONE +if BOARD_TI_BEAGLEBONE_BLACK config BOARD_SPECIFIC_OPTIONS def_bool y @@ -10,11 +10,11 @@ config MAINBOARD_DIR string - default "ti/beaglebone" + default "ti/beaglebone-black" config MAINBOARD_PART_NUMBER string - default "Beaglebone" + default "Beaglebone Black" config MAX_CPUS int @@ -28,4 +28,4 @@ int default 0 -endif # BOARD_TI_BEAGLEBONE +endif # BOARD_TI_BEAGLEBONE_BLACK diff --git a/src/mainboard/ti/beaglebone-black/Kconfig.name b/src/mainboard/ti/beaglebone-black/Kconfig.name new file mode 100644 index 0000000..a7757b5 --- /dev/null +++ b/src/mainboard/ti/beaglebone-black/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_TI_BEAGLEBONE_BLACK + bool "Beaglebone Black" diff --git a/src/mainboard/ti/beaglebone/Makefile.inc b/src/mainboard/ti/beaglebone-black/Makefile.inc similarity index 100% rename from src/mainboard/ti/beaglebone/Makefile.inc rename to src/mainboard/ti/beaglebone-black/Makefile.inc diff --git a/src/mainboard/ti/beaglebone/board_info.txt b/src/mainboard/ti/beaglebone-black/board_info.txt similarity index 100% rename from src/mainboard/ti/beaglebone/board_info.txt rename to src/mainboard/ti/beaglebone-black/board_info.txt diff --git a/src/mainboard/ti/beaglebone/bootblock.c b/src/mainboard/ti/beaglebone-black/bootblock.c similarity index 100% rename from src/mainboard/ti/beaglebone/bootblock.c rename to src/mainboard/ti/beaglebone-black/bootblock.c diff --git a/src/mainboard/ti/beaglebone/devicetree.cb b/src/mainboard/ti/beaglebone-black/devicetree.cb similarity index 100% rename from src/mainboard/ti/beaglebone/devicetree.cb rename to src/mainboard/ti/beaglebone-black/devicetree.cb diff --git a/src/mainboard/ti/beaglebone/leds.c b/src/mainboard/ti/beaglebone-black/leds.c similarity index 100% rename from src/mainboard/ti/beaglebone/leds.c rename to src/mainboard/ti/beaglebone-black/leds.c diff --git a/src/mainboard/ti/beaglebone/leds.h b/src/mainboard/ti/beaglebone-black/leds.h similarity index 100% rename from src/mainboard/ti/beaglebone/leds.h rename to src/mainboard/ti/beaglebone-black/leds.h diff --git a/src/mainboard/ti/beaglebone/romstage.c b/src/mainboard/ti/beaglebone-black/romstage.c similarity index 100% rename from src/mainboard/ti/beaglebone/romstage.c rename to src/mainboard/ti/beaglebone-black/romstage.c diff --git a/src/mainboard/ti/beaglebone/Kconfig.name b/src/mainboard/ti/beaglebone/Kconfig.name deleted file mode 100644 index f03759e..0000000 --- a/src/mainboard/ti/beaglebone/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_TI_BEAGLEBONE - bool "Beaglebone" -- To view, visit https://review.coreboot.org/c/coreboot/+/44379 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied0632badf19c20b37411375f0bce652453aef6e Gerrit-Change-Number: 44379 Gerrit-PatchSet: 1 Gerrit-Owner: Sam Lewis <sam.vr.lewis(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support
by Patrick Rudolph (Code Review) 19 Aug '20

19 Aug '20

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/29667 ) Change subject: mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support ...................................................................... mb/emulation/qemu-q35,qemu-i440fx: Add x86_64 support * Enable optional x86_64 romstage, postcar and ramstage * Add Kconfig for x86_64 compilation * Add documentation for x86 qemu mainboards * Increase CAR stack as x86_64 uses more than 0x4000 bytes Working: * Boots to Linux * Boots to SeaBIOS * Drops to protected mode at end of ramstage * Enumerates PCI devices * Relocateable ramstage * SMM Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/29667 Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M Documentation/arch/x86/index.md A Documentation/mainboard/emulation/qemu-i440fx.md A Documentation/mainboard/emulation/qemu-q35.md M Documentation/mainboard/index.md M src/cpu/qemu-x86/Kconfig 5 files changed, 165 insertions(+), 19 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 7b9e1fc..11d8a4f 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -5,10 +5,11 @@ * [x86 PAE support](pae.md) ## State of x86_64 support -At the moment there's no single board that supports x86_64 or to be exact -`ARCH_RAMSTAGE_X86_64` and `ARCH_ROMSTAGE_X86_64`. +At the moment there's only experimental x86_64 support. +The `emulation/qemu-i440fx` and `emulation/qemu-q35` boards do support +*ARCH_RAMSTAGE_X86_64* , *ARCH_POSTCAR_X86_64* and *ARCH_ROMSTAGE_X86_64*. -In order to add support for x86_64 the following assumptions are made: +In order to add support for x86_64 the following assumptions were made: * The CPU supports long mode * All memory returned by malloc must be below 4GiB in physical memory * All code that is to be run must be below 4GiB in physical memory @@ -39,18 +40,16 @@ At the moment *$n* is 4, which results in identity mapping the lower 4 GiB. -## Steps to add basic support for x86_64 -* Add x86_64 toolchain support - *DONE* -* Fix compilation errors - *DONE* -* Fix linker errors - *TODO* -* Add x86_64 rmodule support - *DONE* -* Add x86_64 exception handlers - *DONE* -* Setup page tables for long mode - *DONE* -* Add assembly code for long mode - *DONE* -* Add assembly code for SMM - *DONE* -* Add assembly code for postcar stage - *DONE* -* Add assembly code to return to protected mode - *DONE* -* Implement reference code for mainboard `emulation/qemu-q35` - *TODO* +## Basic x86_64 support +Basic support for x86_64 has been implemented for QEMU mainboard target. + +## Reference implementation +The reference implementation is +* [QEMU i440fx](../../mainboard/emulation/qemu-i440fx.md) +* [QEMU Q35](../../mainboard/emulation/qemu-q35.md) + +## TODO +* Identity map memory above 4GiB in ramstage ## Future work diff --git a/Documentation/mainboard/emulation/qemu-i440fx.md b/Documentation/mainboard/emulation/qemu-i440fx.md new file mode 100644 index 0000000..059ad12 --- /dev/null +++ b/Documentation/mainboard/emulation/qemu-i440fx.md @@ -0,0 +1,64 @@ +# qemu i440fx mainboard + +## Running coreboot in qemu +Emulators like qemu don't need a firmware to do hardware init. +The hardware starts in the configured state already. + +The coreboot port allows to test non mainboard specific code. +As you can easily attach a debugger, it's a good target for +experimental code. + +## coreboot x86_64 support +coreboot historically runs in 32-bit protected mode, even though the +processor supports x86_64 instructions (long mode). + +The qemu-i440fx mainboard has been ported to x86_64 and will serve as +reference platform to enable additional platforms. + +To enable the support set the Kconfig option ``CONFIG_CPU_QEMU_X86_64=y``. + +## Installing qemu + +On debian you can install qemu by running: +```bash +$ sudo apt-get install qemu +``` + +On redhat you can install qemu by running: +```bash +$ sudo dnf install qemu +``` + +## Running coreboot + +### To run the i386 version of coreboot (default) +Running on qemu-system-i386 will require a 32 bit operating system. + +```bash +qemu-system-i386 -bios build/coreboot.rom -serial stdio -M pc +``` + +### To run the experimental x86_64 version of coreboot +Running on qemu-system-x86_64 allows to run a 32 bit or 64 bit operating system, +as well as firmware. + +```bash +qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -M pc +``` + +## Finding bugs +To test coreboot's x86 code it's recommended to run on a x86 host and enable KVM. +It will not only run faster, but is closer to real hardware. If you see the +following message: + + KVM internal error. Suberror: 1 + emulation failure + +something went wrong. The same bug will likely cause a FAULT on real hardware, +too. + +To enable KVM run: + +```bash +qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -M pc -accel kvm -cpu host +``` diff --git a/Documentation/mainboard/emulation/qemu-q35.md b/Documentation/mainboard/emulation/qemu-q35.md new file mode 100644 index 0000000..00163e8 --- /dev/null +++ b/Documentation/mainboard/emulation/qemu-q35.md @@ -0,0 +1,64 @@ +# qemu q35 mainboard + +## Running coreboot in qemu +Emulators like qemu don't need a firmware to do hardware init. +The hardware starts in the configured state already. + +The coreboot port allows to test non mainboard specific code. +As you can easily attach a debugger, it's a good target for +experimental code. + +## coreboot x86_64 support +coreboot historically runs in 32-bit protected mode, even though the +processor supports x86_64 instructions (long mode). + +The qemu-q35 mainboard has been ported to x86_64 and will serve as +reference platform to enable additional platforms. + +To enable the support set the Kconfig option ``CONFIG_CPU_QEMU_X86_64=y``. + +## Installing qemu + +On debian you can install qemu by running: +```bash +$ sudo apt-get install qemu +``` + +On redhat you can install qemu by running: +```bash +$ sudo dnf install qemu +``` + +## Running coreboot +### To run the i386 version of coreboot (default) +Running on qemu-system-i386 will require a 32 bit operating system. + +```bash +qemu-system-i386 -bios build/coreboot.rom -serial stdio -M q35 +``` + +### To run the experimental x86_64 version of coreboot +Running on `qemu-system-x86_64` allows to run a 32 bit or 64 bit operating system +and firmware. + +```bash +qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -M q35 +``` + +## Finding bugs +To test coreboot's x86 code it's recommended to run on a x86 host and enable KVM. +It will not only run faster, but is closer to real hardware. If you see the +following message: + + KVM internal error. Suberror: 1 + emulation failure + +something went wrong. The same bug will likely cause a FAULT on real hardware, +too. + +To enable KVM run: + +```bash +qemu-system-x86_64 -bios build/coreboot.rom -serial stdio -M q35 -accel kvm -cpu host +``` + diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 1749064..0eefee8 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -37,6 +37,8 @@ - [Spike RISC-V emulator](emulation/spike-riscv.md) - [Qemu RISC-V emulator](emulation/qemu-riscv.md) - [Qemu AArch64 emulator](emulation/qemu-aarch64.md) +- [Qemu x86 Q35](emulation/qemu-q35.md) +- [Qemu x86 PC](emulation/qemu-i440fx.md) ## Facebook diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 21ada02..af0c746 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -2,12 +2,29 @@ config CPU_QEMU_X86 bool - select ARCH_BOOTBLOCK_X86_32 - select ARCH_VERSTAGE_X86_32 - select ARCH_ROMSTAGE_X86_32 - select ARCH_RAMSTAGE_X86_32 select SMP select UDELAY_TSC select TSC_MONOTONIC_TIMER select UNKNOWN_TSC_RATE select SMM_ASEG + +if CPU_QEMU_X86 + +config CPU_QEMU_X86_64 + bool "Experimental 64bit support" + select ARCH_BOOTBLOCK_X86_64 + select ARCH_VERSTAGE_X86_64 + select ARCH_ROMSTAGE_X86_64 + select ARCH_POSTCAR_X86_64 + select ARCH_RAMSTAGE_X86_64 + +config CPU_QEMU_X86_32 + bool + default n if CPU_QEMU_X86_64 + default y + select ARCH_BOOTBLOCK_X86_32 + select ARCH_VERSTAGE_X86_32 + select ARCH_ROMSTAGE_X86_32 + select ARCH_POSTCAR_X86_32 + select ARCH_RAMSTAGE_X86_32 +endif -- To view, visit https://review.coreboot.org/c/coreboot/+/29667 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If2f02a95b2f91ab51043d4e81054354f4a6eb5d5 Gerrit-Change-Number: 29667 Gerrit-PatchSet: 43 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-MessageType: merged

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Change in coreboot[master]: soc/intel/jasperlake: Apply FiVR related settings
by Meera Ravindranath (Code Review) 19 Aug '20

19 Aug '20

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41062 ) Change subject: soc/intel/jasperlake: Apply FiVR related settings ...................................................................... Patch Set 19: Can we please start active review on this CL? -- To view, visit https://review.coreboot.org/c/coreboot/+/41062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Gerrit-Change-Number: 41062 Gerrit-PatchSet: 19 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 19 Aug 2020 10:29:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Apply FiVR related settings
by Meera Ravindranath (Code Review) 19 Aug '20

19 Aug '20

Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/41062 ) Change subject: soc/intel/jasperlake: Apply FiVR related settings ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/41062 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ief81fe481c94abef9754881cf1f454699fafa52e Gerrit-Change-Number: 41062 Gerrit-PatchSet: 19 Gerrit-Owner: Meera Ravindranath <meera.ravindranath(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Comment-Date: Wed, 19 Aug 2020 10:27:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cpu/x86/64bit/exit32: Add support for ramstage
by Patrick Rudolph (Code Review) 19 Aug '20

19 Aug '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44504 ) Change subject: cpu/x86/64bit/exit32: Add support for ramstage ...................................................................... cpu/x86/64bit/exit32: Add support for ramstage When compiled in RAMSTAGE use the segments for ramstage. Allows to call this assembly code in ramstage to exit long mode. The next commit makes use of this. Tested on qemu: Still boots on x86_64. Change-Id: I8beb31866bd15afc206b480b1ba05df995adc402 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/x86/64bit/exit32.inc 1 file changed, 10 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/44504/1 diff --git a/src/cpu/x86/64bit/exit32.inc b/src/cpu/x86/64bit/exit32.inc index 48837d9..6722cfd 100644 --- a/src/cpu/x86/64bit/exit32.inc +++ b/src/cpu/x86/64bit/exit32.inc @@ -12,14 +12,22 @@ #include <cpu/x86/msr.h> #include <cpu/x86/cr.h> +#if defined(__RAMSTAGE__) +#include <arch/ram_segs.h> +#define CODE_SEG RAM_CODE_SEG +#define DATA_SEG RAM_DATA_SEG +#else #include <arch/rom_segs.h> +#define CODE_SEG ROM_CODE_SEG +#define DATA_SEG ROM_DATA_SEG +#endif drop_longmode: /* Ensure cache is clean. */ wbinvd /* Set 32-bit code segment and ss */ - mov $ROM_CODE_SEG, %rcx + mov $CODE_SEG, %rcx /* SetCodeSelector32 will drop us to protected mode on return */ call SetCodeSelector32 @@ -54,7 +62,7 @@ /* Running in 32-bit compatibility mode */ /* Use flat data segment */ - movl $ROM_DATA_SEG, %eax + movl $DATA_SEG, %eax movl %eax, %ds movl %eax, %es movl %eax, %ss -- To view, visit https://review.coreboot.org/c/coreboot/+/44504 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8beb31866bd15afc206b480b1ba05df995adc402 Gerrit-Change-Number: 44504 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: arch/x86/boot: Jump to payload in protected mode
by Patrick Rudolph (Code Review) 19 Aug '20

19 Aug '20

Patrick Rudolph has submitted this change. ( https://review.coreboot.org/c/coreboot/+/30118 ) Change subject: arch/x86/boot: Jump to payload in protected mode ...................................................................... arch/x86/boot: Jump to payload in protected mode * On ARCH_RAMSTAGE_X86_64 jump to the payload in protected mode. * Add a helper function to jump to arbitrary code in protected mode, similar to the real mode call handler. * Doesn't affect existing x86_32 code. * Add a macro to cast pointer to uint32_t that dies if it would overflow on conversion Tested on QEMU Q35 using SeaBIOS as payload. Tested on Lenovo T410 with additional x86_64 patches. Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/30118 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M Documentation/arch/x86/index.md M src/arch/x86/Makefile.inc M src/arch/x86/boot.c A src/arch/x86/c_exit.S M src/arch/x86/include/arch/boot/boot.h M src/include/assert.h 6 files changed, 74 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/Documentation/arch/x86/index.md b/Documentation/arch/x86/index.md index 81eb519..7b9e1fc 100644 --- a/Documentation/arch/x86/index.md +++ b/Documentation/arch/x86/index.md @@ -15,6 +15,8 @@ * The high dword of pointers is always zero * The reference implementation is qemu * The CPU supports 1GiB hugepages +* x86 payloads are loaded below 4GiB in physical memory and are jumped + to in *protected mode* ## Assuptions for all stages using the reference implementation * 0-4GiB are identity mapped using 2MiB-pages as WB @@ -47,7 +49,7 @@ * Add assembly code for long mode - *DONE* * Add assembly code for SMM - *DONE* * Add assembly code for postcar stage - *DONE* -* Add assembly code to return to protected mode - *TODO* +* Add assembly code to return to protected mode - *DONE* * Implement reference code for mainboard `emulation/qemu-q35` - *TODO* ## Future work diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 5bba47f..a5c3309 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -245,6 +245,7 @@ ramstage-y += boot.c ramstage-y += post.c ramstage-y += c_start.S +ramstage-y += c_exit.S ramstage-y += cpu.c ramstage-y += cpu_common.c ramstage-y += ebda.c diff --git a/src/arch/x86/boot.c b/src/arch/x86/boot.c index db9d69e..777a0b7 100644 --- a/src/arch/x86/boot.c +++ b/src/arch/x86/boot.c @@ -1,10 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <arch/boot/boot.h> #include <commonlib/helpers.h> #include <console/console.h> #include <program_loading.h> #include <ip_checksum.h> #include <symbols.h> +#include <assert.h> int payload_arch_usable_ram_quirk(uint64_t start, uint64_t size) { @@ -19,6 +21,13 @@ void arch_prog_run(struct prog *prog) { +#if ENV_RAMSTAGE && defined(__x86_64__) + const uint32_t arg = pointer_to_uint32_safe(prog_entry_arg(prog)); + const uint32_t entry = pointer_to_uint32_safe(prog_entry(prog)); + + /* On x86 coreboot payloads expect to be called in protected mode */ + protected_mode_jump(entry, arg); +#else #ifdef __x86_64__ void (*doit)(void *arg); #else @@ -27,4 +36,5 @@ #endif doit = prog_entry(prog); doit(prog_entry_arg(prog)); +#endif } diff --git a/src/arch/x86/c_exit.S b/src/arch/x86/c_exit.S new file mode 100644 index 0000000..e5b9bf8 --- /dev/null +++ b/src/arch/x86/c_exit.S @@ -0,0 +1,38 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <arch/ram_segs.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/cr.h> + + +#ifdef __x86_64__ + + /* + * Functions to handle mode switches from long mode to protected + * mode. + */ +.text +.code64 + .section ".text.protected_mode_jump", "ax", @progbits + .globl protected_mode_jump +protected_mode_jump: + + push %rbp + mov %rsp, %rbp + + /* Arguments to stack */ + push %rdi + push %rsi + + #include <cpu/x86/64bit/exit32.inc> + + movl -8(%ebp), %eax /* Function to call */ + movl -16(%ebp), %ebx /* Argument 0 */ + + /* Align the stack */ + andl $0xFFFFFFF0, %esp + subl $12, %esp + pushl %ebx /* Argument 0 */ + + jmp *%eax +#endif diff --git a/src/arch/x86/include/arch/boot/boot.h b/src/arch/x86/include/arch/boot/boot.h index c735915..1ef927e 100644 --- a/src/arch/x86/include/arch/boot/boot.h +++ b/src/arch/x86/include/arch/boot/boot.h @@ -7,4 +7,15 @@ #define ELF_DATA ELFDATA2LSB #define ELF_ARCH EM_386 +#include <types.h> +/* + * Jump to function in protected mode. + * @arg func_ptr Function to jump to in protected mode + * @arg Argument to pass to called function + * + * @noreturn + */ +void protected_mode_jump(uint32_t func_ptr, + uint32_t argument); + #endif /* ASM_I386_BOOT_H */ diff --git a/src/include/assert.h b/src/include/assert.h index 262b8cc..944c677 100644 --- a/src/include/assert.h +++ b/src/include/assert.h @@ -80,4 +80,15 @@ *(type *)(uintptr_t)0; \ }) +#ifdef __x86_64__ +#define pointer_to_uint32_safe(x) ({ \ + if ((uintptr_t)(x) > 0xffffffffUL) \ + die("Cast from pointer to uint32_t overflows"); \ + (uint32_t)(uintptr_t)(x); \ +}) +#else +#define pointer_to_uint32_safe(x) ({ \ + (uint32_t)(uintptr_t)(x); \ +}) +#endif #endif // __ASSERT_H__ -- To view, visit https://review.coreboot.org/c/coreboot/+/30118 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6552ac30f1b6205e08e16d251328e01ce3fbfd14 Gerrit-Change-Number: 30118 Gerrit-PatchSet: 34 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: merged

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Change in coreboot[master]: UDK2017/IntelFsp2Pkg: Add FSP*_ARCH_UPD.
by Ronak Kanabar (Code Review) 19 Aug '20

19 Aug '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44414 ) Change subject: UDK2017/IntelFsp2Pkg: Add FSP*_ARCH_UPD. ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/c/coreboot/+/44414/7//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44414/7//COMMIT_MSG@7 PS7, Line 7: UDK2017/IntelFsp2Pkg: Add FSP*_ARCH_UPD. > Does the Jasper Lake FSP use UDK2017 bindings? CB:42239 added edk2-stable202005 headers yes, JSL is using UDK2017. main point of this CL is that. In new FSPv2295 JSL need Headers with FSPS_ARCH_UPD which is not in edk2-stable202005 also. thats why i updated here in UDK2017. -- To view, visit https://review.coreboot.org/c/coreboot/+/44414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21b0a72eae49976a0e36b4ac69c2efec8aaffabc Gerrit-Change-Number: 44414 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 19 Aug 2020 08:38:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: comment

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