coreboot-gerrit August 2020

coreboot-gerrit@coreboot.org

1 participants
2457 discussions

Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Tim Wawrzynczak (Code Review) 19 Aug '20

19 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Wed, 19 Aug 2020 22:43:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: util/cbfstool/lz4/lib: Remove empty lines at end of file
by HAOUAS Elyes (Code Review) 19 Aug '20

19 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44590 ) Change subject: util/cbfstool/lz4/lib: Remove empty lines at end of file ...................................................................... util/cbfstool/lz4/lib: Remove empty lines at end of file Change-Id: Id27cc43911a1e62d4f1d2d49d18294cb727f9bcf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/cbfstool/lz4/lib/lz4.c M util/cbfstool/lz4/lib/xxhash.c 2 files changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/44590/1 diff --git a/util/cbfstool/lz4/lib/lz4.c b/util/cbfstool/lz4/lib/lz4.c index e393690..00d5fd1 100644 --- a/util/cbfstool/lz4/lib/lz4.c +++ b/util/cbfstool/lz4/lib/lz4.c @@ -1565,4 +1565,3 @@ } #endif /* LZ4_COMMONDEFS_ONLY */ - diff --git a/util/cbfstool/lz4/lib/xxhash.c b/util/cbfstool/lz4/lib/xxhash.c index 0f89626..74d0d14 100644 --- a/util/cbfstool/lz4/lib/xxhash.c +++ b/util/cbfstool/lz4/lib/xxhash.c @@ -958,5 +958,3 @@ else return XXH64_digest_endian(state_in, XXH_bigEndian); } - - -- To view, visit https://review.coreboot.org/c/coreboot/+/44590 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id27cc43911a1e62d4f1d2d49d18294cb727f9bcf Gerrit-Change-Number: 44590 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/volteer: Implement weak function `cse_board_reset`
by Tim Wawrzynczak (Code Review) 19 Aug '20

19 Aug '20

Tim Wawrzynczak has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44536 ) Change subject: mb/google/volteer: Implement weak function `cse_board_reset` ...................................................................... mb/google/volteer: Implement weak function `cse_board_reset` Since Volteer also uses the CSE Lite SKU and the cr50, it is subject to a problem where old cr50 FW will not be able to properly detect an SoC reset, so the reset on cold boots caused by the CSE Lite RO->RW jump should instead get an assist from the EC, which can perform a full cold reset. BUG=b:162977697 TEST=Verify EC performs the cold reset Signed-off-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Change-Id: Ie8ae21c203da218459d5fd30a23be23520ed0598 --- M src/mainboard/google/volteer/mainboard.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/44536/1 diff --git a/src/mainboard/google/volteer/mainboard.c b/src/mainboard/google/volteer/mainboard.c index 5317c11..a926673 100644 --- a/src/mainboard/google/volteer/mainboard.c +++ b/src/mainboard/google/volteer/mainboard.c @@ -6,10 +6,18 @@ #include <device/device.h> #include <ec/ec.h> #include <ec/google/chromeec/ec.h> +#include <halt.h> +#include <intelblocks/cse.h> #include <soc/gpio.h> #include <vendorcode/google/chromeos/chromeos.h> #include <variant/gpio.h> +void cse_board_reset(void) +{ + if (!google_chromeec_ap_reset()) + halt(); +} + static void mainboard_init(struct device *dev) { mainboard_ec_init(); -- To view, visit https://review.coreboot.org/c/coreboot/+/44536 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie8ae21c203da218459d5fd30a23be23520ed0598 Gerrit-Change-Number: 44536 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-MessageType: newchange

5 7

Change in coreboot[master]: Makefile.inc: Remove redundant -fno-common CFLAG
by HAOUAS Elyes (Code Review) 19 Aug '20

19 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44215 ) Change subject: Makefile.inc: Remove redundant -fno-common CFLAG ...................................................................... Makefile.inc: Remove redundant -fno-common CFLAG GCC 10 defaults to -fno-common. Change-Id: I7c27beaa4e0311a072a1c7c00bfc1bfa46901c6c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44215/1 diff --git a/Makefile.inc b/Makefile.inc index 63b4977..2526c25 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -424,7 +424,7 @@ CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else -CFLAGS_common += -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer +CFLAGS_common += -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie # Disable 'overflow' warning for previously unaffected MCHBARx_AND_OR macro -- To view, visit https://review.coreboot.org/c/coreboot/+/44215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7c27beaa4e0311a072a1c7c00bfc1bfa46901c6c Gerrit-Change-Number: 44215 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

1 2

Change in coreboot[master]: mb/intel/jasperlake_rvp: Update data-lanes and I2C address for OV9734
by Sugnan Prabhu S (Code Review) 19 Aug '20

19 Aug '20

Sugnan Prabhu S has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44583 ) Change subject: mb/intel/jasperlake_rvp: Update data-lanes and I2C address for OV9734 ...................................................................... mb/intel/jasperlake_rvp: Update data-lanes and I2C address for OV9734 Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Change-Id: I5910bcace770fe3dea440f35b56621d59fe7f395 --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/44583/1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb index dfe26b7..01dcea2 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/devicetree.cb @@ -179,7 +179,7 @@ register "device_type" = "INTEL_ACPI_CAMERA_CIO2" register "cio2_num_ports" = "2" - register "cio2_lanes_used" = "{2,2}" + register "cio2_lanes_used" = "{1,2}" register "cio2_lane_endpoint[0]" = ""^I2C4.CAM0"" register "cio2_lane_endpoint[1]" = ""^I2C5.CAM1"" register "cio2_prt[0]" = "0" @@ -354,7 +354,7 @@ register "off_seq.ops[1]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" register "off_seq.ops[2]" = "SEQ_OPS_CLK_DISABLE(0, 0)" - device i2c 10 on end + device i2c 36 on end end end device pci 19.1 on # I2C #5 Cam 1 and VCM -- To view, visit https://review.coreboot.org/c/coreboot/+/44583 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5910bcace770fe3dea440f35b56621d59fe7f395 Gerrit-Change-Number: 44583 Gerrit-PatchSet: 1 Gerrit-Owner: Sugnan Prabhu S <sugnan.prabhu.s(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: Disable SeaBIOS options not supported by hardware: scripts to apply t...
by Mike Banon (Code Review) 19 Aug '20

19 Aug '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39899 ) Change subject: Disable SeaBIOS options not supported by hardware: scripts to apply the patches ...................................................................... Disable SeaBIOS options not supported by hardware: scripts to apply the patches These scripts will help you to securely and conveniently apply CB:33871 to disable SeaBIOS options not supported by ASUS AM1I-A and A88XM-E hardware. Save to ./coreboot/ then run ./get_cfgsb_patches.sh , ./check... and ./apply... https://review.coreboot.org/c/coreboot/+/33871 mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware https://review.coreboot.org/c/coreboot/+/39898 mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I4f001164f110a9b14297f981de8b39f30dfca4fc --- A apply_cfgsb_patches.sh A check_cfgsb_patches.sh A get_cfgsb_patches.sh A sha256sums_cfgsb_correct.txt 4 files changed, 45 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/39899/1 diff --git a/apply_cfgsb_patches.sh b/apply_cfgsb_patches.sh new file mode 100755 index 0000000..1654de0 --- /dev/null +++ b/apply_cfgsb_patches.sh @@ -0,0 +1,14 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/33871 +### mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware +### +patch -p1 < "./aa8fb0a.diff" +### +### https://review.coreboot.org/c/coreboot/+/39898 +### mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware +### +if [ -d "./src/mainboard/asus/a88xm-e/" ]; then + patch -p1 < "./81da3da.diff" +fi +### diff --git a/check_cfgsb_patches.sh b/check_cfgsb_patches.sh new file mode 100755 index 0000000..5c8b01e --- /dev/null +++ b/check_cfgsb_patches.sh @@ -0,0 +1,13 @@ +#!/bin/sh +rm -f "./sha256sums_cfgsb_my.txt" +sha256sum "./aa8fb0a.diff" > "./sha256sums_cfgsb_my.txt" +sha256sum "./81da3da.diff" >> "./sha256sums_cfgsb_my.txt" +if cmp -s "./sha256sums_cfgsb_my.txt" "./sha256sums_cfgsb_correct.txt" +then + echo "SHA256 checksums are correct, please run ./apply_cfgsb_patches.sh" + exit 0 +else + echo "! MISMATCH ! See ./sha256sums_cfgsb_my.txt and ./sha256sums_cfgsb_correct.txt" + exit 1 +fi +# diff --git a/get_cfgsb_patches.sh b/get_cfgsb_patches.sh new file mode 100755 index 0000000..7c0a60a --- /dev/null +++ b/get_cfgsb_patches.sh @@ -0,0 +1,16 @@ +#!/bin/sh +### +### https://review.coreboot.org/c/coreboot/+/33871 +### mb/asus/am1i-a: Disable SeaBIOS options unsupported by hardware +### +rm -f "./aa8fb0a.diff" +wget "https://review.coreboot.org/changes/33871/revisions/4/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./aa8fb0a.diff" +### +### https://review.coreboot.org/c/coreboot/+/39898 +### mb/asus/a88xm-e: Disable SeaBIOS options unsupported by hardware +### +rm -f "./81da3da.diff" +wget "https://review.coreboot.org/changes/39898/revisions/1/patch?zip" +unzip "./patch?zip" && rm -f "./patch?zip" # && patch -p1 < "./81da3da.diff" +### diff --git a/sha256sums_cfgsb_correct.txt b/sha256sums_cfgsb_correct.txt new file mode 100644 index 0000000..9e41170 --- /dev/null +++ b/sha256sums_cfgsb_correct.txt @@ -0,0 +1,2 @@ +221ef13ab26faa7874c6a877d63a8130ab47fe9b1026082d890187b124cc5952 ./aa8fb0a.diff +f90525582937d2bc07771b45c5487181a9058dbfa564c3c9ec42eef18e617ed6 ./81da3da.diff -- To view, visit https://review.coreboot.org/c/coreboot/+/39899 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4f001164f110a9b14297f981de8b39f30dfca4fc Gerrit-Change-Number: 39899 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

1 3

Change in ...coreboot[master]: tint: introduce the new tint build system with checksum verification
by Mike Banon (Code Review) 19 Aug '20

19 Aug '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/33887 Change subject: tint: introduce the new tint build system with checksum verification ...................................................................... tint: introduce the new tint build system with checksum verification Three stages of the new tint build system: 1) generate_core.sh extracts the core part from buildgcc script, most importantly the checksum calculation/verification functions. 2) tintify_core.sh adds the tint-specific footer/header to the core, such as the properties of current version including its checksum. 3) tint.sh - generated and "tintified" core script - builds a tint. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I20d7cd477595aa73f3cab9c78235f4de9813b989 --- M payloads/external/tint/Makefile A payloads/external/tint/generate_core.sh R payloads/external/tint/tint-0.04-nmu1_libpayload.patch A payloads/external/tint/tintify_core.sh 4 files changed, 252 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/33887/1 diff --git a/payloads/external/tint/Makefile b/payloads/external/tint/Makefile index 253bfea..95cbd87 100644 --- a/payloads/external/tint/Makefile +++ b/payloads/external/tint/Makefile @@ -1,5 +1,25 @@ -project_url=https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_0.04+nmu1.tar.gz -archive_name=tint_0.04+nmu1.tar.gz +# +# TINT build system - helps to securely download TINT with a checksum verification and build it. +# + +# +# Properties of the current TINT version +# + +TINT_VERSION=0.04-nmu1 +TINT_EXT_VERSION=0.04+nmu1 +TINT_ARCHIVE_LINK="https://mirror.fsf.org/trisquel/pool/main/t/tint/tint_${TINT_EXT_VERSION}.t…" +TINT_ARCHIVE="tint_${TINT_VERSION}.tar.gz" +TINT_DIR="tint-${TINT_VERSION}" +TINT_CHECKSUM="7fcaa428c6d0de7096d1e4fbfd14848096ae5aad" + +# +# Locations of the input/output scripts +# + +buildgcc="./../../../util/crossgcc/buildgcc" +corescript="./core.sh" +tintified="./tint.sh" unexport KCONFIG_AUTOHEADER unexport KCONFIG_AUTOCONFIG @@ -10,28 +30,39 @@ all: tint -tint: patch - echo " MAKE TINT " - $(MAKE) -C tint +################################################################################ +# +# Three stages of TINT build system: +# +# 1) generate_core.sh extracts the core part from buildgcc script, +# most importantly the checksum calculation/verification functions. +# +# 2) tintify_core.sh adds the TINT-specific footer/header to the core, +# such as the properties of current version including its checksum. +# +# 3) tint.sh - generated and "tintified" core script - builds a TINT. +# +################################################################################ -patch: download - cd tint; \ - if [ -e debian ]; then \ - rm -rf debian typedefs.h Makefile; \ - touch Makefile; \ - patch -l -p1 < ../libpayload_tint.patch; \ - fi - -download: - test -d tint || { wget $(project_url); \ - tar -xvf $(archive_name); \ - rm $(archive_name); \ - mv tint-0.04+nmu1 tint; } +tint: + if [ ! -f ${tintified} ]; then \ + chmod +x "./generate_core.sh" ; \ + "./generate_core.sh" ${buildgcc} ${corescript} "prepare_before_patch" ; \ + chmod +x "./tintify_core.sh" ; \ + "./tintify_core.sh" ${corescript} ${tintified} \ + ${TINT_ARCHIVE_LINK} ${TINT_ARCHIVE} ${TINT_DIR} ${TINT_CHECKSUM} ; \ + fi ; \ + chmod +x ${tintified} + ${tintified} clean: - test -d tint && $(MAKE) -C tint clean || exit 0 + test -d "./tint/" && $(MAKE) -C "./tint/" clean || exit 0 distclean: - rm -rf tint + rm -rf "./tint/" + rm -f ${corescript} + rm -f ${tintified} -.PHONY: download patch tint clean distclean +.PHONY: tint clean distclean + +# diff --git a/payloads/external/tint/generate_core.sh b/payloads/external/tint/generate_core.sh new file mode 100755 index 0000000..bb0de2d --- /dev/null +++ b/payloads/external/tint/generate_core.sh @@ -0,0 +1,102 @@ +#!/bin/sh +# +# generate_core.sh extracts the core part from buildgcc script, +# most importantly the checksum calculation/verification functions. +# +# Copyright (C) 2019 Mike Banon <mikebdp2(a)gmail.com> +# +############################################################################## +# +# USAGE: +# ./generate_core.sh <buildgcc> <corescript> prepare_before_patch +# where +# buildgcc - path to input buildgcc script +# corescript - path to output core part script +# prepare_before_patch - optional argument to insert prepare_${package} +# call into the unpack_and_patch function, e.g. +# for removing some files with rm command +# in order to reduce the size of patch file +# +############################################################################## + +buildgcc="$1" +corescript="$2" +prepare_before_patch="$3" + +# +# Imports the source file fragment between start and end into the +# destination file, optionally excluding the last line if not needed +# + +import_from_file() { + source="$1" + destination="$2" + start="$3" + end="$4" + last_line_disabled="$5" + if [ -z "${last_line_disabled}" ] ; then + sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};{p}}" "$source" >> "$destination" + else + sed -n "/^${start}/,/^${end}/{/^${start}/{p;n};/^${end}/{q};{p}}" "$source" >> "$destination" + fi +} + +# +# Import the color defines together with UNAME/HALT_FOR_TOOLS variables +# + +import_from_file "$buildgcc" "$corescript" "red=" "HALT_FOR_TOOLS=0" || exit "$?" + +# +# Import the core functions +# + +FUNCTIONS="please_install searchtool download compute_hash error_hash_mismatch verify_hash unpack_and_patch" + +for F in $FUNCTIONS ; do + import_from_file "$buildgcc" "$corescript" "$F()" "}" || exit "$?" +done + +# +# Import a fragment where we find tar/patch/make and other essential tools +# + +import_from_file "$buildgcc" "$corescript" "# Find all the required tools" "# Allow" "last_line_disabled" || exit "$?" + +# +# Import a fragment with conditional exit if some required tools were not found +# + +import_from_file "$buildgcc" "$corescript" "if \[ \"\$HALT_FOR_TOOLS" "fi" || exit "$?" + +# +# Avoid the unnecessary subdirectories holding a single file each +# + +sed -i -e "s/patches\///g" "$corescript" +sed -i -e "s/sum\///g" "$corescript" +sed -i -e "s/tarballs\///g" "$corescript" +sed -i -e "s/cd tarballs || exit 1//g" "$corescript" +sed -i -e "s/cd \.\.//g" "$corescript" + +# +# Get the known checksum without using a dedicated single-line file +# + +sed -i -e "s/\tknown_hash=\"\$(get_known_hash.*/\tknown_hash=\"\$2\"/g" "$corescript" + +# +# Update the paths printed at the error messages +# + +sed -i -e "s/util\/crossgcc\///g" "$corescript" + +# +# Insert prepare_${package} function call between the unpack and patch operations +# + +if [ ! -z "${prepare_before_patch}" ] ; then + sed -i -e "/\$TAR \$FLAGS \"\$(basename \"\$archive\")\"/a prepare_\${package} || exit \"\$?\"" "$corescript" +fi + +# diff --git a/payloads/external/tint/libpayload_tint.patch b/payloads/external/tint/tint-0.04-nmu1_libpayload.patch similarity index 100% rename from payloads/external/tint/libpayload_tint.patch rename to payloads/external/tint/tint-0.04-nmu1_libpayload.patch diff --git a/payloads/external/tint/tintify_core.sh b/payloads/external/tint/tintify_core.sh new file mode 100755 index 0000000..77abc14 --- /dev/null +++ b/payloads/external/tint/tintify_core.sh @@ -0,0 +1,98 @@ +#!/bin/sh +# +# tintify_core.sh adds the TINT-specific footer/header to the core, +# such as the properties of current TINT version including its checksum. +# +# Copyright (C) 2019 Mike Banon <mikebdp2(a)gmail.com> +# +################################################################################ +# +# USAGE: +# ./tintify_core.sh <corescript> <tintified> \ +# <TINT_ARCHIVE_LINK> <TINT_ARCHIVE> <TINT_DIR> <TINT_CHECKSUM> +# where +# corescript - path to input core script +# tintified - path to output tint script +# +################################################################################ + +corescript="$1" +tintified="$2" + +# +# TINT-specific header +# + +# +# Insert the properties of the current TINT version +# + +echo "#!/bin/sh" > "$tintified" +echo "TINT_ARCHIVE_LINK=${3}" >> "$tintified" +echo "TINT_ARCHIVE=${4}" >> "$tintified" +echo "TINT_DIR=${5}" >> "$tintified" +echo "TINT_CHECKSUM=${6}" >> "$tintified" + +# +# Add the replace_plus_with_minus() function - needed to fix the version number +# + +echo "replace_plus_with_minus() {" >> "$tintified" +echo "for x in *\"+\"*; do" >> "$tintified" +echo "y=\$(printf %sa \"\$x\" | tr \"+\" \"-\")" >> "$tintified" +echo "mv -- \"\$x\" \"\${y%a}\"" >> "$tintified" +echo "done" >> "$tintified" +echo "}" >> "$tintified" + +# +# Add the prepare_TINT() function, it will remove the unneeded debian directory +# as well as typedefs.h and old Makefile to significantly reduce the patch size +# + +echo "prepare_TINT() {" >> "$tintified" +echo "replace_plus_with_minus" >> "$tintified" +echo "if [ ! -z ./\${TINT_DIR} ] && [ -e ./\${TINT_DIR}/debian ] ; then" >> "$tintified" +echo "rm -rf ./\${TINT_DIR}/debian ./\${TINT_DIR}/typedefs.h ./\${TINT_DIR}/Makefile;" >> "$tintified" +echo "touch ./\${TINT_DIR}/Makefile;" >> "$tintified" +echo "fi" >> "$tintified" +echo "}" >> "$tintified" + +# +# Importing the core script +# + +cat "$corescript" >> "$tintified" + +# +# download() function adjustments - became necessary after a version number fix +# + +sed -i -e "/download() {/a package=\$1\narchive_link=\"\$(eval echo \\\\\$\$package\"_ARCHIVE_LINK\")\"" "$tintified" +sed -i -e "s/downloading from \$archive/&_link/g" "$tintified" +sed -i -e "s/$download_showing_percentage \"\$archive$./\1_link\"\nreplace_plus_with_minus/g" "$tintified" + +# +# TINT-specific footer +# + +echo "if [ ! -d tint ] ; then" >> "$tintified" + +echo "printf \"Downloading and verifying TINT tarball ... \\n\"" >> "$tintified" +echo "download TINT || exit \"\$?\"" >> "$tintified" +echo "verify_hash TINT \${TINT_CHECKSUM} || exit \"\$?\"" >> "$tintified" +echo "printf \"Downloaded TINT tarball ... \${green}ok\${NC}\\n\"" >> "$tintified" + +echo "printf \"Unpacking and patching TINT... \\n\"" >> "$tintified" +echo "unpack_and_patch TINT || exit 1" >> "$tintified" +echo "printf \"Unpacked and patched TINT... \${green}ok\${NC}\\n\"" >> "$tintified" + +echo "mv ./\${TINT_DIR} ./tint" >> "$tintified" +echo "fi" >> "$tintified" + +echo "printf \"Building TINT ... \\n\"" >> "$tintified" +echo "make -C ./tint" >> "$tintified" +echo "printf \"TINT built ... \${green}ok\${NC}\\n\"" >> "$tintified" + +chmod +x "$tintified" + +# -- To view, visit https://review.coreboot.org/c/coreboot/+/33887 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I20d7cd477595aa73f3cab9c78235f4de9813b989 Gerrit-Change-Number: 33887 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2295
by Karthik Ramasubramanian (Code Review) 19 Aug '20

19 Aug '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44415 ) Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2295 ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I569987427cccefc1c5015bdabb10b41f29f2624a Gerrit-Change-Number: 44415 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 19 Aug 2020 16:14:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/jasperlake: Select PLATFORM_USES_FSP2_2
by Karthik Ramasubramanian (Code Review) 19 Aug '20

19 Aug '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43815 ) Change subject: soc/intel/jasperlake: Select PLATFORM_USES_FSP2_2 ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/43815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia606ec26da93242ecdd602a9b3badbece5dcd034 Gerrit-Change-Number: 43815 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 19 Aug 2020 16:03:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: soc/intel/jasperlake: Disable multiphase SI init
by Karthik Ramasubramanian (Code Review) 19 Aug '20

19 Aug '20

Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43816 ) Change subject: soc/intel/jasperlake: Disable multiphase SI init ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/43816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d591b46c403e68ff0b41ac8f87c742ae774111e Gerrit-Change-Number: 43816 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 19 Aug 2020 16:02:44 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit August 2020