Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44557 )
Change subject: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths
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Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/44557/1/src/soc/intel/tigerlake/fs…
File src/soc/intel/tigerlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/44557/1/src/soc/intel/tigerlake/fs…
PS1, Line 118: assrt
assert ?
https://review.coreboot.org/c/coreboot/+/44557/1/src/soc/intel/tigerlake/fs…
PS1, Line 204: EDS "
: "spec
nit: As far as I know, `EDS` means `External Design Specification`, so `EDS spec` would be `External Design Specification spec`, which is a bit redundant.
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f
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