coreboot-gerrit August 2020

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Change in coreboot[master]: mb/google/volteer/*/gpio.c: add GPP_D16 to early_gpio_table
by Caveh Jalali (Code Review) 20 Aug '20

20 Aug '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44117 ) Change subject: mb/google/volteer/*/gpio.c: add GPP_D16 to early_gpio_table ...................................................................... Patch Set 2: > Patch Set 1: > > This is missing changes for baseboard, Halvor, and Trondo. They each export their own early_gpio_table under certain conditions. halvor already has this change. trondo only has a skeletal gpio.c, so there's nothing to update yet. -- To view, visit https://review.coreboot.org/c/coreboot/+/44117 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf5e770f540e5d1e27b40f270bb004f4196bc7be Gerrit-Change-Number: 44117 Gerrit-PatchSet: 2 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 20 Aug 2020 23:37:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback
by Furquan Shaikh (Code Review) 20 Aug '20

20 Aug '20

Furquan Shaikh has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback ...................................................................... cse_lite: Move global reset after MRC writeback With CSE-lite enabled, we were going through the lengthy memory training procedure twice on the first power-on boot or after full BIOS SPI flash update. This moves the global reset performed to achieve the CSE-lite RO to RW reboot to a later boot phase so that it happens after the memory training data has been written to the MRC cache. Now, the 2nd (and subsequent) reboot can utilize the memory training data established during the 1st boot. This reduces the first boot time by about 20s on a 16GB system. Looking at the timing stats form cbmem, the normal boot penalty is about 300ms - mostly attributed to running FspSiliconInit a 2nd time. We will get this time back when the mrc_cache refactoring effort lands (cb:44196, et. al). BUG=b:162021048 TEST=Booted on volteer, confirmed 20s faster boot time. Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Signed-off-by: Caveh Jalali <caveh(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/44430 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro(a)google.com> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 5 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Nick Vaccaro: Looks good to me, approved Tim Wawrzynczak: Looks good to me, approved diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index c29b56c..a8948be 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -663,7 +663,11 @@ } #if CONFIG(SOC_INTEL_TIGERLAKE) -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, cse_fw_sync, NULL); +/* + * This needs to happen after the MRC cache write to avoid a 2nd + * memory training sequence. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_RESOURCES, BS_ON_ENTRY, cse_fw_sync, NULL); #else BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 6 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback
by Caveh Jalali (Code Review) 20 Aug '20

20 Aug '20

Caveh Jalali has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback ...................................................................... Patch Set 5: (1 comment) https://review.coreboot.org/c/coreboot/+/44430/2//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44430/2//COMMIT_MSG@7 PS2, Line 7: cse_lite: Move global reset after MRC writeback. > Please remove the dot/period at the end of the summary. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 5 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Aug 2020 22:59:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: 3rdparty/vboot: Update to latest master
by Patrick Georgi (Code Review) 20 Aug '20

20 Aug '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44623 ) Change subject: 3rdparty/vboot: Update to latest master ...................................................................... 3rdparty/vboot: Update to latest master This also includes https://chromium-review.googlesource.com/2318026 which fixes an issue with duplicate symbols. Change-Id: Icf450616b3bcd8b7c01261c913cd172625dbd6ba Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M 3rdparty/vboot 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/44623/1 diff --git a/3rdparty/vboot b/3rdparty/vboot index ed23c08..3932b1c 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit ed23c08440dae6657d026a30b504578e03e0426f +Subproject commit 3932b1c8729e9bfac918da50224d06adae73fde0 -- To view, visit https://review.coreboot.org/c/coreboot/+/44623 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf450616b3bcd8b7c01261c913cd172625dbd6ba Gerrit-Change-Number: 44623 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/google/coral: Add USB2 phy setting override for Astronaut
by Paul Menzel (Code Review) 20 Aug '20

20 Aug '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/22135 ) Change subject: mainboard/google/coral: Add USB2 phy setting override for Astronaut ...................................................................... Patch Set 3: Clicking on the Change-Id of the revert doesn’t give a result. -- To view, visit https://review.coreboot.org/c/coreboot/+/22135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf5c9e5f4dae15630ec4d6ca6648cae78ca910c6 Gerrit-Change-Number: 22135 Gerrit-PatchSet: 3 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Assignee: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 20 Aug 2020 21:03:56 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: /soc/amd/acpi Move ACPI IVRS generation to coreboot
by Jason Glenesk (Code Review) 20 Aug '20

20 Aug '20

Hello Jason Glenesk, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43804 to review the following change. Change subject: /soc/amd/acpi Move ACPI IVRS generation to coreboot ...................................................................... /soc/amd/acpi Move ACPI IVRS generation to coreboot Add code for IVRS generation to coreboot. Publish coreboot generated structure rather than IVRS generated by FSP binary. BUG=b:155307433 TEST=Boot trembyle to shell and extract and compare IVRS tables Change-Id: I693f4399766c71c3ad53539634c65ba59afd0fe1 Signed-off-by: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> --- M src/acpi/acpi.c M src/include/acpi/acpi_ivrs.h M src/soc/amd/picasso/agesa_acpi.c 3 files changed, 525 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/43804/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 7873c0f..0b65459 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -1626,7 +1626,7 @@ case VFCT: /* ACPI 2.0/3.0/4.0: 1 */ return 1; case IVRS: - return IVRS_FORMAT_FIXED; + return IVRS_FORMAT_MIXED; case DBG2: return 0; case FACS: /* ACPI 2.0/3.0: 1, ACPI 4.0 upto 6.3: 2 */ diff --git a/src/include/acpi/acpi_ivrs.h b/src/include/acpi/acpi_ivrs.h index 82748d0..62408ee 100644 --- a/src/include/acpi/acpi_ivrs.h +++ b/src/include/acpi/acpi_ivrs.h @@ -40,6 +40,7 @@ /* Extended Feature Support */ #define IVINFO_EFR_SUPPORTED 0x01 +#define EFR_SUPPORT (1 << 27) /* IVHD Flags Field */ #define IVHD_FLAG_PPE_SUP (1 << 7) /* Type 10h only */ @@ -55,11 +56,11 @@ #define IOMMU_INFO_UNIT_ID_SHIFT 8 /* IVHD IOMMU Feature Reporting Field */ -#define IOMMU_FEATURE_HATS_SHIFT 30 /* Type 10h only */ -#define IOMMU_FEATURE_GATS_SHIFT 28 /* Type 10h only */ -#define IOMMU_FEATURE_MSI_NUM_PPR_SHIFT 23 -#define IOMMU_FEATURE_PN_BANKS_SHIFT 17 -#define IOMMU_FEATURE_PN_COUNTERS_SHIFT 13 +#define IOMMU_FEATURE_HATS_SHIFT 20 /* Type 10h only */ +#define IOMMU_FEATURE_GATS_SHIFT 16 /* Type 10h only */ +#define IOMMU_FEATURE_MSI_NUM_PPR_SHIFT 5 +#define IOMMU_FEATURE_PN_BANKS_SHIFT 5 +#define IOMMU_FEATURE_PN_COUNTERS_SHIFT 6 #define IOMMU_FEATURE_PA_SMAX_SHIFT 8 /* Type 10h only */ #define IOMMU_FEATURE_HE_SUP (1 << 7) /* Type 10h only */ @@ -68,8 +69,9 @@ #define IOMMU_FEATURE_GLX_SINGLE_LEVEL (0 << 3) /* Type 10h only */ #define IOMMU_FEATURE_GLX_TWO_LEVEL (1 << 3) /* Type 10h only */ #define IOMMU_FEATURE_GLX_THREE_LEVEL (2 << 3) /* Type 10h only */ -#define IOMMU_FEATURE_GT_SUP (1 << 1) /* Type 10h only */ -#define IOMMU_FEATURE_NX_SUP (1 << 0) /* Type 10h only */ +#define IOMMU_FEATURE_GT_SUP (1 << 2) /* Type 10h only */ +#define IOMMU_FEATURE_NX_SUP (1 << 1) /* Type 10h only */ +#define IOMMU_FEATURE_XT_SUP 1 /* IVHD Device Entry Type Codes */ #define IVHD_DEV_4_BYTE_ALL 0x01 @@ -106,6 +108,48 @@ #define IVHD_UID_INT 0x01 #define IVHD_UID_STRING 0x02 +#define IOMMU_CAP_ID 0x0f + +/// MMIO Offset 0x30 +#define MMIO_0X30_PRE_F_SUP 1 +#define MMIO_0X30_PPR_SUP (0x1 << 1) +#define MMIO_0X30_XT_SUP (0x1 << 2) +#define MMIO_0X30_NX_SUP (0x1 << 3) +#define MMIO_0X30_GT_SUP (0x1 << 4) +#define MMIO_0X30_EFR_IGNORED (0x1 << 5) +#define MMIO_0X30_IA_SUP (0x1 << 6) +#define MMIO_0X30_GA_SUP (0x1 << 7) +#define MMIO_0X30_HE_SUP (0x1 << 8) +#define MMIO_0X30_PC_SUP (0x1 << 9) +#define MMIO_0X30_HATS (0x3 << 10) +#define MMIO_0X30_GATS (0x3 << 12) +#define MMIO_0X30_GLX_SUP (0x3 << 14) +#define MMIO_0X30_SMI_F_SUP (0x3 << 16) +#define MMIO_0X30_SMI_FRC (0x7 << 18) +#define MMIO_0X30_GAM_SUP (0x7 << 21) +#define MMIO_0X30_PAS_MAX 0x1f00000000 + +/// MMIO Offset 0x18 +#define MMIO_0X18_IOMMU_EN 1 +#define MMIO_0X18_HT_TUN_EN (1 << 1) +#define MMIO_0X18_PASS_PW (1 << 8) +#define MMIO_0X18_RES_PASS_PW (1 << 9) +#define MMIO_0X18_COHERENT (1 << 10) +#define MMIO_0X18_ISOC (1 << 11) + +/// MMIO Offset 0x4000 +#define MMIO_0X4000_N_COUNTER_BANKS (0x3f << 12) +#define MMIO_0X4000_N_COUNTER (0xf << 7) + +/// Capability offset 0 +#define CAP_OFFSET_0_IOTLB_SP (1 << 24) + +/// Capability offset 10h +#define CAP_OFFSET_0X10_MSI_NUM_PPR (0x1f << 27) + +#define IOMMU_MMIO32(x) (*((volatile uint32_t *)(x))) +#define IOMMU_MMIO64(x) (*((volatile uint64_t *)(x))) + /* IVHD (I/O Virtualization Hardware Definition Block) 4-byte entry */ typedef struct ivrs_ivhd_generic { uint8_t type; @@ -123,6 +167,24 @@ uint8_t reserved2; } __packed ivrs_ivhd_alias_t; +/* IVRS IVHD (I/O Virtualization Hardware Definition Block) Type 40h */ +typedef struct acpi_ivrs_ivhd_40{ + uint8_t type; + uint8_t flags; + uint16_t length; + uint16_t device_id; + uint16_t capability_offset; + uint32_t iommu_base_low; + uint32_t iommu_base_high; + uint16_t pci_segment_group; + uint16_t iommu_info; + uint32_t iommu_attributes; + uint32_t efr_reg_image_low; + uint32_t efr_reg_image_high; + uint32_t reserved[2]; + uint8_t entry[0]; +} __packed acpi_ivrs_ivhd40_t; + typedef struct ivrs_ivhd_extended { uint8_t type; uint16_t dev_id; @@ -139,4 +201,25 @@ uint8_t variety; } __packed ivrs_ivhd_special_t; +typedef struct ivrs_ivhd_id { + uint8_t id_byte_0; + uint8_t id_byte_1; + uint8_t id_byte_2; + uint8_t id_byte_3; + uint8_t id_byte_4; + uint8_t id_byte_5; + uint8_t id_byte_6; + uint8_t id_byte_7; +} __packed ivrs_ivhd_id_t; + +typedef struct ivrs_ivhd_f0_entry { + uint8_t type; + uint16_t dev_id;; + uint8_t dte_setting; + ivrs_ivhd_id_t hardware_id; + ivrs_ivhd_id_t compatible_id; + uint8_t uuid_format; + uint8_t uuid_length; +} __packed ivrs_ivhd_f0_entry_t; + #endif /* __ACPI_ACPI_IVRS_H__ */ diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c index fb168a1..3ea8d7f 100644 --- a/src/soc/amd/picasso/agesa_acpi.c +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -1,11 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <acpi/acpi.h> +#include <acpi/acpi_ivrs.h> #include <console/console.h> #include <fsp/util.h> #include <FspGuids.h> #include <soc/acpi.h> #include <stdint.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <soc/pci_devs.h> +#include <stdlib.h> struct amd_fsp_acpi_hob_info { uint32_t table_size_in_bytes; @@ -39,15 +44,443 @@ return current; } +unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current) +{ + /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ + current = ALIGN_UP(current, 8); + ivrs_ivhd_special_t *ivhd_ioapic = (ivrs_ivhd_special_t *)current; + + ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; + ivhd_ioapic->reserved = 0x0000; + ivhd_ioapic->dte_setting = IVHD_DTE_LINT_1_PASS | IVHD_DTE_LINT_0_PASS | + IVHD_DTE_SYS_MGT_NO_TRANS | IVHD_DTE_NMI_PASS | + IVHD_DTE_EXT_INT_PASS | IVHD_DTE_INIT_PASS; + ivhd_ioapic->handle = CONFIG_MAX_CPUS; /* FCH IOAPIC ID */ + ivhd_ioapic->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); + ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; + current += sizeof(ivrs_ivhd_special_t); + + ivhd_ioapic = (ivrs_ivhd_special_t *)current; + + ivhd_ioapic->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; + ivhd_ioapic->reserved = 0x0000; + ivhd_ioapic->dte_setting = 0x00; + ivhd_ioapic->handle = CONFIG_MAX_CPUS + 1; /* GNB IOAPIC ID */ + ivhd_ioapic->source_dev_id = PCI_DEVFN(0, 1); + ivhd_ioapic->variety = IVHD_SPECIAL_DEV_IOAPIC; + current += sizeof(ivrs_ivhd_special_t); + + return current; +} + +static unsigned long ivhd_describe_hpet(unsigned long current) +{ + /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ + current = ALIGN_UP(current, 8); + ivrs_ivhd_special_t *ivhd_hpet = (ivrs_ivhd_special_t *)current; + + ivhd_hpet->type = IVHD_DEV_8_BYTE_EXT_SPECIAL_DEV; + ivhd_hpet->reserved = 0x0000; + ivhd_hpet->dte_setting = 0x00; + ivhd_hpet->handle = 0x00; + ivhd_hpet->source_dev_id = PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC); + ivhd_hpet->variety = IVHD_SPECIAL_DEV_HPET; + current += sizeof(ivrs_ivhd_special_t); + + return current; +} + +static unsigned long ivhd_describe_f0_device(unsigned long current, uint16_t dev_id, uint8_t datasetting) +{ + /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ + current = ALIGN_UP(current, 8); + ivrs_ivhd_f0_entry_t *ivhd_f0 = (ivrs_ivhd_f0_entry_t *) current; + + ivhd_f0->type = IVHD_DEV_VARIABLE; + ivhd_f0->dev_id = dev_id; + ivhd_f0->dte_setting = datasetting; + ivhd_f0->hardware_id.id_byte_0 = 'A'; + ivhd_f0->hardware_id.id_byte_1 = 'M'; + ivhd_f0->hardware_id.id_byte_2 = 'D'; + ivhd_f0->hardware_id.id_byte_3 = 'I'; + ivhd_f0->hardware_id.id_byte_4 = '0'; + ivhd_f0->hardware_id.id_byte_5 = '0'; + ivhd_f0->hardware_id.id_byte_6 = '4'; + ivhd_f0->hardware_id.id_byte_7 = '0'; + + ivhd_f0->compatible_id.id_byte_0 = 0; + ivhd_f0->compatible_id.id_byte_1 = 0; + ivhd_f0->compatible_id.id_byte_2 = 0; + ivhd_f0->compatible_id.id_byte_3 = 0; + ivhd_f0->compatible_id.id_byte_4 = 0; + ivhd_f0->compatible_id.id_byte_5 = 0; + ivhd_f0->compatible_id.id_byte_6 = 0; + ivhd_f0->compatible_id.id_byte_7 = 0; + + ivhd_f0->uuid_format = 0; + ivhd_f0->uuid_length = 0; + + current += sizeof(ivrs_ivhd_f0_entry_t); + return current; +} + +static unsigned long ivhd_dev_range(unsigned long current, uint16_t start_devid, + uint16_t end_devid, uint8_t setting) +{ + /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ + current = ALIGN_UP(current, 4); + ivrs_ivhd_generic_t *ivhd_range = (ivrs_ivhd_generic_t *)current; + + /* Create the start range IVHD entry */ + ivhd_range->type = IVHD_DEV_4_BYTE_START_RANGE; + ivhd_range->dev_id = start_devid; + ivhd_range->dte_setting = setting; + current += sizeof(ivrs_ivhd_generic_t); + + /* Create the end range IVHD entry */ + ivhd_range = (ivrs_ivhd_generic_t *)current; + ivhd_range->type = IVHD_DEV_4_BYTE_END_RANGE; + ivhd_range->dev_id = end_devid; + ivhd_range->dte_setting = setting; + current += sizeof(ivrs_ivhd_generic_t); + + return current; +} + +static unsigned long add_ivhd_dev_entry(struct device *parent, struct device *dev, + unsigned long *current, uint8_t type, uint8_t data) +{ + if (type == IVHD_DEV_4_BYTE_SELECT) { + /* 4-byte IVHD structures must be aligned to the 4-byte boundary. */ + *current = ALIGN_UP(*current, 4); + ivrs_ivhd_generic_t *ivhd_entry = (ivrs_ivhd_generic_t *)*current; + + ivhd_entry->type = type; + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dte_setting = data; + *current += sizeof(ivrs_ivhd_generic_t); + } else if (type == IVHD_DEV_8_BYTE_ALIAS_SELECT) { + /* 8-byte IVHD structures must be aligned to the 8-byte boundary. */ + *current = ALIGN_UP(*current, 8); + ivrs_ivhd_alias_t *ivhd_entry = (ivrs_ivhd_alias_t *)*current; + + ivhd_entry->type = type; + ivhd_entry->dev_id = dev->path.pci.devfn | (dev->bus->secondary << 8); + ivhd_entry->dte_setting = data; + ivhd_entry->reserved1 = 0; + ivhd_entry->reserved2 = 0; + ivhd_entry->source_dev_id = parent->path.pci.devfn | + (parent->bus->secondary << 8); + *current += sizeof(ivrs_ivhd_alias_t); + } + + return *current; +} + +static void ivrs_add_device_or_bridge(struct device *parent, struct device *dev, + unsigned long *current, uint16_t *ivhd_length) +{ + unsigned int header_type, is_pcie; + unsigned long current_backup; + + header_type = dev->hdr_type & 0x7f; + is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE); + + if (((header_type == PCI_HEADER_TYPE_NORMAL) || + (header_type == PCI_HEADER_TYPE_BRIDGE)) && is_pcie) { + /* Device or Bridge is PCIe */ + current_backup = *current; + add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_4_BYTE_SELECT, 0x0); + *ivhd_length += (*current - current_backup); + } else if ((header_type == PCI_HEADER_TYPE_NORMAL) && !is_pcie) { + /* Device is legacy PCI or PCI-X */ + current_backup = *current; + add_ivhd_dev_entry(parent, dev, current, IVHD_DEV_8_BYTE_ALIAS_SELECT, 0x0); + *ivhd_length += (*current - current_backup); + } +} + +static void add_ivhd_device_entries(struct device *parent, struct device *dev, + unsigned int depth, int linknum, int8_t *root_level, + unsigned long *current, uint16_t *ivhd_length) +{ + struct device *sibling; + struct bus *link; + + if (!root_level) { + root_level = malloc(sizeof(int8_t)); + *root_level = -1; + } + + if (dev->path.type == DEVICE_PATH_PCI) { + if ((dev->bus->secondary == 0x0) && + (dev->path.pci.devfn == 0x0)) + *root_level = depth; + + if ((*root_level != -1) && (dev->enabled)) { + if (depth != *root_level) + ivrs_add_device_or_bridge(parent, dev, current, ivhd_length); + } + } + + for (link = dev->link_list; link; link = link->next) + for (sibling = link->children; sibling; sibling = + sibling->sibling) + add_ivhd_device_entries(dev, sibling, depth + 1, depth, root_level, + current, ivhd_length); + + free(root_level); +} + +static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_t *ivrs) +{ + acpi_ivrs_ivhd40_t *ivhd_40; + unsigned long current_backup; + + /* + * These devices should be already found by previous function. + * Do not perform NULL checks. + */ + struct device *nb_dev = pcidev_on_root(0, 0); + struct device *iommu_dev = pcidev_on_root(0, 2); + + memset((void *)current, 0, sizeof(acpi_ivrs_ivhd40_t)); + ivhd_40 = (acpi_ivrs_ivhd40_t *)current; + + /* Enable EFR */ + ivhd_40->type = IVHD_BLOCK_TYPE_FULL__ACPI_HID; + /* For type 40h bits 6 and 7 are reserved */ + ivhd_40->flags = ivrs->ivhd.flags & 0x3f; + ivhd_40->length = sizeof(struct acpi_ivrs_ivhd_40); + /* BDF <bus>:00.2 */ + ivhd_40->device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivhd_40->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); + ivhd_40->iommu_base_low = ivrs->ivhd.iommu_base_low; + ivhd_40->iommu_base_high = ivrs->ivhd.iommu_base_high; + ivhd_40->pci_segment_group = 0x0000; + ivhd_40->iommu_info = ivrs->ivhd.iommu_info; + /* For type 40h bits 31:28 and 12:0 are reserved */ + ivhd_40->iommu_attributes = ivrs->ivhd.iommu_feature_info & 0xfffe000; + + if (pci_read_config32(iommu_dev, ivhd_40->capability_offset) & EFR_SUPPORT) { + ivhd_40->efr_reg_image_low = IOMMU_MMIO32(ivhd_40->iommu_base_low + 0x30); + ivhd_40->efr_reg_image_high = IOMMU_MMIO32(ivhd_40->iommu_base_low + 0x34); + } + + current += sizeof(acpi_ivrs_ivhd40_t); + + /* Now repeat all the device entries from type 10h */ + current_backup = current; + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + ivhd_40->length += (current - current_backup); + add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, &current, &ivhd_40->length); + + /* Describe HPET */ + current_backup = current; + current = ivhd_describe_hpet(current); + ivhd_40->length += (current - current_backup); + + /* Describe IOAPICs */ + current_backup = current; + current = acpi_fill_ivrs_ioapic(ivrs, current); + ivhd_40->length += (current - current_backup); + + /* Describe EMMC */ + current_backup = current; + current = ivhd_describe_f0_device( current, PCI_DEVFN(0x13, 1), 0xf7); + ivhd_40->length += (current - current_backup); + + return current; +} + +static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_t *ivrs) +{ + acpi_ivrs_ivhd11_t *ivhd_11; + ivhd11_iommu_attr_t *ivhd11_attr_ptr; + unsigned long current_backup; + + /* + * These devices should be already found by previous function. + * Do not perform NULL checks. + */ + struct device *nb_dev = pcidev_on_root(0, 0); + struct device *iommu_dev = pcidev_on_root(0, 2); + + /* + * In order to utilize all features, firmware should expose type 11h + * IVHD which supersedes the type 10h. + */ + memset((void *)current, 0, sizeof(acpi_ivrs_ivhd11_t)); + ivhd_11 = (acpi_ivrs_ivhd11_t *)current; + + /* Enable EFR */ + ivhd_11->type = IVHD_BLOCK_TYPE_FULL__FIXED; + /* For type 11h bits 6 and 7 are reserved */ + ivhd_11->flags = ivrs->ivhd.flags & 0x3f; + ivhd_11->length = sizeof(struct acpi_ivrs_ivhd_11); + /* BDF <bus>:00.2 */ + ivhd_11->device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivhd_11->capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); + ivhd_11->iommu_base_low = ivrs->ivhd.iommu_base_low; + ivhd_11->iommu_base_high = ivrs->ivhd.iommu_base_high; + ivhd_11->pci_segment_group = 0x0000; + ivhd_11->iommu_info = ivrs->ivhd.iommu_info; + ivhd11_attr_ptr = (ivhd11_iommu_attr_t*) &ivrs->ivhd.iommu_feature_info; + ivhd_11->iommu_attributes.perf_counters = ivhd11_attr_ptr->perf_counters; + ivhd_11->iommu_attributes.perf_counter_banks = ivhd11_attr_ptr->perf_counter_banks; + ivhd_11->iommu_attributes.msi_num_ppr = ivhd11_attr_ptr->msi_num_ppr; + + if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_SUPPORT) { + ivhd_11->efr_reg_image_low = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x30); + ivhd_11->efr_reg_image_high = IOMMU_MMIO32(ivhd_11->iommu_base_low + 0x34); + } + + current += sizeof(acpi_ivrs_ivhd11_t); + + /* Now repeat all the device entries from type 10h */ + current_backup = current; + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + ivhd_11->length += (current - current_backup); + add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, &current, &ivhd_11->length); + + /* Describe HPET */ + current_backup = current; + current = ivhd_describe_hpet(current); + ivhd_11->length += (current - current_backup); + + /* Describe IOAPICs */ + current_backup = current; + current = acpi_fill_ivrs_ioapic(ivrs, current); + ivhd_11->length += (current - current_backup); + + return acpi_fill_ivrs40(current, ivrs); +} + +static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current) +{ + unsigned long current_backup; + uint64_t mmio_x30_value; + uint64_t mmio_x18_value; + uint64_t mmio_x4000_value; + uint32_t capability_offset_0; + uint32_t capability_offset_10; + + struct device *iommu_dev; + struct device *nb_dev; + + nb_dev = pcidev_on_root(0, 0); + if (!nb_dev) { + printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__); + printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__); + + return (unsigned long)ivrs; + } + + iommu_dev = pcidev_on_root(0, 2); + if (!iommu_dev) { + printk(BIOS_WARNING, "%s: IOMMU device not found\n", __func__); + + return (unsigned long)ivrs; + } + + if (ivrs != NULL) { + ivrs->ivhd.type = IVHD_BLOCK_TYPE_LEGACY__FIXED; + ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd); + + /* BDF <bus>:00.2 */ + ivrs->ivhd.device_id = 0x02 | (nb_dev->bus->secondary << 8); + ivrs->ivhd.capability_offset = pci_find_capability(iommu_dev, IOMMU_CAP_ID); + ivrs->ivhd.iommu_base_low = pci_read_config32(iommu_dev, 0x44) & 0xffffc000; + ivrs->ivhd.iommu_base_high = pci_read_config32(iommu_dev, 0x48); + + capability_offset_0 = pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset) ; + capability_offset_10 = pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset + 0x10) ; + mmio_x18_value= IOMMU_MMIO64(ivrs->ivhd.iommu_base_low + 0x18); + mmio_x30_value = IOMMU_MMIO64(ivrs->ivhd.iommu_base_low + 0x30); + mmio_x4000_value = IOMMU_MMIO64(ivrs->ivhd.iommu_base_low + 0x4000); + + ivrs->ivhd.flags |= ((mmio_x30_value & MMIO_0X30_PPR_SUP) ? BIT(7) : 0); + ivrs->ivhd.flags |= ((mmio_x30_value & MMIO_0X30_PRE_F_SUP) ? BIT(6) : 0); + ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_0X18_COHERENT) ? BIT(5) : 0); + ivrs->ivhd.flags |= ((capability_offset_0 & CAP_OFFSET_0_IOTLB_SP) ? BIT(4) : 0); + ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_0X18_ISOC) ? BIT(3) : 0); + ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_0X18_RES_PASS_PW) ? BIT(2) : 0); + ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_0X18_PASS_PW) ? BIT(1) : 0); + ivrs->ivhd.flags |= ((mmio_x18_value & MMIO_0X18_HT_TUN_EN) ? BIT(0) : 0); + + ivrs->ivhd.pci_segment_group = 0x0000; + + ivrs->ivhd.iommu_info = pci_read_config16(iommu_dev, ivrs->ivhd.capability_offset + 0x10) & 0x1F; + ivrs->ivhd.iommu_info |= (pci_read_config16(iommu_dev, ivrs->ivhd.capability_offset + 0xC) &0x1F) << IOMMU_INFO_UNIT_ID_SHIFT ; + + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_0X30_HATS) ? (mmio_x30_value & MMIO_0X30_HATS) << IOMMU_FEATURE_HATS_SHIFT : 0); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_0X30_GATS) ? (mmio_x30_value & MMIO_0X30_GATS) << IOMMU_FEATURE_GATS_SHIFT : 0); + ivrs->ivhd.iommu_feature_info |= ((capability_offset_10 & CAP_OFFSET_0X10_MSI_NUM_PPR) ? ((capability_offset_10 & CAP_OFFSET_0X10_MSI_NUM_PPR)) >> IOMMU_FEATURE_MSI_NUM_PPR_SHIFT:0) ; + ivrs->ivhd.iommu_feature_info |= (mmio_x4000_value & MMIO_0X4000_N_COUNTER_BANKS) << IOMMU_FEATURE_PN_BANKS_SHIFT; + ivrs->ivhd.iommu_feature_info |= (mmio_x4000_value & MMIO_0X4000_N_COUNTER) << IOMMU_FEATURE_PN_COUNTERS_SHIFT; + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_0X30_PAS_MAX) ? (mmio_x30_value & MMIO_0X30_PAS_MAX) >>24 : 0); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_0X30_HE_SUP) ? IOMMU_FEATURE_HE_SUP : 0); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_0X30_GA_SUP) ? IOMMU_FEATURE_GA_SUP : 0); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_0X30_IA_SUP) ? IOMMU_FEATURE_IA_SUP : 0); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_0X30_GLX_SUP) ? (mmio_x30_value & MMIO_0X30_GLX_SUP) >> 11 : 0); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_0X30_GT_SUP) ? IOMMU_FEATURE_GT_SUP : 0); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_0X30_NX_SUP) ? IOMMU_FEATURE_NX_SUP : 0); + ivrs->ivhd.iommu_feature_info |= ((mmio_x30_value & MMIO_0X30_XT_SUP) ? IOMMU_FEATURE_XT_SUP : 0); + + /* Enable EFR if supported */ + ivrs->iv_info = pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset + 0x10) & 0x007fffe0; + if (pci_read_config32(iommu_dev, ivrs->ivhd.capability_offset) & EFR_SUPPORT) + ivrs->iv_info |= IVINFO_EFR_SUPPORTED; + + } else { + printk(BIOS_WARNING, "%s: AGESA returned NULL IVRS\n", __func__); + + return (unsigned long)ivrs; + } + + /* + * Add all possible PCI devices on bus 0 that can generate transactions + * processed by IOMMU. Start with device 00:01.0 + */ + current_backup = current; + current = ivhd_dev_range(current, PCI_DEVFN(1, 0), PCI_DEVFN(0x1f, 6), 0); + ivrs->ivhd.length += (current - current_backup); + add_ivhd_device_entries(NULL, all_devices, 0, -1, NULL, &current, &ivrs->ivhd.length); + + /* Describe HPET */ + current_backup = current; + current = ivhd_describe_hpet(current); + ivrs->ivhd.length += (current - current_backup); + + /* Describe IOAPICs */ + current_backup = current; + current = acpi_fill_ivrs_ioapic(ivrs, current); + ivrs->ivhd.length += (current - current_backup); + + /* If EFR is not supported, IVHD type 11h is reserved */ + if (!(ivrs->iv_info & IVINFO_EFR_SUPPORTED)) + return current; + + return acpi_fill_ivrs11(current, ivrs); +} + uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, acpi_rsdp_t *rsdp) { + acpi_ivrs_t *ivrs; + printk(BIOS_DEBUG, "Searching for AGESA FSP ACPI Tables\n"); current = add_agesa_acpi_table(AMD_FSP_ACPI_SSDT_HOB_GUID, "SSDT", rsdp, current); current = add_agesa_acpi_table(AMD_FSP_ACPI_CRAT_HOB_GUID, "CRAT", rsdp, current); current = add_agesa_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); - current = add_agesa_acpi_table(AMD_FSP_ACPI_IVRS_HOB_GUID, "IVRS", rsdp, current); + + /* IVRS */ + current = ALIGN(current, 8); + ivrs = (acpi_ivrs_t *) current; + acpi_create_ivrs(ivrs, acpi_fill_ivrs); + current += ivrs->header.length; + acpi_add_table(rsdp, ivrs); /* Add SRAT, MSCT, SLIT if needed in the future */ -- To view, visit https://review.coreboot.org/c/coreboot/+/43804 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I693f4399766c71c3ad53539634c65ba59afd0fe1 Gerrit-Change-Number: 43804 Gerrit-PatchSet: 1 Gerrit-Owner: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)amd.corp-partner.google.com> Gerrit-MessageType: newchange

5 49

Change in coreboot[master]: src/mainboard: Escape variable expansion in Kconfig
by Patrick Georgi (Code Review) 20 Aug '20

20 Aug '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44584 ) Change subject: src/mainboard: Escape variable expansion in Kconfig ...................................................................... src/mainboard: Escape variable expansion in Kconfig Kconfig 5.8 interprets $(...) itself using environment variables, which generally means that they expand to the empty string. \$(...) works with both our current and new Kconfig with the desired behavior (to pass it through unmodified). Change-Id: I726567eeb61d2035560152677d2b4548c1472be9 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M src/mainboard/google/dedede/Kconfig M src/mainboard/kontron/bsl6/Kconfig M src/mainboard/ocp/deltalake/Kconfig 3 files changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/44584/1 diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index d5057c71..d4c4d06 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -54,8 +54,8 @@ config FMDFILE string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-16MiB.fmd" if BOARD_ROMSIZE_KB_16384 + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/chromeos-dedede-32MiB.fmd" if BOARD_ROMSIZE_KB_32768 config MAINBOARD_DIR string diff --git a/src/mainboard/kontron/bsl6/Kconfig b/src/mainboard/kontron/bsl6/Kconfig index 2da8f44..437c5a3 100644 --- a/src/mainboard/kontron/bsl6/Kconfig +++ b/src/mainboard/kontron/bsl6/Kconfig @@ -40,7 +40,7 @@ config OVERRIDE_DEVICETREE string - default "variants/$(CONFIG_VARIANT_DIR)/overridetree.cb" + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" config CBFS_SIZE hex diff --git a/src/mainboard/ocp/deltalake/Kconfig b/src/mainboard/ocp/deltalake/Kconfig index fbdb067..b229c94 100644 --- a/src/mainboard/ocp/deltalake/Kconfig +++ b/src/mainboard/ocp/deltalake/Kconfig @@ -40,7 +40,7 @@ config FMDFILE string - default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/board.fmd" + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" # Deltalake is single socket server, the platform design has 1 DIMM per channel config DIMM_MAX -- To view, visit https://review.coreboot.org/c/coreboot/+/44584 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I726567eeb61d2035560152677d2b4548c1472be9 Gerrit-Change-Number: 44584 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: soc/intel/common/cse_lite: Perform a board specific reset
by Karthik Ramasubramanian (Code Review) 20 Aug '20

20 Aug '20

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44187 ) Change subject: soc/intel/common/cse_lite: Perform a board specific reset ...................................................................... soc/intel/common/cse_lite: Perform a board specific reset When ME jumps from RO to RW, global reset is initiated. When AP is reset as part of global reset, in some boards TPM initialization fails. This is because AP reset is not detected by TPM hosting an older firmware version. To signal TPMs running older firmware version about AP reset, a modified reset sequence needs to be performed. Hence add support to perform board-specific reset sequence. BUG=b:162290856, b:162386991 TEST=Ensure that the device boots to OS with the board-specific reset sequence when ME jumps from RO to RW with an older and newer Cr50 firmware. Change-Id: I8663e7f25461e58e45766e2ac00d752bfa191d8b Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/common/block/include/intelblocks/cse.h 2 files changed, 13 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/44187/1 diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index a12f2d0..7e80e72 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -355,12 +355,21 @@ return true; } +__weak void cse_board_reset(void) +{ + /* Default weak implementation, does nothing. */ +} + /* Set the CSE's next boot partition and issues system reset */ static bool cse_set_and_boot_from_next_bp(enum boot_partition_id bp) { if (!cse_set_next_boot_partition(bp)) return false; + /* Allow the board to perform a reset for CSE RO<->RW jump */ + cse_board_reset(); + + /* If board does not perform the reset, then perform global_reset */ do_global_reset(); die("cse_lite: Failed to reset the system\n"); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index a1dc3d9..5466ba6 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -219,4 +219,8 @@ * currently selected partition. */ void cse_fw_sync(void *unused); + +/* Perform a board-specific reset sequence for CSE RO<->RW jump */ +void cse_board_reset(void); + #endif // SOC_INTEL_COMMON_CSE_H -- To view, visit https://review.coreboot.org/c/coreboot/+/44187 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8663e7f25461e58e45766e2ac00d752bfa191d8b Gerrit-Change-Number: 44187 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: newchange

7 20

Change in coreboot[master]: sb/intel/lynxpoint: Drop unneeded and rotten Kconfig option
by Angel Pons (Code Review) 20 Aug '20

20 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44547 ) Change subject: sb/intel/lynxpoint: Drop unneeded and rotten Kconfig option ...................................................................... sb/intel/lynxpoint: Drop unneeded and rotten Kconfig option Not selecting `ME_MBP_CLEAR_LATE` results in a build failure. Since both traditional and ULT platforms are known to be working, drop the option. Change-Id: I09ce27f812966800e36f6c0624c93759089faf45 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/Kconfig M src/southbridge/intel/lynxpoint/me_9.x.c 2 files changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/44547/1 diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig index 3071fae..c104cbb 100644 --- a/src/southbridge/intel/lynxpoint/Kconfig +++ b/src/southbridge/intel/lynxpoint/Kconfig @@ -51,15 +51,6 @@ If you set this option to y, the serial IRQ machine will be operated in continuous mode. -config ME_MBP_CLEAR_LATE - bool "Defer wait for ME MBP Cleared" - default y - help - If you set this option to y, the Management Engine driver - will defer waiting for the MBP Cleared indicator until the - finalize step. This can speed up boot time if the ME takes - a long time to indicate this status. - config FINALIZE_USB_ROUTE_XHCI bool "Route all ports to XHCI controller in finalize step" default y diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 12168de..f32ee5b 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -548,10 +548,8 @@ if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; -#if CONFIG(ME_MBP_CLEAR_LATE) /* Wait for ME MBP Cleared indicator */ intel_me_mbp_clear(PCH_ME_DEV); -#endif /* Make sure ME is in a mode that expects EOP */ reg32 = pci_read_config32(PCH_ME_DEV, PCI_ME_HFS); @@ -927,11 +925,6 @@ host.interrupt_generate = 1; write_host_csr(&host); -#if !CONFIG(ME_MBP_CLEAR_LATE) - /* Wait for the mbp_cleared indicator. */ - intel_me_mbp_clear(dev); -#endif - /* Dump out the MBP contents. */ if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) { printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", -- To view, visit https://review.coreboot.org/c/coreboot/+/44547 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I09ce27f812966800e36f6c0624c93759089faf45 Gerrit-Change-Number: 44547 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/asus/am1i-a/buildOpts.c: choose the 1600 MHz RAM frequency
by Mike Banon (Code Review) 20 Aug '20

20 Aug '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44462 ) Change subject: mb/asus/am1i-a/buildOpts.c: choose the 1600 MHz RAM frequency ...................................................................... mb/asus/am1i-a/buildOpts.c: choose the 1600 MHz RAM frequency Together with the "AMD_XMP" changes, now this board with Crucial BLT8G3D1869DT1TX0 sticks could run at 1600 MHz CL8 (8-8-9-23) speeds. Earlier only 1333 MHz CL9 (9-9-10-27) has been possible with coreboot. 1866 MHz CL9 is impossible on f16kb without northbridge overclocking. tRP in "CL-tRCD-tRP-tRAS" gets set 1 point higher by AGESA because of Errata 638. See more info in a BKDG for AMD Family 16h Models 00h-0Fh. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I7e9f5120421221043f9f9dfe143b51bfa61936be --- M src/mainboard/asus/am1i-a/buildOpts.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/44462/1 diff --git a/src/mainboard/asus/am1i-a/buildOpts.c b/src/mainboard/asus/am1i-a/buildOpts.c index fe0915b..d143cc3 100644 --- a/src/mainboard/asus/am1i-a/buildOpts.c +++ b/src/mainboard/asus/am1i-a/buildOpts.c @@ -40,7 +40,7 @@ #define BLDCFG_MEMORY_SODIMM_CAPABLE FALSE #define BLDCFG_MEMORY_ENABLE_BANK_INTERLEAVING FALSE #define BLDCFG_MEMORY_CHANNEL_INTERLEAVING FALSE -#define BLDCFG_MEMORY_CLOCK_SELECT DDR1333_FREQUENCY /* FIXME: Turtle RAM? */ +#define BLDCFG_MEMORY_CLOCK_SELECT DDR1600_FREQUENCY #define BLDCFG_IGNORE_SPD_CHECKSUM TRUE #define BLDCFG_ENABLE_ECC_FEATURE FALSE #define BLDCFG_ECC_SYNC_FLOOD FALSE -- To view, visit https://review.coreboot.org/c/coreboot/+/44462 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7e9f5120421221043f9f9dfe143b51bfa61936be Gerrit-Change-Number: 44462 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020