coreboot-gerrit August 2020

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Change in coreboot[master]: mb/asrock/b85m_pro4: Select PECI function on Super I/O
by Angel Pons (Code Review) 20 Aug '20

20 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44552 ) Change subject: mb/asrock/b85m_pro4: Select PECI function on Super I/O ...................................................................... mb/asrock/b85m_pro4: Select PECI function on Super I/O This allows the Super I/O to know how hot the CPU is. Change-Id: I9c91136c3bb5aae541bb7ac64bb62be36c3c0b5d Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/bootblock.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/44552/1 diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c index 0cedcd6..7314552 100644 --- a/src/mainboard/asrock/b85m_pro4/bootblock.c +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -54,6 +54,7 @@ pnp_write_config(GLOBAL_DEV, 0x24, 0x1c); pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2c, 0x80); pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); /* Power RAM in S3 and let the PCH handle power failure actions */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44552 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9c91136c3bb5aae541bb7ac64bb62be36c3c0b5d Gerrit-Change-Number: 44552 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: vc/amd/agesa/f16kb: raise the DDR3 UDIMM Freq limit 1333MHz values to...
by Mike Banon (Code Review) 20 Aug '20

20 Aug '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44461 ) Change subject: vc/amd/agesa/f16kb: raise the DDR3 UDIMM Freq limit 1333MHz values to 1600MHz ...................................................................... vc/amd/agesa/f16kb: raise the DDR3 UDIMM Freq limit 1333MHz values to 1600MHz AMD f16kb boards should be perfectly capable of working at 1600MHz RAM speeds even with two DDR3 UDIMM modules. These low 1333MHz limits aren't justified, should raise them to 1600MHz and let the memory training code to do the rest. Successfully tested on ASUS AM1I-A and two Crucial BLT8G3D1869DT1TX0 UDIMMs, together with the other related AMD_XMP changes which help to enable 1600MHz. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I2a9da4e594ab3dc38b5ba87520633cbd01c9ce01 --- M src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/44461/1 diff --git a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c index 7e9b64e..3bc99bf 100644 --- a/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c +++ b/src/vendorcode/amd/agesa/f16kb/Proc/Mem/Ps/KB/mpUkb3.c @@ -92,8 +92,8 @@ {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntU6L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -111,8 +111,8 @@ {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntMicroSrvU6L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, @@ -130,8 +130,8 @@ {{_2DIMM, 1, 1, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 1, 0, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, {{_2DIMM, 2, 2, 0, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 1, 1, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, - {{_2DIMM, 2, 0, 2, 0, DDR1333_FREQUENCY, DDR1333_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 1, 1, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, + {{_2DIMM, 2, 0, 2, 0, DDR1600_FREQUENCY, DDR1600_FREQUENCY, UNSUPPORTED_DDR_FREQUENCY}}, }; CONST PSC_TBL_ENTRY KBMaxFreqTblEntU4L = { {PSCFG_MAXFREQ, UDIMM_TYPE, _1DIMM + _2DIMM, {AMD_FAMILY_16_KB, AMD_F16_ALL}, PT_DONT_CARE, DDR3_TECHNOLOGY}, -- To view, visit https://review.coreboot.org/c/coreboot/+/44461 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2a9da4e594ab3dc38b5ba87520633cbd01c9ce01 Gerrit-Change-Number: 44461 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/dedede/var/magolor: Enable Audio
by Ren Kuo (Code Review) 20 Aug '20

20 Aug '20

Ren Kuo has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44525 ) Change subject: mb/google/dedede/var/magolor: Enable Audio ...................................................................... mb/google/dedede/var/magolor: Enable Audio 1. Enable HDA Pci device in devicetree 2. Enable I2C4 in devicetree and fill ACPI information 3. Pass correct IRQ GPIO for headset jack BUG=None BRANCH=None TEST=Audio playback and recording works on Magolor DUT. Signed-off-by: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Change-Id: I38e2ff9b4b89dccc4c538773d15fd67d20bc895e --- M src/mainboard/google/dedede/variants/magolor/overridetree.cb 1 file changed, 26 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/44525/1 diff --git a/src/mainboard/google/dedede/variants/magolor/overridetree.cb b/src/mainboard/google/dedede/variants/magolor/overridetree.cb index 404024b..9d6598a 100644 --- a/src/mainboard/google/dedede/variants/magolor/overridetree.cb +++ b/src/mainboard/google/dedede/variants/magolor/overridetree.cb @@ -37,6 +37,31 @@ }" device domain 0 on - device pci 15.0 on end + device pci 19.0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Realtek RT5682"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)" + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP L"" + register "uid" = "0" + device i2c 28 on end + end + chip drivers/i2c/generic + register "hid" = ""10EC1015"" + register "desc" = ""Realtek SPK AMP R"" + register "uid" = "1" + device i2c 29 on end + end + end + device pci 1f.3 on end # Intel HDA end end -- To view, visit https://review.coreboot.org/c/coreboot/+/44525 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I38e2ff9b4b89dccc4c538773d15fd67d20bc895e Gerrit-Change-Number: 44525 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: Revert "mainboard/google/coral: Add USB2 phy setting override for Ast...
by Ren Kuo (Code Review) 20 Aug '20

20 Aug '20

Hello build bot (Jenkins), Patrick Georgi, Tim Chen, Paul Menzel, Aaron Durbin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43082 to review the following change. Change subject: Revert "mainboard/google/coral: Add USB2 phy setting override for Astronaut" ...................................................................... Revert "mainboard/google/coral: Add USB2 phy setting override for Astronaut" This reverts commit 2f1b7aaa3ef69ff6c79bedc9025dcb437535cd16. Reason for revert: replace it with another cl Change-Id: I3a30971e3f456ca8d5c274ab9c326b7781c06125 --- M src/mainboard/google/reef/variants/coral/mainboard.c 1 file changed, 0 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/43082/1 diff --git a/src/mainboard/google/reef/variants/coral/mainboard.c b/src/mainboard/google/reef/variants/coral/mainboard.c index 853276e..805c153 100644 --- a/src/mainboard/google/reef/variants/coral/mainboard.c +++ b/src/mainboard/google/reef/variants/coral/mainboard.c @@ -21,12 +21,8 @@ #include <soc/intel/common/vbt.h> enum { - SKU_0_ASTRONAUT = 0, - SKU_1_ASTRONAUT = 1, SKU_2_SANTA = 2, SKU_3_SANTA = 3, - SKU_61_ASTRONAUT = 61, - SKU_62_ASTRONAUT = 62, SKU_160_NASHER = 160, SKU_161_NASHER = 161, SKU_162_NASHER = 162, @@ -64,21 +60,11 @@ sku_id = variant_board_sku(); switch (sku_id) { - case SKU_0_ASTRONAUT: - case SKU_1_ASTRONAUT: - cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7; - cfg->usb2eye[1].Usb20PerPortTxiSet = 2; - break; case SKU_2_SANTA: case SKU_3_SANTA: cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7; cfg->usb2eye[1].Usb20PerPortTxiSet = 2; break; - case SKU_61_ASTRONAUT: - case SKU_62_ASTRONAUT: - cfg->usb2eye[1].Usb20PerPortPeTxiSet = 7; - cfg->usb2eye[1].Usb20PerPortTxiSet = 5; - break; default: break; } -- To view, visit https://review.coreboot.org/c/coreboot/+/43082 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3a30971e3f456ca8d5c274ab9c326b7781c06125 Gerrit-Change-Number: 43082 Gerrit-PatchSet: 1 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mainboard/google/coral: Add USB2 phy setting override for Astronaut
by Ren Kuo (Code Review) 20 Aug '20

20 Aug '20

Ren Kuo has created a revert of this change. ( https://review.coreboot.org/c/coreboot/+/22135 ) Change subject: mainboard/google/coral: Add USB2 phy setting override for Astronaut ...................................................................... -- To view, visit https://review.coreboot.org/c/coreboot/+/22135 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icf5c9e5f4dae15630ec4d6ca6648cae78ca910c6 Gerrit-Change-Number: 22135 Gerrit-PatchSet: 3 Gerrit-Owner: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Assignee: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ren Kuo <ren.kuo(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Tim Chen <Tim-Chen(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: revert

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Change in coreboot[master]: lib: Add ASan support to ramstage on x86 arch
by Angel Pons (Code Review) 20 Aug '20

20 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42496 ) Change subject: lib: Add ASan support to ramstage on x86 arch ...................................................................... Patch Set 27: Code-Review+1 (1 comment) https://review.coreboot.org/c/coreboot/+/42496/27/src/lib/asan.c File src/lib/asan.c: https://review.coreboot.org/c/coreboot/+/42496/27/src/lib/asan.c@12 PS27, Line 12: * it under the terms of the GNU General Public License version 2 as > I copied this header verbatim from Linux's kasan code. […] I'd add a SPDX header, then this as a separate comment: /* * This file contains shadow memory manipulation and error * reporting code. Copied from Linux's kasan code. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/42496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Gerrit-Change-Number: 42496 Gerrit-PatchSet: 27 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Thu, 20 Aug 2020 08:50:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Georgi <pgeorgi(a)google.com> Comment-In-Reply-To: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-MessageType: comment

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Change in coreboot[master]: mb/amd/mandolin: select ACPI driver for internal memory mapped UARTs
by Felix Held (Code Review) 20 Aug '20

20 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44529 ) Change subject: mb/amd/mandolin: select ACPI driver for internal memory mapped UARTs ...................................................................... mb/amd/mandolin: select ACPI driver for internal memory mapped UARTs In order for Linux to find and use the SoC's integrated UARTs, they need to be exposed in ACPI. BUG=b:165020060 TEST=Linux detects the SoC's integrated UARTs. Change-Id: Iaa66657b88f62b2067c865c3e1945b7bdbf9be23 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/mainboard/amd/mandolin/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/44529/1 diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 0360e95..1d2fa5e 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -10,6 +10,7 @@ select BOARD_ROMSIZE_KB_8192 if BOARD_AMD_MANDOLIN select AZALIA_PLUGIN_SUPPORT select HAVE_ACPI_RESUME + select DRIVERS_UART_ACPI select PICASSO_CONSOLE_UART if !AMD_LPC_DEBUG_CARD config FMDFILE -- To view, visit https://review.coreboot.org/c/coreboot/+/44529 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iaa66657b88f62b2067c865c3e1945b7bdbf9be23 Gerrit-Change-Number: 44529 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/xeon_sp/cpx/Kconfig: Relocate 'select CACHE_MRC_SETTINGS'
by HAOUAS Elyes (Code Review) 20 Aug '20

20 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44548 ) Change subject: soc/intel/xeon_sp/cpx/Kconfig: Relocate 'select CACHE_MRC_SETTINGS' ...................................................................... soc/intel/xeon_sp/cpx/Kconfig: Relocate 'select CACHE_MRC_SETTINGS' This will remove the warning: "src/soc/intel/xeon_sp/cpx/Kconfig:79:warning: config symbol 'CPU_BCLK_MHZ' uses select, but is not boolean or tristate" Change-Id: I2cfaf347b638e3847caa167e7efda89e9202960a Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/intel/xeon_sp/cpx/Kconfig 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44548/1 diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig index dcbadf8..3d764fe 100644 --- a/src/soc/intel/xeon_sp/cpx/Kconfig +++ b/src/soc/intel/xeon_sp/cpx/Kconfig @@ -72,12 +72,12 @@ config SOC_INTEL_COMMON_BLOCK_P2SB def_bool y +select CACHE_MRC_SETTINGS + config CPU_BCLK_MHZ int default 100 -select CACHE_MRC_SETTINGS - # CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel # Default value is set to one socket, full config. config DIMM_MAX -- To view, visit https://review.coreboot.org/c/coreboot/+/44548 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cfaf347b638e3847caa167e7efda89e9202960a Gerrit-Change-Number: 44548 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: Add Bay Trail support
by Angel Pons (Code Review) 20 Aug '20

20 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/42359 ) Change subject: Add Bay Trail support ...................................................................... Patch Set 36: (1 comment) https://review.coreboot.org/c/libgfxinit/+/42359/34/common/valleyview/hw-gf… File common/valleyview/hw-gfx-gma-plls.adb: https://review.coreboot.org/c/libgfxinit/+/42359/34/common/valleyview/hw-gf… PS34, Line 421: elsif Target_Clock <= 340_000_000 then > Maximum is 300MHz, `VCO_Upper / P1_Lower / P2_Lower / 5`. I'll try to use a constant local -- To view, visit https://review.coreboot.org/c/libgfxinit/+/42359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If81b1268c69b64fa30384f629f1eb43bda15ef52 Gerrit-Change-Number: 42359 Gerrit-PatchSet: 36 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Name of user not set #1002789 Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 20 Aug 2020 07:54:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Nico Huber <nico.h(a)gmx.de> Gerrit-MessageType: comment

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Change in coreboot[master]: util/abuild: Avoid another git submodule invocation
by Patrick Georgi (Code Review) 20 Aug '20

20 Aug '20

Patrick Georgi has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44550 ) Change subject: util/abuild: Avoid another git submodule invocation ...................................................................... util/abuild: Avoid another git submodule invocation .xcompile is generated before the submodules handling, but there's no need for the submodules to be around, so skip here, too. Change-Id: I60205f65b124a09067de5ae50f066b5cf64733f2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- M util/abuild/abuild 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44550/1 diff --git a/util/abuild/abuild b/util/abuild/abuild index 903a569..f90e2b3 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -769,7 +769,7 @@ exit 1 fi -$MAKE -C"${ROOT}" .xcompile || exit 1 +$MAKE -C"${ROOT}" UPDATED_SUBMODULES=1 .xcompile || exit 1 customizing=$(echo "$customizing" | cut -c3-) if [ "$customizing" = "" ]; then -- To view, visit https://review.coreboot.org/c/coreboot/+/44550 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I60205f65b124a09067de5ae50f066b5cf64733f2 Gerrit-Change-Number: 44550 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020