coreboot-gerrit August 2020

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Change in coreboot[master]: src/ec: Add missing <{stddef,stdint}|types>
by HAOUAS Elyes (Code Review) 20 Aug '20

20 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43952 ) Change subject: src/ec: Add missing <{stddef,stdint}|types> ...................................................................... src/ec: Add missing <{stddef,stdint}|types> Include <types.h> when stddef, stdint and stdbool are needed. Change-Id: I6d8a5d839e9bee1dfdd00f84a403f543af51a382 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/ec/google/chromeec/crosec_proto.c M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec_i2c.c M src/ec/google/chromeec/ec_lpc.c M src/ec/google/chromeec/ec_spi.c M src/ec/google/chromeec/vboot_storage.c M src/ec/google/chromeec/vstore.c M src/ec/google/wilco/chip.c M src/ec/google/wilco/commands.c M src/ec/kontron/kempld/kempld_i2c.c M src/ec/lenovo/h8/panic.c M src/ec/lenovo/h8/sense.c 12 files changed, 17 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/43952/1 diff --git a/src/ec/google/chromeec/crosec_proto.c b/src/ec/google/chromeec/crosec_proto.c index e54ad7e..0355fe3 100644 --- a/src/ec/google/chromeec/crosec_proto.c +++ b/src/ec/google/chromeec/crosec_proto.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <console/console.h> +#include <stddef.h> #include <stdint.h> #include <string.h> diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index e66e3b1..7cf4300 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include <stdint.h> #include <string.h> #include <assert.h> #include <console/console.h> @@ -12,6 +11,7 @@ #include <security/vboot/vboot_common.h> #include <stdlib.h> #include <timer.h> +#include <types.h> #include "ec.h" diff --git a/src/ec/google/chromeec/ec_i2c.c b/src/ec/google/chromeec/ec_i2c.c index 68e3cf2..ed1440c 100644 --- a/src/ec/google/chromeec/ec_i2c.c +++ b/src/ec/google/chromeec/ec_i2c.c @@ -2,6 +2,7 @@ #include <console/console.h> #include <device/i2c_simple.h> +#include <stddef.h> #include <stdint.h> #include <string.h> diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 5306dcc..4ac07a5 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -6,6 +6,7 @@ #include <delay.h> #include <device/pnp.h> #include <ec/google/common/mec.h> +#include <stddef.h> #include <stdint.h> #include "chip.h" diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c index ecf1b42..58f88e8 100644 --- a/src/ec/google/chromeec/ec_spi.c +++ b/src/ec/google/chromeec/ec_spi.c @@ -5,6 +5,8 @@ #include "ec.h" #include "ec_commands.h" #include <spi-generic.h> +#include <stddef.h> +#include <stdint.h> #include <timer.h> static struct stopwatch cs_cooldown_sw; diff --git a/src/ec/google/chromeec/vboot_storage.c b/src/ec/google/chromeec/vboot_storage.c index 4bd2590..edda036 100644 --- a/src/ec/google/chromeec/vboot_storage.c +++ b/src/ec/google/chromeec/vboot_storage.c @@ -3,6 +3,8 @@ #include <assert.h> #include <console/console.h> #include <ec/google/chromeec/ec.h> +#include <stddef.h> +#include <stdint.h> #include <vendorcode/google/chromeos/chromeos.h> #define VBOOT_HASH_VSLOT 0 diff --git a/src/ec/google/chromeec/vstore.c b/src/ec/google/chromeec/vstore.c index 2a33a3f..8eb540e 100644 --- a/src/ec/google/chromeec/vstore.c +++ b/src/ec/google/chromeec/vstore.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <stddef.h> #include <stdint.h> #include <string.h> #include "ec.h" diff --git a/src/ec/google/wilco/chip.c b/src/ec/google/wilco/chip.c index dccaa23..6970d23 100644 --- a/src/ec/google/wilco/chip.c +++ b/src/ec/google/wilco/chip.c @@ -11,6 +11,7 @@ #include <ec/acpi/ec.h> #include <intelblocks/cpulib.h> #include <pc80/keyboard.h> +#include <stddef.h> #include <stdint.h> #include "commands.h" diff --git a/src/ec/google/wilco/commands.c b/src/ec/google/wilco/commands.c index 98b1efb..d596d74 100644 --- a/src/ec/google/wilco/commands.c +++ b/src/ec/google/wilco/commands.c @@ -2,8 +2,8 @@ #include <console/console.h> #include <ec/acpi/ec.h> -#include <stdint.h> #include <string.h> +#include <types.h> #include "ec.h" #include "commands.h" diff --git a/src/ec/kontron/kempld/kempld_i2c.c b/src/ec/kontron/kempld/kempld_i2c.c index 296cf76..a8385bc 100644 --- a/src/ec/kontron/kempld/kempld_i2c.c +++ b/src/ec/kontron/kempld/kempld_i2c.c @@ -10,6 +10,7 @@ #include <console/console.h> #include <device/device.h> #include <device/i2c_bus.h> +#include <stddef.h> #include <timer.h> #include <delay.h> diff --git a/src/ec/lenovo/h8/panic.c b/src/ec/lenovo/h8/panic.c index 1bd8d1b..5776f3b 100644 --- a/src/ec/lenovo/h8/panic.c +++ b/src/ec/lenovo/h8/panic.c @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ + #include <console/console.h> #include <ec/acpi/ec.h> +#include <stddef.h> +#include <stdint.h> #include "h8.h" diff --git a/src/ec/lenovo/h8/sense.c b/src/ec/lenovo/h8/sense.c index fc850fb..0740b14 100644 --- a/src/ec/lenovo/h8/sense.c +++ b/src/ec/lenovo/h8/sense.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <ec/acpi/ec.h> +#include <stddef.h> +#include <stdint.h> #include "h8.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/43952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d8a5d839e9bee1dfdd00f84a403f543af51a382 Gerrit-Change-Number: 43952 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/acpi: Add missing <stddef.h> and <stdint.h>
by HAOUAS Elyes (Code Review) 20 Aug '20

20 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43950 ) Change subject: src/acpi: Add missing <stddef.h> and <stdint.h> ...................................................................... src/acpi: Add missing <stddef.h> and <stdint.h> Change-Id: Ied71f41f5a725e89afe71667e3aaad0b4ca45826 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/acpi/acpi.c M src/acpi/acpigen.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/43950/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 7873c0f..6341929 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -23,6 +23,8 @@ #include <commonlib/helpers.h> #include <cpu/cpu.h> #include <cbfs.h> +#include <stddef.h> +#include <stdint.h> #include <version.h> #include <commonlib/sort.h> diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index a4a74f6..cc90016 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -19,6 +19,8 @@ #include <device/pci_def.h> #include <device/pci_type.h> #include <device/soundwire.h> +#include <stddef.h> +#include <stdint.h> static char *gencurrent; -- To view, visit https://review.coreboot.org/c/coreboot/+/43950 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ied71f41f5a725e89afe71667e3aaad0b4ca45826 Gerrit-Change-Number: 43950 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/security: Add missing <{stddef,stdint}|types>
by HAOUAS Elyes (Code Review) 20 Aug '20

20 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43946 ) Change subject: src/security: Add missing <{stddef,stdint}|types> ...................................................................... src/security: Add missing <{stddef,stdint}|types> Change-Id: If22d582891f869b04fee79983658ba5c5467d261 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/security/intel/stm/SmmStm.c M src/security/memory/memory_clear.c M src/security/tpm/tspi.h M src/security/tpm/tspi/crtm.c M src/security/tpm/tspi/log.c M src/security/tpm/tspi/tspi.c M src/security/tpm/tss/tcg-1.2/tss.c M src/security/tpm/tss/tcg-2.0/tss.c M src/security/tpm/tss/tcg-2.0/tss_marshaling.c M src/security/vboot/common.c M src/security/vboot/ec_sync.c M src/security/vboot/mrc_cache_hash_tpm.c M src/security/vboot/secdata_tpm.c M src/security/vboot/vboot_common.h M src/security/vboot/vboot_logic.c 15 files changed, 24 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/43946/1 diff --git a/src/security/intel/stm/SmmStm.c b/src/security/intel/stm/SmmStm.c index 7256401..07496e8 100644 --- a/src/security/intel/stm/SmmStm.c +++ b/src/security/intel/stm/SmmStm.c @@ -6,8 +6,8 @@ #include <cpu/x86/msr.h> #include <cpu/x86/cache.h> #include <security/intel/stm/SmmStm.h> -#include <stdbool.h> #include <string.h> +#include <types.h> #define TXT_EVTYPE_BASE 0x400 #define TXT_EVTYPE_STM_HASH (TXT_EVTYPE_BASE + 14) diff --git a/src/security/memory/memory_clear.c b/src/security/memory/memory_clear.c index 557125d..3f8db2f 100644 --- a/src/security/memory/memory_clear.c +++ b/src/security/memory/memory_clear.c @@ -20,6 +20,8 @@ #include <security/memory/memory.h> #include <cbmem.h> #include <acpi/acpi.h> +#include <stddef.h> +#include <stdint.h> /* Helper to find free space for memset_pae. */ static uintptr_t get_free_memory_range(struct memranges *mem, diff --git a/src/security/tpm/tspi.h b/src/security/tpm/tspi.h index a776a4d..92adaee 100644 --- a/src/security/tpm/tspi.h +++ b/src/security/tpm/tspi.h @@ -6,6 +6,8 @@ #include <security/tpm/tss.h> #include <commonlib/tcpa_log_serialized.h> #include <commonlib/region.h> +#include <stddef.h> +#include <stdint.h> #include <vb2_api.h> #define TPM_PCR_MAX_LEN 64 diff --git a/src/security/tpm/tspi/crtm.c b/src/security/tpm/tspi/crtm.c index f5c788c..463b07a 100644 --- a/src/security/tpm/tspi/crtm.c +++ b/src/security/tpm/tspi/crtm.c @@ -5,6 +5,7 @@ #include <cbfs.h> #include "crtm.h" #include <string.h> +#include <types.h> /* * This function sets the TCPA log namespace diff --git a/src/security/tpm/tspi/log.c b/src/security/tpm/tspi/log.c index 1d6f9ac..948648a 100644 --- a/src/security/tpm/tspi/log.c +++ b/src/security/tpm/tspi/log.c @@ -7,6 +7,8 @@ #include <symbols.h> #include <cbmem.h> #include <bootstate.h> +#include <stddef.h> +#include <stdint.h> #include <vb2_sha.h> static struct tcpa_table *tcpa_cbmem_init(void) diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 6ef0138..06eab0b 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -7,6 +7,8 @@ #include <security/tpm/tss.h> #include <assert.h> #include <security/vboot/misc.h> +#include <stddef.h> +#include <stdint.h> #include <vb2_api.h> #include <vb2_sha.h> diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index 30cd1cc..07e1b36 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -17,6 +17,8 @@ #include <security/tpm/tis.h> #include <vb2_api.h> #include <security/tpm/tss.h> +#include <stddef.h> +#include <stdint.h> #include "tss_internal.h" #include "tss_commands.h" diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 79d8eb9..95649a7 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -6,6 +6,7 @@ #include <vb2_api.h> #include <security/tpm/tis.h> #include <security/tpm/tss.h> +#include <types.h> #include "tss_structures.h" #include "tss_marshaling.h" diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index f31c7d0..a93a397 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -2,6 +2,8 @@ #include <commonlib/iobuf.h> #include <console/console.h> +#include <stddef.h> +#include <stdint.h> #include <string.h> #include "tss_marshaling.h" diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 0121f56..8354727 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -8,6 +8,7 @@ #include <security/vboot/misc.h> #include <security/vboot/symbols.h> #include <security/vboot/vboot_common.h> +#include <stddef.h> static struct vb2_context *vboot_ctx; diff --git a/src/security/vboot/ec_sync.c b/src/security/vboot/ec_sync.c index 97b8ed9..33d7b97 100644 --- a/src/security/vboot/ec_sync.c +++ b/src/security/vboot/ec_sync.c @@ -11,6 +11,7 @@ #include <security/vboot/vboot_common.h> #include <timer.h> #include <timestamp.h> +#include <types.h> #include <vb2_api.h> #include <vboot_api.h> /* for VbExDisplayScreen() and VbScreenData */ diff --git a/src/security/vboot/mrc_cache_hash_tpm.c b/src/security/vboot/mrc_cache_hash_tpm.c index bc500a2..c993fb0 100644 --- a/src/security/vboot/mrc_cache_hash_tpm.c +++ b/src/security/vboot/mrc_cache_hash_tpm.c @@ -7,6 +7,8 @@ #include <security/tpm/tss.h> #include <fsp/memory_init.h> #include <console/console.h> +#include <stddef.h> +#include <stdint.h> #include <string.h> void mrc_cache_update_hash(const uint8_t *data, size_t size) diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index 691d2c0..1a40e4f 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -10,6 +10,8 @@ #include <security/tpm/tspi.h> #include <security/tpm/tss.h> #include <security/tpm/tss/tcg-1.2/tss_structures.h> +#include <stddef.h> +#include <stdint.h> #include <vb2_api.h> #include <console/console.h> diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index f2cff65..e616e91 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -3,6 +3,7 @@ #define __VBOOT_VBOOT_COMMON_H__ #include <commonlib/region.h> +#include <stddef.h> #include <vb2_api.h> /* diff --git a/src/security/vboot/vboot_logic.c b/src/security/vboot/vboot_logic.c index c4c3b4b..bf6b0cf 100644 --- a/src/security/vboot/vboot_logic.c +++ b/src/security/vboot/vboot_logic.c @@ -9,6 +9,8 @@ #include <security/vboot/misc.h> #include <security/vboot/vbnv.h> #include <security/vboot/tpm_common.h> +#include <stddef.h> +#include <stdint.h> #include <string.h> #include <timestamp.h> #include <vb2_api.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/43946 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If22d582891f869b04fee79983658ba5c5467d261 Gerrit-Change-Number: 43946 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: src/soc/sifive: Add missing <{stddef,stdint}.h>
by HAOUAS Elyes (Code Review) 20 Aug '20

20 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43943 ) Change subject: src/soc/sifive: Add missing <{stddef,stdint}.h> ...................................................................... src/soc/sifive: Add missing <{stddef,stdint}.h> Change-Id: I07110ad3b8d8376fc23eea0a512ba469f8f7213e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/soc/sifive/fu540/clock.c M src/soc/sifive/fu540/sdram.c M src/soc/sifive/fu540/spi.c 3 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/43943/1 diff --git a/src/soc/sifive/fu540/clock.c b/src/soc/sifive/fu540/clock.c index 9b21532..90b380e 100644 --- a/src/soc/sifive/fu540/clock.c +++ b/src/soc/sifive/fu540/clock.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <soc/clock.h> #include <soc/addressmap.h> +#include <stddef.h> #include <stdint.h> // 33.33 Mhz after reset diff --git a/src/soc/sifive/fu540/sdram.c b/src/soc/sifive/fu540/sdram.c index 3f2f498..dd370b2 100644 --- a/src/soc/sifive/fu540/sdram.c +++ b/src/soc/sifive/fu540/sdram.c @@ -1,5 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <stddef.h> +#include <stdint.h> #include <soc/sdram.h> #include <soc/addressmap.h> diff --git a/src/soc/sifive/fu540/spi.c b/src/soc/sifive/fu540/spi.c index d877452..50a9849 100644 --- a/src/soc/sifive/fu540/spi.c +++ b/src/soc/sifive/fu540/spi.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/mmio.h> +#include <stddef.h> +#include <stdint.h> #include <soc/spi.h> #include <soc/clock.h> #include <soc/addressmap.h> -- To view, visit https://review.coreboot.org/c/coreboot/+/43943 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I07110ad3b8d8376fc23eea0a512ba469f8f7213e Gerrit-Change-Number: 43943 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2295
by Aamir Bohra (Code Review) 20 Aug '20

20 Aug '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44415 ) Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2295 ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I569987427cccefc1c5015bdabb10b41f29f2624a Gerrit-Change-Number: 44415 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 20 Aug 2020 03:28:45 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Select PLATFORM_USES_FSP2_2
by Aamir Bohra (Code Review) 20 Aug '20

20 Aug '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43815 ) Change subject: soc/intel/jasperlake: Select PLATFORM_USES_FSP2_2 ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/43815 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia606ec26da93242ecdd602a9b3badbece5dcd034 Gerrit-Change-Number: 43815 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 20 Aug 2020 03:28:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/jasperlake: Disable multiphase SI init
by Aamir Bohra (Code Review) 20 Aug '20

20 Aug '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43816 ) Change subject: soc/intel/jasperlake: Disable multiphase SI init ...................................................................... Patch Set 9: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/43816 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2d591b46c403e68ff0b41ac8f87c742ae774111e Gerrit-Change-Number: 43816 Gerrit-PatchSet: 9 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 20 Aug 2020 03:27:49 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: mb/google/zork/baseboard: Remove unused reference
by Matt Papageorge (Code Review) 20 Aug '20

20 Aug '20

Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44556 ) Change subject: mb/google/zork/baseboard: Remove unused reference ...................................................................... mb/google/zork/baseboard: Remove unused reference Remove references to clk_pm_support which is currently ignored by Picasso AGESA FSP. BUG=b:161218965,b:162423378 TEST=Build test Trembyle and Dali, boot to ChromeOS 5 times each Change-Id: Ic5d6abc56821863b68e45c11763f00d2b6410983 Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> --- M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c 2 files changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/44556/1 diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c index c6e63ad..4be866d 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c @@ -27,7 +27,6 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ2, - .clk_pm_support = true, }, { // WLAN @@ -42,7 +41,6 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, - .clk_pm_support = true, }, { // SD Reader diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c index 26a5d33..49d8ade 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c @@ -46,7 +46,6 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, - .clk_pm_support = true, }, { // SD Reader @@ -78,7 +77,6 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ4, - .clk_pm_support = true, }, { // WLAN @@ -93,7 +91,6 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, - .clk_pm_support = true, }, { // SD Reader -- To view, visit https://review.coreboot.org/c/coreboot/+/44556 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic5d6abc56821863b68e45c11763f00d2b6410983 Gerrit-Change-Number: 44556 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths
by Wonkyu Kim (Code Review) 19 Aug '20

19 Aug '20

Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44557 ) Change subject: soc/intel/tigerlake: Add FSP UPDs for minimum assertion widths ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44557 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8180d95a2185c3786334e10613f47e77b7bc9d5f Gerrit-Change-Number: 44557 Gerrit-PatchSet: 1 Gerrit-Owner: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Raj Astekar <raj.astekar(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Aug 2020 23:55:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/fsp/picasso: update pci descriptor comments
by Matt Papageorge (Code Review) 19 Aug '20

19 Aug '20

Matt Papageorge has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44554 ) Change subject: vc/amd/fsp/picasso: update pci descriptor comments ...................................................................... vc/amd/fsp/picasso: update pci descriptor comments Update fsp_dxio_descriptor comments to be more comprehensive of the currently available data fields. Most of these are not currently utilized with Zork but may be in future projects. BUG=b:161218965 TEST=Build test Trembyle Change-Id: I8eb79fa7807dcf5b28b7b0ec60953ef857d51972 Signed-off-by: Matt Papageorge <matthewpapa07(a)gmail.com> --- M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c M src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c M src/vendorcode/amd/fsp/picasso/platform_descriptors.h 3 files changed, 26 insertions(+), 23 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/44554/1 diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c index c6e63ad..4be866d 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_dalboz.c @@ -27,7 +27,6 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ2, - .clk_pm_support = true, }, { // WLAN @@ -42,7 +41,6 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, - .clk_pm_support = true, }, { // SD Reader diff --git a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c index 26a5d33..49d8ade 100644 --- a/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/fsps_baseboard_trembyle.c @@ -46,7 +46,6 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, - .clk_pm_support = true, }, { // SD Reader @@ -78,7 +77,6 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ4, - .clk_pm_support = true, }, { // WLAN @@ -93,7 +91,6 @@ .link_aspm_L1_2 = true, .turn_off_unused_lanes = true, .clk_req = CLK_REQ0, - .clk_pm_support = true, }, { // SD Reader diff --git a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h index d5977ef..08c1990 100644 --- a/src/vendorcode/amd/fsp/picasso/platform_descriptors.h +++ b/src/vendorcode/amd/fsp/picasso/platform_descriptors.h @@ -28,6 +28,14 @@ GEN_INVALID // Max Gen for boundary check } dxio_link_speed_cap; +/* Upstream Auto Speed Change Allowed */ +typedef enum { + SPDC_DEFAULT = 0, + SPDC_DISBLED, + SPDC_ENABLED, + SPDC_INVALID +} dxio_upstream_auto_speed_change; + /* SATA ChannelType initialization */ typedef enum { SATA_CHANNEL_OTHER = 0, // Default Channel Type @@ -150,31 +158,31 @@ * GPP[3:2] | [5:4] | PCIe */ typedef struct __packed { - uint8_t engine_type; + uint8_t engine_type; // Descriptor type, see dxio_engine_type uint8_t start_logical_lane; // Start lane of the pci device uint8_t end_logical_lane; // End lane of the pci device - uint8_t gpio_group_id; // FCH reset number. 0 is global reset + uint8_t gpio_group_id; // Currently unused by FSP uint32_t port_present :1; // Should be TRUE if train link uint32_t reserved_3 :7; uint32_t device_number :5; // Desired root port device number uint32_t function_number :3; // Desired root port function number - uint32_t link_speed_capability :2; - uint32_t auto_spd_change :2; - uint32_t eq_preset :4; - uint32_t link_aspm :2; - uint32_t link_aspm_L1_1 :1; - uint32_t link_aspm_L1_2 :1; - uint32_t clk_req :4; - uint8_t link_hotplug; - uint8_t slot_power_limit; - uint32_t slot_power_limit_scale :2; + uint32_t link_speed_capability :2; // See dxio_link_speed_cap + uint32_t auto_spd_change :2; // See dxio_upstream_auto_speed_change + uint32_t eq_preset :4; // Gen3 equalization preset + uint32_t link_aspm :2; // See dxio_aspm_type + uint32_t link_aspm_L1_1 :1; // Set to 1 if link should be L1.1 capable, otherwise 0 + uint32_t link_aspm_L1_2 :1; // Set to 1 if link should be L1.2 capable, otherwise 0 + uint32_t clk_req :4; // See cpm_clk_req + uint8_t link_hotplug; // Currently unused by FSP + uint8_t slot_power_limit; // Currently unused by FSP + uint32_t slot_power_limit_scale :2; // Currently unused by FSP uint32_t reserved_4 :6; - uint32_t link_compliance_mode :1; - uint32_t link_safe_mode :1; - uint32_t sb_link :1; - uint32_t clk_pm_support :1; - uint32_t channel_type :3; - uint32_t turn_off_unused_lanes :1; + uint32_t link_compliance_mode :1; // Currently unused by FSP + uint32_t link_safe_mode :1; // Currently unused by FSP + uint32_t sb_link :1; // Currently unused by FSP + uint32_t clk_pm_support :1; // Currently unused by FSP + uint32_t channel_type :3; // See dxio_sata_channel_type + uint32_t turn_off_unused_lanes :1; // Power down lanes if device not present uint8_t reserved[4]; } fsp_dxio_descriptor; -- To view, visit https://review.coreboot.org/c/coreboot/+/44554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8eb79fa7807dcf5b28b7b0ec60953ef857d51972 Gerrit-Change-Number: 44554 Gerrit-PatchSet: 1 Gerrit-Owner: Matt Papageorge <matthewpapa07(a)gmail.com> Gerrit-MessageType: newchange

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