coreboot-gerrit August 2020

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Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Nico Huber (Code Review) 19 Aug '20

19 Aug '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... Patch Set 25: Code-Review+1 > Patch Set 25: > > > Patch Set 25: > > > > > Patch Set 25: Code-Review+1 > > > > > > LGTM. Are there any interdependencies with any of the other PCIe PM-related settings? > > > > Perhaps that "PcieRpAspm" doesn't disable L1 for a given root port? > > should coreboot automatically disable L1SS on a given port if PcieRpAspm is disabled for that port? Or are we just depending on the board config to be sane? pciexp_config_L1_sub_state() checks for the capabilities. If we tell FSP that it's not capable, the root port's capability regs should reflect that (I never tested it, though). One dependency for L1 substates is clock PM (i.e. a usable clockreq signal). There is no capability for that. It's currently only configurable globally via Kconfig (cf. CB:41696). -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 25 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 19 Aug 2020 15:48:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: [TEST]: mb/google/dedede: Reduce PL1 and PL2 values
by Sumeet R Pawnikar (Code Review) 19 Aug '20

19 Aug '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44053 ) Change subject: [TEST]: mb/google/dedede: Reduce PL1 and PL2 values ...................................................................... [TEST]: mb/google/dedede: Reduce PL1 and PL2 values This is test patch reduces PL1 and PL2 values. Change-Id: Ia32325f2db941bbeb1566635f2cf99760982d170 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/44053/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 7502489..86dee2a 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -148,14 +148,14 @@ register "dptf_enable" = "1" register "power_limits_config" = "{ - .tdp_pl1_override = 6, - .tdp_pl2_override = 20, + .tdp_pl1_override = 4, + .tdp_pl2_override = 15, }" # Enable processor thermal control register "Device4Enable" = "1" - register "tcc_offset" = "10" # TCC of 90C + register "tcc_offset" = "20" # TCC of 90C # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required @@ -181,13 +181,13 @@ register "controls.power_limits.pl1" = "{ .min_power = 3000, - .max_power = 6000, + .max_power = 4000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, .granularity = 200,}" register "controls.power_limits.pl2" = "{ .min_power = 6000, - .max_power = 20000, + .max_power = 15000, .time_window_min = 1 * MSECS_PER_SEC, .time_window_max = 1 * MSECS_PER_SEC, .granularity = 1000,}" -- To view, visit https://review.coreboot.org/c/coreboot/+/44053 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia32325f2db941bbeb1566635f2cf99760982d170 Gerrit-Change-Number: 44053 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: [TEST] mb/google/dedede: change TCC offset
by Sumeet R Pawnikar (Code Review) 19 Aug '20

19 Aug '20

Sumeet R Pawnikar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44133 ) Change subject: [TEST] mb/google/dedede: change TCC offset ...................................................................... [TEST] mb/google/dedede: change TCC offset Change TCC offset to prevent system shutdown during stress test. Change-Id: I265bec65fea904b6b8572f121d19aea4a890e334 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/mainboard/google/dedede/variants/baseboard/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/44133/1 diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index d0609ef..01b32f9 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -155,7 +155,7 @@ # Enable processor thermal control register "Device4Enable" = "1" - register "tcc_offset" = "10" # TCC of 90C + register "tcc_offset" = "20" # TCC of 90C # chipset_lockdown configuration # Use below format to override value in overridetree.cb if required -- To view, visit https://review.coreboot.org/c/coreboot/+/44133 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I265bec65fea904b6b8572f121d19aea4a890e334 Gerrit-Change-Number: 44133 Gerrit-PatchSet: 1 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: newchange

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Change in libgfxinit[master]: Add Bay Trail support
by Nico Huber (Code Review) 19 Aug '20

19 Aug '20

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/libgfxinit/+/42359 ) Change subject: Add Bay Trail support ...................................................................... Patch Set 36: (3 comments) https://review.coreboot.org/c/libgfxinit/+/42359/34/common/valleyview/hw-gf… File common/valleyview/hw-gfx-gma-plls.adb: https://review.coreboot.org/c/libgfxinit/+/42359/34/common/valleyview/hw-gf… PS34, Line 421: elsif Target_Clock <= 340_000_000 then Maximum is 300MHz, `VCO_Upper / P1_Lower / P2_Lower / 5`. https://review.coreboot.org/c/libgfxinit/+/42359/34/common/valleyview/hw-gf… PS34, Line 425: -- should be, but doesn't always have to be the same: Stale comment. We have different copies of the code for each refclock currently. https://review.coreboot.org/c/libgfxinit/+/42359/34/common/valleyview/hw-gf… PS34, Line 434: pragma Debug (Debug.Put_Int32 (340_000_000)); 300MHz -- To view, visit https://review.coreboot.org/c/libgfxinit/+/42359 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: libgfxinit Gerrit-Branch: master Gerrit-Change-Id: If81b1268c69b64fa30384f629f1eb43bda15ef52 Gerrit-Change-Number: 42359 Gerrit-PatchSet: 36 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-CC: Name of user not set #1002789 Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 19 Aug 2020 15:12:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge: Drop none reliable MCHBARx_{AND,OR} macros
by HAOUAS Elyes (Code Review) 19 Aug '20

19 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44506 ) Change subject: nb/intel/sandybridge: Drop none reliable MCHBARx_{AND,OR} macros ...................................................................... nb/intel/sandybridge: Drop none reliable MCHBARx_{AND,OR} macros Use of MCHBARx_AND_OR gives an error: overflow in conversion from 'int' to 'u16' {aka 'volatile short unsigned int'} changes value from '(int)*(volatile u16 *)((unsigned int)((int)i * 1024) + 4275127072) & -65536 | 26214' to '26214' [-Werror=overflow] Change-Id: I73f7f22dfa2440b3b44312e614a5d38ae1efcfc8 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/sandybridge/early_init.c M src/northbridge/intel/sandybridge/finalize.c M src/northbridge/intel/sandybridge/northbridge.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/sandybridge.h 5 files changed, 75 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/44506/1 diff --git a/src/northbridge/intel/sandybridge/early_init.c b/src/northbridge/intel/sandybridge/early_init.c index 2ee273c..af39ffe 100644 --- a/src/northbridge/intel/sandybridge/early_init.c +++ b/src/northbridge/intel/sandybridge/early_init.c @@ -105,18 +105,18 @@ pci_update_config8(PCI_DEV(0, 2, 0), MSAC, ~0x06, 0x02); /* Erratum workarounds */ - MCHBAR32_OR(SAPMCTL, (1 << 9) | (1 << 10)); + MCHBAR32(SAPMCTL) |= ((1 << 9) | (1 << 10)); /* Enable SA Clock Gating */ - MCHBAR32_OR(SAPMCTL, 1); + MCHBAR32(SAPMCTL) |= 1; /* GPU RC6 workaround for sighting 366252 */ - MCHBAR32_OR(SSKPD_HI, 1 << 31); + MCHBAR32(SSKPD_HI) |= (1 << 31); /* VLW (Virtual Legacy Wire?) */ - MCHBAR32_AND(0x6120, ~(1 << 0)); + MCHBAR32(0x6120) &= ~(1 << 0); - MCHBAR32_OR(INTRDIRCTL, (1 << 4) | (1 << 5)); + MCHBAR32(INTRDIRCTL) |= ((1 << 4) | (1 << 5)); } static void start_peg_link_training(void) diff --git a/src/northbridge/intel/sandybridge/finalize.c b/src/northbridge/intel/sandybridge/finalize.c index 26c5306..dfa5948 100644 --- a/src/northbridge/intel/sandybridge/finalize.c +++ b/src/northbridge/intel/sandybridge/finalize.c @@ -18,13 +18,13 @@ pci_or_config32(HOST_BRIDGE, TSEGMB, 1 << 0); pci_or_config32(HOST_BRIDGE, TOLUD, 1 << 0); - MCHBAR32_OR(PAVP_MSG, 1 << 0); /* PAVP */ - MCHBAR32_OR(SAPMCTL, 1 << 31); /* SA PM */ - MCHBAR32_OR(UMAGFXCTL, 1 << 0); /* UMA GFX */ - MCHBAR32_OR(VTDTRKLCK, 1 << 0); /* VTDTRK */ - MCHBAR32_OR(REQLIM, 1 << 31); - MCHBAR32_OR(DMIVCLIM, 1 << 31); - MCHBAR32_OR(CRDTLCK, 1 << 0); + MCHBAR32(PAVP_MSG) |= (1 << 0); /* PAVP */ + MCHBAR32(SAPMCTL) |= (1 << 31); /* SA PM */ + MCHBAR32(UMAGFXCTL) |= (1 << 0); /* UMA GFX */ + MCHBAR32(VTDTRKLCK) |= (1 << 0); /* VTDTRK */ + MCHBAR32(REQLIM) |= (1 << 31); + MCHBAR32(DMIVCLIM) |= (1 << 31); + MCHBAR32(CRDTLCK) |= (1 << 0); /* Memory Controller Lockdown */ MCHBAR8(MC_LOCK) = 0x8f; diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index e670c09..9a345a5 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -359,10 +359,10 @@ * * FIXME: Never clock gate on Ivy Bridge stepping A0! */ - MCHBAR32_OR(PEGCTL, 1); + MCHBAR32(PEGCTL) |= 1; printk(BIOS_DEBUG, "Disabling PEG IO clock.\n"); } else { - MCHBAR32_AND(PEGCTL, ~1); + MCHBAR32(PEGCTL) &= ~1; } } diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 3527c8e..2ff7ac8 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -178,7 +178,7 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel) { - u32 addr, stretch; + u32 addr, stretch, reg32; stretch = ctrl->ref_card_offset[channel]; /* @@ -190,11 +190,17 @@ stretch = 3; addr = SCHED_SECOND_CBIT_ch(channel); - MCHBAR32_AND_OR(addr, 0xffffc3ff, (stretch << 12) | (stretch << 10)); + reg32 = MCHBAR32(addr); + reg32 &= 0xffffc3ff; + reg32 |= ((stretch << 12) | (stretch << 10)); + MCHBAR32(addr) = reg32; printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); } else { addr = TC_OTHP_ch(channel); - MCHBAR32_AND_OR(addr, 0xfff0ffff, (stretch << 16) | (stretch << 18)); + reg32 = MCHBAR32(addr); + reg32 &= 0xfff0ffff; + reg32 |= ((stretch << 16) | (stretch << 18)); + MCHBAR32(addr) = reg32; printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); } } @@ -254,7 +260,7 @@ MCHBAR32(TC_DTP_ch(channel)) = reg; } - MCHBAR32_OR(addr, 0x00020000); + MCHBAR32(addr) |= 0x00020000; dram_odt_stretch(ctrl, channel); @@ -271,7 +277,7 @@ printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); MCHBAR32(TC_RFTP_ch(channel)) = reg; - MCHBAR32_OR(TC_RFP_ch(channel), 0xff); + MCHBAR32(TC_RFP_ch(channel)) |= 0xff; /* Self-refresh timing parameters */ reg = 0; @@ -652,19 +658,19 @@ MCHBAR32(MC_INIT_STATE_G) = reg; /* Assert DIMM reset signal */ - MCHBAR32_AND(MC_INIT_STATE_G, ~2); + MCHBAR32(MC_INIT_STATE_G) &= ~2; /* Wait 200us */ udelay(200); /* Deassert DIMM reset signal */ - MCHBAR32_OR(MC_INIT_STATE_G, 2); + MCHBAR32(MC_INIT_STATE_G) |= 2; /* Wait 500us */ udelay(500); /* Enable DCLK */ - MCHBAR32_OR(MC_INIT_STATE_G, 4); + MCHBAR32(MC_INIT_STATE_G) |= 4; /* XXX Wait 20ns */ udelay(1); @@ -957,10 +963,10 @@ } /* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 8); + MCHBAR32(MC_INIT_STATE_G) |= 8; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x200000); + MCHBAR32(SCHED_CBIT_ch(channel)) &= ~0x200000; wait_for_iosav(channel); @@ -2637,15 +2643,15 @@ int err; FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x8000000); + MCHBAR32(TC_RWP_ch(channel)) |= 0x8000000; FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + MCHBAR32(SCHED_CBIT_ch(channel)) |= 0x200000; } /* Refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~8); + MCHBAR32(MC_INIT_STATE_G) &= ~8; FOR_ALL_POPULATED_CHANNELS { write_op(ctrl, channel); } @@ -2678,10 +2684,10 @@ wait_for_iosav(channel); /* Refresh enable */ - MCHBAR32_OR(MC_INIT_STATE_G, 8); + MCHBAR32(MC_INIT_STATE_G) |= 8; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32_AND(SCHED_CBIT_ch(channel), ~0x00200000); + MCHBAR32(SCHED_CBIT_ch(channel)) &= ~0x00200000; MCHBAR32(IOSAV_STATUS_ch(channel)); wait_for_iosav(channel); @@ -2723,7 +2729,7 @@ printram("CPF\n"); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); + MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane) &= 0; } FOR_ALL_POPULATED_CHANNELS { @@ -2747,7 +2753,7 @@ program_timings(ctrl, channel); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - MCHBAR32_AND(IOSAV_By_BW_MASK_ch(channel, lane), 0); + MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) &= 0; } return 0; } @@ -2978,11 +2984,11 @@ iosav_run_once(channel); wait_for_iosav(channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x200000); + MCHBAR32(SCHED_CBIT_ch(channel)) |= 0x200000; } /* refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~8); + MCHBAR32(MC_INIT_STATE_G) &= ~8; FOR_ALL_POPULATED_CHANNELS { wait_for_iosav(channel); @@ -3964,6 +3970,7 @@ { const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f }; int i, pat; + u32 reg32; int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; @@ -3985,8 +3992,10 @@ FOR_ALL_POPULATED_CHANNELS { /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), - ~0x3f000000, rege3c_b24[i] << 24); + reg32 = MCHBAR32(GDCRCMDDEBUGMUXCFG_Cz_S(channel); + reg32 &= ~0x3f000000; + reg32 |= (rege3c_b24[i] << 24); + MCHBAR32(GDCRCMDDEBUGMUXCFG_Cz_S(channel)) = reg32; udelay(2); @@ -4053,7 +4062,7 @@ FOR_ALL_CHANNELS { /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); + MCHBAR32(GDCRCMDDEBUGMUXCFG_Cz_S(channel)) &= ~0x3f000000; udelay(2); } @@ -4423,7 +4432,7 @@ FOR_ALL_POPULATED_CHANNELS { /* Always drive command bus */ - MCHBAR32_OR(TC_RAP_ch(channel), 0x20000000); + MCHBAR32(TC_RAP_ch(channel)) |= 0x20000000; } udelay(1); @@ -4463,7 +4472,7 @@ int channel; FOR_ALL_POPULATED_CHANNELS { MCHBAR32(MC_INIT_STATE_ch(channel)) = 0x00001000 | ctrl->rankmap[channel]; - MCHBAR32_AND(TC_RAP_ch(channel), ~0x20000000); + MCHBAR32(TC_RAP_ch(channel)) &= ~0x20000000; } } @@ -4481,13 +4490,17 @@ int channel; int t1_cycles = 0, t1_ns = 0, t2_ns; int t3_ns; - u32 r32; + u32 r32, reg32; /* FIXME: This register only exists on Ivy Bridge */ MCHBAR32(WMM_READ_CONFIG) = 0x46; - FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_OTHP_ch(channel), 0xffffcfff, 0x1000); + FOR_ALL_CHANNELS { + reg32 = MCHBAR32(TC_OTHP_ch(channel)); + reg32 &= 0xffffcfff; + reg32 |= 0x1000; + MCHBAR32(TC_OTHP_ch(channel)) = reg32; + } if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -4522,14 +4535,21 @@ } MCHBAR32(MEM_TRML_ESTIMATION_CONFIG) = 0xca9171e5; - MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); - MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); + reg32 = MCHBAR32(MEM_TRML_THRESHOLDS_CONFIG); + reg32 &= ~0x00ffffff; + reg32 |= 0x00e4d5d0; + MCHBAR32(MEM_TRML_THRESHOLDS_CONFIG) = reg32; + MCHBAR32(MEM_TRML_INTERRUPT) &= ~0x1f; - FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); + FOR_ALL_CHANNELS { + reg32 = MCHBAR32(TC_RFP_ch(channel)); + reg32 &= ~(3 << 16); + reg32 |= (1 << 16); + MCHBAR32(TC_RFP_ch(channel)) = reg32; + } - MCHBAR32_OR(MC_INIT_STATE_G, 1); - MCHBAR32_OR(MC_INIT_STATE_G, 0x80); + MCHBAR32(MC_INIT_STATE_G) |= 1; + MCHBAR32(MC_INIT_STATE_G) |= 0x80; MCHBAR32(BANDTIMERS_SNB) = 0xfa; /* Find a populated channel */ @@ -4555,9 +4575,11 @@ /* The graphics driver will use these watermark values */ printk(BIOS_DEBUG, "t123: %d, %d, %d\n", t1_ns, t2_ns, t3_ns); - MCHBAR32_AND_OR(SSKPD, 0xC0C0C0C0, - ((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | - ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c); + reg32 = MCHBAR32(SSKPD); + reg32 &= 0xC0C0C0C0; + reg32 |= (((encode_wm(t1_ns) + encode_wm(t2_ns)) << 16) | (encode_wm(t1_ns) << 8) | + ((encode_wm(t3_ns) + encode_wm(t2_ns) + encode_wm(t1_ns)) << 24) | 0x0c)); + MCHBAR32(SSKPD) = reg32; } void restore_timings(ramctr_timing *ctrl) @@ -4586,11 +4608,11 @@ } FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 0x08000000); + MCHBAR32(TC_RWP_ch(channel)) |= 0x08000000; FOR_ALL_POPULATED_CHANNELS { udelay(1); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 0x00200000); + MCHBAR32(SCHED_CBIT_ch(channel)) |= 0x00200000; } printram("CPE\n"); @@ -4646,7 +4668,7 @@ MCHBAR32(GDCRTRAININGMOD_ch(0)) = 0; FOR_ALL_CHANNELS { - MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); + MCHBAR32(GDCRCMDDEBUGMUXCFG_Cz_S(channel)) &= ~0x3f000000; udelay(2); } } diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 72724a3..2fed3a2 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -67,15 +67,6 @@ #define MCHBAR8(x) (*((volatile u8 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR16(x) (*((volatile u16 *)(DEFAULT_MCHBAR + (x)))) #define MCHBAR32(x) (*((volatile u32 *)(DEFAULT_MCHBAR + (x)))) -#define MCHBAR8_AND(x, and) (MCHBAR8(x) = MCHBAR8(x) & (and)) -#define MCHBAR16_AND(x, and) (MCHBAR16(x) = MCHBAR16(x) & (and)) -#define MCHBAR32_AND(x, and) (MCHBAR32(x) = MCHBAR32(x) & (and)) -#define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) -#define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) -#define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* As there are many registers, define them on a separate file */ #include "mchbar_regs.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/44506 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I73f7f22dfa2440b3b44312e614a5d38ae1efcfc8 Gerrit-Change-Number: 44506 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: nb/intel/haswell: Drop none reliable MCHBARx_AND_OR macro
by HAOUAS Elyes (Code Review) 19 Aug '20

19 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44458 ) Change subject: nb/intel/haswell: Drop none reliable MCHBARx_AND_OR macro ...................................................................... nb/intel/haswell: Drop none reliable MCHBARx_AND_OR macro Change-Id: Ib32f91de325a2291801807cdb2a887e18f08f102 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/northbridge/intel/haswell/haswell.h 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/44458/1 diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 9a99c2a..db343fd 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -50,9 +50,6 @@ #define MCHBAR8_OR(x, or) (MCHBAR8(x) = MCHBAR8(x) | (or)) #define MCHBAR16_OR(x, or) (MCHBAR16(x) = MCHBAR16(x) | (or)) #define MCHBAR32_OR(x, or) (MCHBAR32(x) = MCHBAR32(x) | (or)) -#define MCHBAR8_AND_OR(x, and, or) (MCHBAR8(x) = (MCHBAR8(x) & (and)) | (or)) -#define MCHBAR16_AND_OR(x, and, or) (MCHBAR16(x) = (MCHBAR16(x) & (and)) | (or)) -#define MCHBAR32_AND_OR(x, and, or) (MCHBAR32(x) = (MCHBAR32(x) & (and)) | (or)) /* As there are many registers, define them on a separate file */ #include "mchbar_regs.h" -- To view, visit https://review.coreboot.org/c/coreboot/+/44458 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib32f91de325a2291801807cdb2a887e18f08f102 Gerrit-Change-Number: 44458 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in ...coreboot[master]: configs: Build test experimental x86_64 code
by Patrick Rudolph (Code Review) 19 Aug '20

19 Aug '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/31472 Change subject: configs: Build test experimental x86_64 code ...................................................................... configs: Build test experimental x86_64 code Add additional build config to test qemu-i440fx x86_64 code. Change-Id: I63f7a6e1602728e4d5ff67f9bd702efebe315c16 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- A configs/config.emulation_qemu_x86_i440fx_x86_64 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/31472/1 diff --git a/configs/config.emulation_qemu_x86_i440fx_x86_64 b/configs/config.emulation_qemu_x86_i440fx_x86_64 new file mode 100644 index 0000000..0ddb3f1 --- /dev/null +++ b/configs/config.emulation_qemu_x86_i440fx_x86_64 @@ -0,0 +1 @@ +CONFIG_CPU_QEMU_X86_64=y -- To view, visit https://review.coreboot.org/c/coreboot/+/31472 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I63f7a6e1602728e4d5ff67f9bd702efebe315c16 Gerrit-Change-Number: 31472 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F
by Felix Singer (Code Review) 19 Aug '20

19 Aug '20

Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37441 ) Change subject: mb/supermicro/x11-lga1151v2-series: Add support for X11SCH-F ...................................................................... Patch Set 65: Code-Review+1 (7 comments) https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/devicetree.cb: https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 10: device pci 01.0 on end Missing comment. https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 16: device pci 14.2 on end Missing comment. https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 19: device pci 16.0 on end # Management Engine Interface Add interface number https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 20: device pci 16.1 on end # Management Engine Interface Same https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 21: device pci 16.4 on end # Management Engine Interface Same https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 23: device pci 1c.1 on Missing comment. https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… File src/mainboard/supermicro/x11-lga1151v2-series/variants/x11sch-f/overridetree.cb: https://review.coreboot.org/c/coreboot/+/37441/65/src/mainboard/supermicro/… PS65, Line 114: device domain 0 on Please add root port numbers. -- To view, visit https://review.coreboot.org/c/coreboot/+/37441 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0ab1cb9462607b9af068bc2374508d99c60d0a30 Gerrit-Change-Number: 37441 Gerrit-PatchSet: 65 Gerrit-Owner: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Guido Beyer @ Prodrive Technologies <guido.beyer(a)prodrive-technologies.com> Gerrit-Reviewer: Justin van Son <justin.van.son(a)prodrive-technologies.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Michael Niewöhner Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stef van Os <stef.van.os(a)prodrive-technologies.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: wouter.eckhardt(a)prodrive-technologies.com Gerrit-CC: Jonas Löffelholz Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 19 Aug 2020 12:23:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: UDK2017/IntelFsp2Pkg: Add FSP*_ARCH_UPD.
by Ronak Kanabar (Code Review) 19 Aug '20

19 Aug '20

Ronak Kanabar has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44414 ) Change subject: UDK2017/IntelFsp2Pkg: Add FSP*_ARCH_UPD. ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/44414 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I21b0a72eae49976a0e36b4ac69c2efec8aaffabc Gerrit-Change-Number: 44414 Gerrit-PatchSet: 7 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2295
by Ronak Kanabar (Code Review) 19 Aug '20

19 Aug '20

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44415 ) Change subject: vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v2295 ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/44415/5//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/44415/5//COMMIT_MSG@15 PS5, Line 15: TBD > chrome-internal:3221772 […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/44415 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I569987427cccefc1c5015bdabb10b41f29f2624a Gerrit-Change-Number: 44415 Gerrit-PatchSet: 6 Gerrit-Owner: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Maulik V Vaghela <maulik.v.vaghela(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Wed, 19 Aug 2020 11:34:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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