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Change in coreboot[master]: soc/amd/picasso: log and print GPIO wake events
by Aaron Durbin (Code Review) 19 Aug '20

19 Aug '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44535 ) Change subject: soc/amd/picasso: log and print GPIO wake events ...................................................................... soc/amd/picasso: log and print GPIO wake events Capture the GPIO subsystem wake state and add events to the eventlog. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I7f10bf4599ea7928cc87b6b10ac11a7c30e58406 --- M src/soc/amd/picasso/include/soc/acpi.h M src/soc/amd/picasso/romstage.c M src/soc/amd/picasso/southbridge.c 3 files changed, 21 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/44535/1 diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 09f60d7..a21d347 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -4,6 +4,8 @@ #define __SOC_PICASSO_ACPI_H__ #include <acpi/acpi.h> +#include <amdblocks/acpi.h> +#include <amdblocks/gpio_banks.h> unsigned long southbridge_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp); @@ -13,4 +15,10 @@ const char *soc_acpi_name(const struct device *dev); +/* Object to capture state of chipset for logging events. */ +struct chipset_state { + struct acpi_pm_gpe_state gpe_state; + struct gpio_wake_state gpio_state; +}; + #endif /* __SOC_PICASSO_ACPI_H__ */ diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index 5a9f051..342fd46 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -11,22 +11,24 @@ #include <console/console.h> #include <program_loading.h> #include <elog.h> +#include <soc/acpi.h> #include <soc/memmap.h> #include <soc/mrc_cache.h> #include <types.h> #include "chip.h" #include <fsp/api.h> -static struct acpi_pm_gpe_state chipset_state; +static struct chipset_state chipset_state; static void fill_chipset_state(void) { - acpi_fill_pm_gpe_state(&chipset_state); + acpi_fill_pm_gpe_state(&chipset_state.gpe_state); + gpio_fill_wake_state(&chipset_state.gpio_state); } static void add_chipset_state_cbmem(int unused) { - struct acpi_pm_gpe_state *state; + struct chipset_state *state; state = cbmem_add(CBMEM_ID_POWER_STATE, sizeof(*state)); diff --git a/src/soc/amd/picasso/southbridge.c b/src/soc/amd/picasso/southbridge.c index df2d0d0..7db9ad8 100644 --- a/src/soc/amd/picasso/southbridge.c +++ b/src/soc/amd/picasso/southbridge.c @@ -18,6 +18,7 @@ #include <amdblocks/lpc.h> #include <amdblocks/acpi.h> #include <amdblocks/spi.h> +#include <soc/acpi.h> #include <soc/cpu.h> #include <soc/i2c.h> #include <soc/southbridge.h> @@ -275,7 +276,7 @@ static void set_nvs_sws(void *unused) { - struct acpi_pm_gpe_state *state; + struct chipset_state *state; struct global_nvs *gnvs; state = cbmem_find(CBMEM_ID_POWER_STATE); @@ -285,7 +286,7 @@ if (gnvs == NULL) return; - acpi_fill_gnvs(gnvs, state); + acpi_fill_gnvs(gnvs, &state->gpe_state); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, set_nvs_sws, NULL); @@ -309,14 +310,16 @@ void southbridge_init(void *chip_info) { - struct acpi_pm_gpe_state *state; + struct chipset_state *state; i2c_soc_init(); sb_init_acpi_ports(); state = cbmem_find(CBMEM_ID_POWER_STATE); - if (state) - acpi_pm_gpe_add_events_print_events(state); + if (state) { + acpi_pm_gpe_add_events_print_events(&state->gpe_state); + gpio_add_events(&state->gpio_state); + } acpi_clear_pm_gpe_status(); al2ahb_clock_gate(); -- To view, visit https://review.coreboot.org/c/coreboot/+/44535 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7f10bf4599ea7928cc87b6b10ac11a7c30e58406 Gerrit-Change-Number: 44535 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

3 2

Change in coreboot[master]: soc/amd/common: add gpio subsystem event reporting
by Aaron Durbin (Code Review) 19 Aug '20

19 Aug '20

Aaron Durbin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44534 ) Change subject: soc/amd/common: add gpio subsystem event reporting ...................................................................... soc/amd/common: add gpio subsystem event reporting In order to log gpio events for wake purposes the state of the gpio subsystem should be snapshotted. Add the ability to capture state of gpio subystem as well as saving up to 16 gpios that indicate their wake status. Likewise, provide the eventlog additions based on state. BUG=b:159947207 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I49fca56c87543aa8aad0eb7da5c5cb570c4349d5 --- M src/soc/amd/common/block/gpio_banks/gpio.c M src/soc/amd/common/block/include/amdblocks/gpio_banks.h 2 files changed, 83 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/44534/1 diff --git a/src/soc/amd/common/block/gpio_banks/gpio.c b/src/soc/amd/common/block/gpio_banks/gpio.c index 4f1b842..f8133a9 100644 --- a/src/soc/amd/common/block/gpio_banks/gpio.c +++ b/src/soc/amd/common/block/gpio_banks/gpio.c @@ -3,12 +3,14 @@ #include <device/mmio.h> #include <device/device.h> #include <console/console.h> +#include <elog.h> #include <gpio.h> #include <amdblocks/acpimmio.h> #include <amdblocks/gpio_banks.h> #include <soc/gpio.h> #include <soc/smi.h> #include <assert.h> +#include <string.h> static int get_gpio_gevent(uint8_t gpio, const struct soc_amd_event *table, size_t items) @@ -298,3 +300,67 @@ program_gpios(c, 1); } } + +static void check_and_add_wake_gpio(int begin, int end, struct gpio_wake_state *state) +{ + int i; + uint32_t reg; + + for (i = begin; i < end; i++) { + reg = gpio_read32(begin); + if (!(reg & GPIO_WAKE_STATUS)) + continue; + printk(BIOS_INFO, "GPIO %d woke system.\n", i); + if (state->num_valid_wake_gpios >= ARRAY_SIZE(state->wake_gpios)) + continue; + state->wake_gpios[state->num_valid_wake_gpios++] = i; + } +} + +static void check_gpios(uint32_t wake_stat, int bit_limit, int gpio_base, + struct gpio_wake_state *state) +{ + int i; + int gpio_end; + + for (i = 0; i < bit_limit; i++) { + if (!(wake_stat & (1U << i))) + continue; + gpio_base = i * 4; + gpio_end = gpio_base + 4; + /* There is no gpio 63. */ + if (gpio_base == 60) + gpio_end = 63; + check_and_add_wake_gpio(gpio_base, gpio_end, state); + } +} + +void gpio_fill_wake_state(struct gpio_wake_state *state) +{ + /* Turn the wake registers into "gpio" index to conform to existing API. */ + const uint8_t stat0 = GPIO_WAKE_STAT_0 / sizeof(uint32_t); + const uint8_t stat1 = GPIO_WAKE_STAT_1 / sizeof(uint32_t); + const uint8_t master_switch = GPIO_MASTER_SWITCH / sizeof(uint32_t); + + memset(state, 0, sizeof(*state)); + + state->master_switch = gpio_read32(master_switch); + state->wake_stat[0] = gpio_read32(stat0); + state->wake_stat[1] = gpio_read32(stat1); + + printk(BIOS_INFO, "GPIO Master Switch: 0x%08x, Wake Stat 0: 0x%08x, Wake Stat 1: 0x%08x\n", + state->master_switch, state->wake_stat[0], state->wake_stat[1]); + + check_gpios(state->wake_stat[0], 32, 0, state); + check_gpios(state->wake_stat[1], 14, 128, state); +} + +void gpio_add_events(const struct gpio_wake_state *state) +{ + int i; + int end; + + end = MIN(state->num_valid_wake_gpios, ARRAY_SIZE(state->wake_gpios)); + for (i = 0; i < end; i++) + elog_add_event_wake(ELOG_WAKE_SOURCE_GPIO, state->wake_gpios[i]); +} diff --git a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h index fdcd0f8..e020c92 100644 --- a/src/soc/amd/common/block/include/amdblocks/gpio_banks.h +++ b/src/soc/amd/common/block/include/amdblocks/gpio_banks.h @@ -20,6 +20,23 @@ #define GPIO_MASTER_SWITCH 0xFC #define GPIO_MASK_STS_EN BIT(28) #define GPIO_INTERRUPT_EN BIT(30) +#define GPIO_WAKE_EN BIT(31) + +#define GPIO_WAKE_STAT_0 0x2F0 +#define GPIO_WAKE_STAT_1 0x2F4 +struct gpio_wake_state { + uint32_t master_switch; + uint32_t wake_stat[2]; + /* Number of wake_gpio with a valid setting. */ + uint32_t num_valid_wake_gpios; + /* GPIO index number that caused a wake. */ + uint8_t wake_gpios[16]; +}; + +/* Fill gpio_wake_state object for future event reporting. */ +void gpio_fill_wake_state(struct gpio_wake_state *state); +/* Add gpio events to the eventlog. */ +void gpio_add_events(const struct gpio_wake_state *state); #define GPIO_PIN_IN (1 << 0) /* for byte access */ #define GPIO_PIN_OUT (1 << 6) /* for byte access */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44534 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I49fca56c87543aa8aad0eb7da5c5cb570c4349d5 Gerrit-Change-Number: 44534 Gerrit-PatchSet: 1 Gerrit-Owner: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

3 13

Change in coreboot[master]: soc/amd/picasso: Use cbfs to locate the amd firmware
by Martin Roth (Code Review) 19 Aug '20

19 Aug '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42831 ) Change subject: soc/amd/picasso: Use cbfs to locate the amd firmware ...................................................................... soc/amd/picasso: Use cbfs to locate the amd firmware Switch from hardcoded locations for the AMD firmware in the RW_A & RW_B regions to locating it with cbfs. BUG=b:154441227 TEST=None yet Signed-off-by: Martin Roth <martin(a)coreboot.org> Change-Id: I27b0593e0db7a9e6ba9b0633ac93b4d93954f002 --- M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/picasso/psp_verstage/psp_verstage.c M src/soc/amd/picasso/psp_verstage/psp_verstage.h 4 files changed, 41 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/42831/1 diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4d07af6..a2321e5 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -520,16 +520,6 @@ Add a space-delimited list of filenames that should only be in the RW-B section. -config PICASSO_FW_A_POSITION - hex - help - Location of the AMD firmware in the RW_A region - -config PICASSO_FW_B_POSITION - hex - help - Location of the AMD firmware in the RW_B region - endif # VBOOT_SLOTS_RW_AB && VBOOT_STARTS_BEFORE_BOOTBLOCK endif # SOC_AMD_PICASSO diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index 35bc1e7..29d1c42 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -497,12 +497,10 @@ ifeq ($(CONFIG_VBOOT_SLOTS_RW_AB)$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK),yy) cbfs-files-y += apu/amdfw_a apu/amdfw_a-file := $(obj)/amdfw_a.rom -apu/amdfw_a-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_A_POSITION)) apu/amdfw_a-type := raw cbfs-files-y += apu/amdfw_b apu/amdfw_b-file := $(obj)/amdfw_b.rom -apu/amdfw_b-position := $(call strip_quotes, $(CONFIG_PICASSO_FW_B_POSITION)) apu/amdfw_b-type := raw endif diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.c b/src/soc/amd/picasso/psp_verstage/psp_verstage.c index de41e4c..4470c63 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.c +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.c @@ -4,7 +4,10 @@ #include <bl_uapp/bl_syscall_public.h> #include <boot_device.h> +#include <cbfs.h> +#include <commonlib/region.h> #include <console/console.h> +#include <fmap.h> #include <security/vboot/misc.h> #include <security/vboot/symbols.h> #include <security/vboot/vboot_common.h> @@ -33,6 +36,21 @@ vboot_reboot(); } +static uintptr_t locate_amdfw(const char *name, struct region_device *rdev) +{ + uint32_t cbfs_type = CBFS_TYPE_RAW; + struct cbfsf fh; + + if (!region_device_sz(&(fh.data))) { + if (cbfs_locate_file_in_region(&fh, "COREBOOT", name, &cbfs_type)) { + printk(BIOS_ERR, "Error: AMD Firmware table could not be found.\n"); + return 0; + } + } + + return (uintptr_t)rdev_mmap_full(&fh.data); +} + /* * Tell the PSP where to load the rest of the firmware from */ @@ -41,6 +59,9 @@ struct psp_ef_table *ef_table; uint32_t psp_dir_addr, bios_dir_addr; uint32_t *psp_dir_in_spi, *bios_dir_in_spi; + const char *rname, *fname; + struct region_device rdev; + uintptr_t amdfw_location; /* Continue booting from RO */ if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) { @@ -49,14 +70,26 @@ } if (vboot_is_firmware_slot_a(ctx)) { - printk(BIOS_SPEW, "Using FMAP RW_A region.\n"); - ef_table = (struct psp_ef_table *)((CONFIG_PICASSO_FW_A_POSITION & - SPI_ADDR_MASK) + (uint32_t)boot_dev.base); + rname = "FW_MAIN_A"; + fname = "apu/amdfw_a"; } else { - printk(BIOS_SPEW, "Using FMAP RW_B region.\n"); - ef_table = (struct psp_ef_table *)((CONFIG_PICASSO_FW_B_POSITION & - SPI_ADDR_MASK) + (uint32_t)boot_dev.base); + rname = "FW_MAIN_B"; + fname = "apu/amdfw_a"; } + printk(BIOS_DEBUG, "Using FMAP %s region.\n", rname); + + if (fmap_locate_area_as_rdev(rname, &rdev)){ + printk(BIOS_ERR, "Error: Could not locate fmap region %s.\n", rname); + return POSTCODE_FMAP_REGION_MISSING; + } + + amdfw_location = locate_amdfw(fname, &rdev); + if (!amdfw_location) { + printk(BIOS_ERR, "Error: AMD Firmware table not found.\n"); + return POSTCODE_AMD_FW_MISSING; + } + ef_table = (struct psp_ef_table *)((amdfw_location & SPI_ADDR_MASK) + + (uint32_t)boot_dev.base); if (ef_table->signature != EMBEDDED_FW_SIGNATURE) { printk(BIOS_ERR, "Error: ROMSIG address is not correct.\n"); diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.h b/src/soc/amd/picasso/psp_verstage/psp_verstage.h index 6fe5c7a..2b1105a 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.h +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.h @@ -28,6 +28,8 @@ #define POSTCODE_PSP_COOKIE_MISMATCH_ERROR 0xC5 #define POSTCODE_BDT1_COOKIE_MISMATCH_ERROR 0xC6 #define POSTCODE_UPDATE_PSP_BIOS_DIR_ERROR 0xC7 +#define POSTCODE_FMAP_REGION_MISSING 0xC8 +#define POSTCODE_AMD_FW_MISSING 0xc9 #define POSTCODE_UNMAP_SPI_ROM 0xF0 #define POSTCODE_UNMAP_FCH_DEVICES 0xF1 -- To view, visit https://review.coreboot.org/c/coreboot/+/42831 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I27b0593e0db7a9e6ba9b0633ac93b4d93954f002 Gerrit-Change-Number: 42831 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

6 20

Change in coreboot[master]: soc/amd/picasso: Remove now unused #define
by Martin Roth (Code Review) 19 Aug '20

19 Aug '20

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44537 ) Change subject: soc/amd/picasso: Remove now unused #define ...................................................................... soc/amd/picasso: Remove now unused #define This #define wasn't removed when the tests were removed, so get rid of it now. BUG=None TEST=Build Signed-off-by: Martin Roth <martinroth(a)chromium.org> Change-Id: Ie0005b6ee97037bf3dfb80f0c2408d8bd9ee9633 --- M src/soc/amd/picasso/psp_verstage/psp_verstage.c 1 file changed, 0 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/44537/1 diff --git a/src/soc/amd/picasso/psp_verstage/psp_verstage.c b/src/soc/amd/picasso/psp_verstage/psp_verstage.c index bac0548..bea0688 100644 --- a/src/soc/amd/picasso/psp_verstage/psp_verstage.c +++ b/src/soc/amd/picasso/psp_verstage/psp_verstage.c @@ -12,8 +12,6 @@ #include <stdarg.h> #include <stdio.h> -#define RUN_PSP_SVC_TESTS 0 - extern char _bss_start, _bss_end; static struct mem_region_device boot_dev = MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); -- To view, visit https://review.coreboot.org/c/coreboot/+/44537 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie0005b6ee97037bf3dfb80f0c2408d8bd9ee9633 Gerrit-Change-Number: 44537 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/zork: remove unused asl files for dirinboz
by Kevin Chiu (Code Review) 19 Aug '20

19 Aug '20

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44514 to review the following change. Change subject: mb/google/zork: remove unused asl files for dirinboz ...................................................................... mb/google/zork: remove unused asl files for dirinboz BUG=b:161579679 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully Change-Id: I713ac3a47c2d47035affb32e6c604b9af23aa90e Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- D src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/audio.asl D src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/mainboard.asl D src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/sleep.asl 3 files changed, 0 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44514/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/audio.asl deleted file mode 100644 index 900e36f..0000000 --- a/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/audio.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/audio.asl> diff --git a/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/mainboard.asl deleted file mode 100644 index a1161ed..0000000 --- a/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/mainboard.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/mainboard.asl> diff --git a/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/sleep.asl b/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/sleep.asl deleted file mode 100644 index 8177a9d..0000000 --- a/src/mainboard/google/zork/variants/dirinboz/include/variant/acpi/sleep.asl +++ /dev/null @@ -1,3 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include <baseboard/acpi/sleep.asl> -- To view, visit https://review.coreboot.org/c/coreboot/+/44514 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I713ac3a47c2d47035affb32e6c604b9af23aa90e Gerrit-Change-Number: 44514 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/google/zork: config I2C2 freq to 400kHz for dirinboz TP/TS
by Kevin Chiu (Code Review) 19 Aug '20

19 Aug '20

Hello Kevin Chiu, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/44515 to review the following change. Change subject: mb/google/zork: config I2C2 freq to 400kHz for dirinboz TP/TS ...................................................................... mb/google/zork: config I2C2 freq to 400kHz for dirinboz TP/TS BUG=b:159597999,b:159597998 BRANCH=master TEST=1. emerge-zork coreboot chromeos-bootimage 2. power on proto board successfully 3. measure i2c freq by scope is 400kHz Change-Id: Icb27ff8a4960caaebc542ee4e507f1611da5a77e Signed-off-by: Kevin Chiu <kevin.chiu(a)quantatw.com> --- M src/mainboard/google/zork/variants/dirinboz/overridetree.cb 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/44515/1 diff --git a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb index 7645ba3..0667943 100644 --- a/src/mainboard/google/zork/variants/dirinboz/overridetree.cb +++ b/src/mainboard/google/zork/variants/dirinboz/overridetree.cb @@ -1,5 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-or-later - chip soc/amd/picasso # Start : OPN Performance Configuration @@ -18,10 +17,12 @@ # End : OPN Performance Configuration - # I2C2 for touchscreen and trackpad + # I2C2 for touchscreen and trackpad register "i2c[2]" = "{ .speed = I2C_SPEED_FAST, + .rise_time_ns = 18, /* 0 to 2.31 (3.3 * .7) */ + .fall_time_ns = 57, /* 2.31 to 0 */ }" # I2C3 for H1 -- To view, visit https://review.coreboot.org/c/coreboot/+/44515 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icb27ff8a4960caaebc542ee4e507f1611da5a77e Gerrit-Change-Number: 44515 Gerrit-PatchSet: 1 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Kevin Chiu <kevin.chiu(a)quanta.corp-partner.google.com> Gerrit-MessageType: newchange

4 5

Change in coreboot[master]: mb/google/volteer/halvor: Skip fw_config override on Halvor.
by Frank Wu (Code Review) 19 Aug '20

19 Aug '20

Frank Wu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44455 ) Change subject: mb/google/volteer/halvor: Skip fw_config override on Halvor. ...................................................................... mb/google/volteer/halvor: Skip fw_config override on Halvor. Volteer and Halvor share the same fw_config MAX98373_ALC5682I_I2S. However, the GPP_A23 is used as I2S1_SCLK on Volteer but HP_INT_L on Halvor. The GPP_A23 is overridden as I2S1_SCLK at last, so the detection of headset jack is not workable. The audio settings are included in halvor/gpio.c and skip the fw_config on Halvor to make the gpios correct. BUG=b:153680359, b:163382106 TEST=FW_NAME=halvor emerge-volteer coreboot chromeos-bootimage, then verify that headset jack detection is fine on Halvor. Signed-off-by: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Change-Id: Ie644ed2b95d0e355f91d92f0b3c4ce14cd4afa98 --- M src/mainboard/google/volteer/fw_config.c M src/mainboard/google/volteer/variants/halvor/include/variant/gpio.h 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/44455/1 diff --git a/src/mainboard/google/volteer/fw_config.c b/src/mainboard/google/volteer/fw_config.c index 61e20f4..21eb3e1b 100644 --- a/src/mainboard/google/volteer/fw_config.c +++ b/src/mainboard/google/volteer/fw_config.c @@ -4,6 +4,7 @@ #include <console/console.h> #include <fw_config.h> #include <gpio.h> +#include <variant/gpio.h> static const struct pad_config dmic_enable_pads[] = { PAD_CFG_NF(GPP_S4, NONE, DEEP, NF2), /* DMIC_CLK1 */ @@ -59,6 +60,9 @@ static void fw_config_handle(void *unused) { +#ifdef SKIP_FW_CONFIG_GPIO + return; +#endif if (fw_config_probe(FW_CONFIG(AUDIO, NONE))) { printk(BIOS_INFO, "Configure GPIOs for no audio.\n"); gpio_configure_pads(i2s_disable_pads, ARRAY_SIZE(i2s_disable_pads)); diff --git a/src/mainboard/google/volteer/variants/halvor/include/variant/gpio.h b/src/mainboard/google/volteer/variants/halvor/include/variant/gpio.h index fe512d8..ce32b3b 100644 --- a/src/mainboard/google/volteer/variants/halvor/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/halvor/include/variant/gpio.h @@ -5,6 +5,7 @@ #include <baseboard/gpio.h> +#define SKIP_FW_CONFIG_GPIO 1 #undef GPIO_EC_IN_RW /* EC in RW */ #define GPIO_EC_IN_RW GPP_F17 -- To view, visit https://review.coreboot.org/c/coreboot/+/44455 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie644ed2b95d0e355f91d92f0b3c4ce14cd4afa98 Gerrit-Change-Number: 44455 Gerrit-PatchSet: 1 Gerrit-Owner: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: crossgcc: Enable GCC to get asan shadow offset at runtime
by Harshit Sharma (Code Review) 18 Aug '20

18 Aug '20

Harshit Sharma has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42794 ) Change subject: crossgcc: Enable GCC to get asan shadow offset at runtime ...................................................................... Patch Set 21: > Patch Set 20: > > I'll put it in now, but we'll need an uprev to gcc 10 soon (see CB:42251). Can you take a > look at this? Sure. -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 21 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Tue, 18 Aug 2020 23:42:20 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: cse_lite: Move global reset after MRC writeback
by Nick Vaccaro (Code Review) 18 Aug '20

18 Aug '20

Nick Vaccaro has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44430 ) Change subject: cse_lite: Move global reset after MRC writeback ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44430 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia42d72fdec41f9792ab8f04205b20a55758a4235 Gerrit-Change-Number: 44430 Gerrit-PatchSet: 4 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Sridhar Siricilla <sridhar.siricilla(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Aug 2020 23:06:53 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake: Configure L1 substates for PCH root ports
by Matt DeVillier (Code Review) 18 Aug '20

18 Aug '20

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39538 ) Change subject: soc/intel/skylake: Configure L1 substates for PCH root ports ...................................................................... Patch Set 25: > Patch Set 25: > > > Patch Set 25: Code-Review+1 > > > > LGTM. Are there any interdependencies with any of the other PCIe PM-related settings? > > Perhaps that "PcieRpAspm" doesn't disable L1 for a given root port? should coreboot automatically disable L1SS on a given port if PcieRpAspm is disabled for that port? Or are we just depending on the board config to be sane? -- To view, visit https://review.coreboot.org/c/coreboot/+/39538 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36150858485715016158595c832c142b0582ddb8 Gerrit-Change-Number: 39538 Gerrit-PatchSet: 25 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 18 Aug 2020 21:38:24 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2020