coreboot-gerrit August 2020

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Change in coreboot[master]: xeon_sp/cpx: Enable ACPI P-state support
by Angel Pons (Code Review) 17 Aug '20

17 Aug '20

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44404 ) Change subject: xeon_sp/cpx: Enable ACPI P-state support ...................................................................... Patch Set 7: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/44404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3bf3ad7f82fbf196a2134a8138b10176fc8be2cc Gerrit-Change-Number: 44404 Gerrit-PatchSet: 7 Gerrit-Owner: Jingle Hsu <jingle_hsu(a)wiwynn.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jonzhang(a)fb.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Mon, 17 Aug 2020 08:43:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable
by Mike Banon (Code Review) 17 Aug '20

17 Aug '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40485 ) Change subject: vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable ...................................................................... vc/amd/agesa/f15tn: add 933 MHz to GfxMemClockFrequencyDefinitionTable This fix is required to avoid the division-by-zero error described at https://mail.coreboot.org/pipermail/coreboot/2014-March/077418.html while trying to run the DDR3 memory at 1866 MHz frequency (= 2*933). With this fix in place, ASUS A88XM-E boots fine with RAM at 1866 MHz. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I8e7d00e362879b1247ecf2ab828936268bf9075f --- M src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/40485/1 diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c index ce50a97..6177d08 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GfxLibTN.c @@ -73,7 +73,7 @@ CONST UINT16 GfxMemClockFrequencyDefinitionTable [][8] = { {0 , 0 , 0 , 0 , 333, 0, 400, 0 }, {0 , 0 , 533, 0 , 0 , 0 , 667, 0 }, -{0 , 0 , 800, 0 , 0 , 0 , 0 , 0 }, +{0 , 0 , 800, 0 , 0 , 0 , 933, 0 }, {0 , 1050, 1066, 0 , 0, 0 , 0, 1200} }; -- To view, visit https://review.coreboot.org/c/coreboot/+/40485 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I8e7d00e362879b1247ecf2ab828936268bf9075f Gerrit-Change-Number: 40485 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: nb/amd/agesa: read 256 bytes to SPD buffer instead of 128
by Mike Banon (Code Review) 17 Aug '20

17 Aug '20

Mike Banon has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40484 ) Change subject: nb/amd/agesa: read 256 bytes to SPD buffer instead of 128 ...................................................................... nb/amd/agesa: read 256 bytes to SPD buffer instead of 128 Required for adding the XMP profiles support. SPD buffer is already 256 bytes at AMD AGESA vendorcode, so this is fine. Signed-off-by: Mike Banon <mikebdp2(a)gmail.com> Change-Id: I7340b110477a4cc1ecb1c239181436e51952568f --- M src/northbridge/amd/agesa/family14/dimmSpd.c M src/northbridge/amd/agesa/family15tn/dimmSpd.c M src/northbridge/amd/agesa/family16kb/dimmSpd.c 3 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/40484/1 diff --git a/src/northbridge/amd/agesa/family14/dimmSpd.c b/src/northbridge/amd/agesa/family14/dimmSpd.c index e9eeb49..fedf53c 100644 --- a/src/northbridge/amd/agesa/family14/dimmSpd.c +++ b/src/northbridge/amd/agesa/family14/dimmSpd.c @@ -41,7 +41,7 @@ if (spdAddress == 0) return AGESA_ERROR; - int err = smbus_readSpd(spdAddress, (void *) info->Buffer, 128); + int err = smbus_readSpd(spdAddress, (void *) info->Buffer, 256); if (err) return AGESA_ERROR; return AGESA_SUCCESS; diff --git a/src/northbridge/amd/agesa/family15tn/dimmSpd.c b/src/northbridge/amd/agesa/family15tn/dimmSpd.c index 761b8b8..498488a 100644 --- a/src/northbridge/amd/agesa/family15tn/dimmSpd.c +++ b/src/northbridge/amd/agesa/family15tn/dimmSpd.c @@ -40,7 +40,7 @@ if (spdAddress == 0) return AGESA_ERROR; - int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 256); if (err) return AGESA_ERROR; return AGESA_SUCCESS; diff --git a/src/northbridge/amd/agesa/family16kb/dimmSpd.c b/src/northbridge/amd/agesa/family16kb/dimmSpd.c index 6c751f9..3a6192c 100644 --- a/src/northbridge/amd/agesa/family16kb/dimmSpd.c +++ b/src/northbridge/amd/agesa/family16kb/dimmSpd.c @@ -40,7 +40,7 @@ if (spdAddress == 0) return AGESA_ERROR; - int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); + int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 256); if (err) return AGESA_ERROR; return AGESA_SUCCESS; -- To view, visit https://review.coreboot.org/c/coreboot/+/40484 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7340b110477a4cc1ecb1c239181436e51952568f Gerrit-Change-Number: 40484 Gerrit-PatchSet: 1 Gerrit-Owner: Mike Banon <mikebdp2(a)gmail.com> Gerrit-MessageType: newchange

4 7

Change in coreboot[master]: soc/intel/skylake/acpi.c: Name devices on secondary bus
by Patrick Georgi (Code Review) 17 Aug '20

17 Aug '20

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43074 ) Change subject: soc/intel/skylake/acpi.c: Name devices on secondary bus ...................................................................... soc/intel/skylake/acpi.c: Name devices on secondary bus Naming a device allows an ACPI _ROM method to be written for it. GPUs may require this to make the configuration data contained within available to an OS driver. This may be required for GPUs that do not contain their vBIOS, or perhaps the drivers require it in this form/fashion. Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully obtains the vBIOS via ACPI (kernel 5.7.11). Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43074 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/soc/intel/skylake/acpi.c 1 file changed, 8 insertions(+), 2 deletions(-) Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index ae9d784..0ec6e47 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -632,12 +632,18 @@ if (dev->path.type != DEVICE_PATH_PCI) return NULL; - /* Only match devices on the root bus */ - if (dev->bus && dev->bus->secondary > 0) + /* Match functions 0 and 1 for possible GPUs on a secondary bus */ + if (dev->bus && dev->bus->secondary > 0) { + switch (PCI_FUNC(dev->path.pci.devfn)) { + case 0: return "DEV0"; + case 1: return "DEV1"; + } return NULL; + } switch (dev->path.pci.devfn) { case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_PEG0: return "PEGP"; case SA_DEVFN_IGD: return "GFX0"; case PCH_DEVFN_ISH: return "ISHB"; case PCH_DEVFN_XHCI: return "XHCI"; -- To view, visit https://review.coreboot.org/c/coreboot/+/43074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Gerrit-Change-Number: 43074 Gerrit-PatchSet: 11 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Prasun Gera Gerrit-MessageType: merged

1 0

Change in coreboot[master]: mb/google/volteer: Make devicetree default as Aux Orientation retimer...
by Brandon Breitenstein (Code Review) 17 Aug '20

17 Aug '20

Brandon Breitenstein has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44358 ) Change subject: mb/google/volteer: Make devicetree default as Aux Orientation retimer controlled ...................................................................... mb/google/volteer: Make devicetree default as Aux Orientation retimer controlled With new board designs being introduced it does not make sense for the default devicetree setting to be retimer disabled on port 0 for Aux Orientation. Change the default to be Aux Orintation retimer controlled on all ports and move the SOC controlled overrides to the corresponding overridetree files. BUG=NONE BRANCH=NONE TEST=Built image for delbin and verified that port 0 flip is working. Change-Id: I5ff59493472db096c027d223f2fd61545dc935e2 Signed-off-by: Brandon Breitenstein <brandon.breitenstein(a)intel.com> --- M src/mainboard/google/volteer/variants/baseboard/devicetree.cb M src/mainboard/google/volteer/variants/halvor/overridetree.cb M src/mainboard/google/volteer/variants/malefor/overridetree.cb M src/mainboard/google/volteer/variants/terrador/overridetree.cb M src/mainboard/google/volteer/variants/trondo/overridetree.cb M src/mainboard/google/volteer/variants/volteer/overridetree.cb M src/mainboard/google/volteer/variants/volteer2/overridetree.cb 7 files changed, 28 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/44358/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index 53bbe5a..4bb3ad8 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -160,9 +160,9 @@ # TCSS USB3 register "TcssXhciEn" = "1" - register "TcssAuxOri" = "1" - register "IomTypeCPortPadCfg[0]" = "0x090E000A" - register "IomTypeCPortPadCfg[1]" = "0x090E000D" + register "TcssAuxOri" = "0" + register "IomTypeCPortPadCfg[0]" = "0x09000000" + register "IomTypeCPortPadCfg[1]" = "0x09000000" register "IomTypeCPortPadCfg[2]" = "0x09000000" register "IomTypeCPortPadCfg[3]" = "0x09000000" register "IomTypeCPortPadCfg[4]" = "0x09000000" diff --git a/src/mainboard/google/volteer/variants/halvor/overridetree.cb b/src/mainboard/google/volteer/variants/halvor/overridetree.cb index 12e059c..e34ea21 100644 --- a/src/mainboard/google/volteer/variants/halvor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/halvor/overridetree.cb @@ -17,6 +17,10 @@ register "SaGv" = "SaGv_Disabled" + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic diff --git a/src/mainboard/google/volteer/variants/malefor/overridetree.cb b/src/mainboard/google/volteer/variants/malefor/overridetree.cb index c84ed83..3895c5c 100644 --- a/src/mainboard/google/volteer/variants/malefor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/malefor/overridetree.cb @@ -19,6 +19,10 @@ register "SaGv" = "SaGv_Disabled" + register = "TcssAuxOri" = "1" + register = "IomTypeCPortPadCfg[0]" = "0x090E000A" + register = "IomTypeCPortPadCfg[1]" = "0x090E000D" + # I2C Port Config register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 8c0fb38..936a5d2 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -19,6 +19,10 @@ register "SaGv" = "SaGv_Disabled" + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic diff --git a/src/mainboard/google/volteer/variants/trondo/overridetree.cb b/src/mainboard/google/volteer/variants/trondo/overridetree.cb index 0932b64..72b1431 100644 --- a/src/mainboard/google/volteer/variants/trondo/overridetree.cb +++ b/src/mainboard/google/volteer/variants/trondo/overridetree.cb @@ -1,5 +1,10 @@ chip soc/intel/tigerlake register "SaGv" = "SaGv_Disabled" + + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + device domain 0 on device pci 15.1 on chip drivers/i2c/hid diff --git a/src/mainboard/google/volteer/variants/volteer/overridetree.cb b/src/mainboard/google/volteer/variants/volteer/overridetree.cb index d4bd7f4..2409ab5 100644 --- a/src/mainboard/google/volteer/variants/volteer/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer/overridetree.cb @@ -43,6 +43,10 @@ }, }, }" + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic diff --git a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb index 62749fc..e32099b 100644 --- a/src/mainboard/google/volteer/variants/volteer2/overridetree.cb +++ b/src/mainboard/google/volteer/variants/volteer2/overridetree.cb @@ -1,4 +1,8 @@ chip soc/intel/tigerlake + register "TcssAuxOri" = "1" + register "IomTypeCPortPadCfg[0]" = "0x090E000A" + register "IomTypeCPortPadCfg[1]" = "0x090E000D" + device domain 0 on device pci 15.0 on chip drivers/i2c/generic -- To view, visit https://review.coreboot.org/c/coreboot/+/44358 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5ff59493472db096c027d223f2fd61545dc935e2 Gerrit-Change-Number: 44358 Gerrit-PatchSet: 1 Gerrit-Owner: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: mb/google/zork: Switch to normal read mode for EM100
by Furquan Shaikh (Code Review) 17 Aug '20

17 Aug '20

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44464 ) Change subject: mb/google/zork: Switch to normal read mode for EM100 ...................................................................... mb/google/zork: Switch to normal read mode for EM100 This change sets the EFS config for SPI read mode to normal read mode when using em100. With this, the boot is stable again without any random hangs in PSP. BUG=b:164429022 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Change-Id: I4cd3673dcc44a61905719a57f734df2fb9f4e6e2 --- M src/mainboard/google/zork/Kconfig 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/44464/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index c4a8f33..24c49c1 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -244,13 +244,13 @@ config EFS_SPI_READ_MODE int - default 4 if EM100 - default 2 + default 0 if EM100 # Normal read mode + default 2 # Dual IO (1-1-2) config EFS_SPI_SPEED int - default 3 if EM100 - default 0 + default 3 if EM100 # 16.66 MHz + default 0 # 66.66 MHz config EFS_SPI_MICRON_FLAG int -- To view, visit https://review.coreboot.org/c/coreboot/+/44464 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4cd3673dcc44a61905719a57f734df2fb9f4e6e2 Gerrit-Change-Number: 44464 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-MessageType: newchange

4 3

Change in coreboot[master]: mb/intel/jasperlake_rvp: Configure GPIOs related to UFC
by Varshit B Pandya (Code Review) 17 Aug '20

17 Aug '20

Varshit B Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44416 ) Change subject: mb/intel/jasperlake_rvp: Configure GPIOs related to UFC ...................................................................... mb/intel/jasperlake_rvp: Configure GPIOs related to UFC This change will configure GPIOs as per schematics. Signed-off-by: Pandya, Varshit B <varshit.b.pandya(a)intel.com> Change-Id: I026c16f73cf597614efaea3e0f0ab1e2cfe1e211 --- M src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c 1 file changed, 15 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/44416/1 diff --git a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c index d67f4a4..02ddcbe 100644 --- a/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c +++ b/src/mainboard/intel/jasperlake_rvp/variants/jslrvp/gpio.c @@ -31,6 +31,9 @@ /* PMC_PLT_RST_N */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* CAM1_RST_N */ + PAD_CFG_GPO(GPP_B14, 0, PLTRST), + /* M.2_WLAN_PERST_N */ PAD_CFG_GPO(GPP_B17, 1, PLTRST), @@ -76,9 +79,18 @@ /* CAM2_PWREN */ PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* CAM1_PWREN */ + PAD_CFG_GPO(GPP_D5, 0, PLTRST), + /*LAN_RST_N*/ PAD_CFG_GPO(GPP_D6, 1, PLTRST), + /* I2C4B_SDA */ + PAD_CFG_NF(GPP_D12, NONE, PLTRST, NF3), + + /* I2C4B_SCL */ + PAD_CFG_NF(GPP_D13, NONE, PLTRST, NF3), + /* AVS_I2S_MCLK */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), @@ -97,6 +109,9 @@ /* I2C5_SCL */ PAD_CFG_NF(GPP_D23, NONE, PLTRST, NF1), + /* IMGCLKOUT_0 */ + PAD_CFG_NF(GPP_E0, NONE, PLTRST, NF2), + /* IMGCLKOUT_1 */ PAD_CFG_NF(GPP_E2, NONE, PLTRST, NF1), -- To view, visit https://review.coreboot.org/c/coreboot/+/44416 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I026c16f73cf597614efaea3e0f0ab1e2cfe1e211 Gerrit-Change-Number: 44416 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit B Pandya <varshit.b.pandya(a)intel.com> Gerrit-MessageType: newchange

4 9

Change in coreboot[master]: Makefile.inc: Remove redundant warning flag
by HAOUAS Elyes (Code Review) 17 Aug '20

17 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44216 ) Change subject: Makefile.inc: Remove redundant warning flag ...................................................................... Makefile.inc: Remove redundant warning flag '-Wstrict-aliasing' is turned on by '-Wall' Change-Id: I51eb8241389f13d2659aef0a3b4b376ce9c651cf Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M Makefile.inc 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/44216/1 diff --git a/Makefile.inc b/Makefile.inc index 2526c25..a54b76c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -422,7 +422,7 @@ CFLAGS_common += -pipe -g -nostdinc -std=gnu11 CFLAGS_common += -nostdlib -Wall -Wundef -Wstrict-prototypes -Wmissing-prototypes CFLAGS_common += -Wwrite-strings -Wredundant-decls -Wno-trigraphs -Wimplicit-fallthrough -CFLAGS_common += -Wstrict-aliasing -Wshadow -Wdate-time -Wtype-limits -Wvla +CFLAGS_common += -Wshadow -Wdate-time -Wtype-limits -Wvla CFLAGS_common += -Wlogical-op -Wduplicated-cond -Wdangling-else CFLAGS_common += -ffreestanding -fno-builtin -fomit-frame-pointer CFLAGS_common += -ffunction-sections -fdata-sections -fno-pie -- To view, visit https://review.coreboot.org/c/coreboot/+/44216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51eb8241389f13d2659aef0a3b4b376ce9c651cf Gerrit-Change-Number: 44216 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

4 12

Change in coreboot[master]: crossgcc: Upgrade IASL to version 20200717
by HAOUAS Elyes (Code Review) 17 Aug '20

17 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43554 ) Change subject: crossgcc: Upgrade IASL to version 20200717 ...................................................................... crossgcc: Upgrade IASL to version 20200717 Change-Id: Ib325fa5c37c32702c572ab56c99e1f8f785cbe53 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix2-20200717_iasl.patch D util/crossgcc/sum/acpica-unix2-20200528.tar.gz.cksum A util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum 4 files changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/43554/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 18948d7..1a9d6bb 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -40,7 +40,7 @@ GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.33.1 GDB_VERSION=9.2 -IASL_VERSION=20200528 +IASL_VERSION=20200717 PYTHON_VERSION=3.8.4 EXPAT_VERSION=2.2.9 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20200528_iasl.patch b/util/crossgcc/patches/acpica-unix2-20200717_iasl.patch similarity index 73% rename from util/crossgcc/patches/acpica-unix2-20200528_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20200717_iasl.patch index 3fac35d..01dec7c 100644 --- a/util/crossgcc/patches/acpica-unix2-20200528_iasl.patch +++ b/util/crossgcc/patches/acpica-unix2-20200717_iasl.patch @@ -1,6 +1,6 @@ -diff -Naur acpica-unix2-20200528_/source/compiler/asloptions.c acpica-unix2-20200528/source/compiler/asloptions.c > acpica-unix2-20200528_iasl.patch ---- acpica-unix2-20200528_/source/compiler/asloptions.c -+++ acpica-unix2-20200528/source/compiler/asloptions.c +diff -Naur acpica-unix2-20200717_/source/compiler/asloptions.c acpica-unix2-20200717/source/compiler/asloptions.c > acpica-unix2-20200717_iasl.patch +--- acpica-unix2-20200717_/source/compiler/asloptions.c ++++ acpica-unix2-20200717/source/compiler/asloptions.c @@ -126,6 +126,7 @@ if (Gbl_DoSignon) { diff --git a/util/crossgcc/sum/acpica-unix2-20200528.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200528.tar.gz.cksum deleted file mode 100644 index d2265e1..0000000 --- a/util/crossgcc/sum/acpica-unix2-20200528.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -27afd4c05c966e9390fcc30bdf1f53ddb7d69033 tarballs/acpica-unix2-20200528.tar.gz diff --git a/util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum new file mode 100644 index 0000000..9bcfe83 --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20200717.tar.gz.cksum @@ -0,0 +1 @@ +92b0177f36b5209e6a667808ca58ef7462c4a6c7 tarballs/acpica-unix2-20200717.tar.gz -- To view, visit https://review.coreboot.org/c/coreboot/+/43554 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib325fa5c37c32702c572ab56c99e1f8f785cbe53 Gerrit-Change-Number: 43554 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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Change in coreboot[master]: [WIP]crossgcc: Upgrade Python to version 3.8.2
by HAOUAS Elyes (Code Review) 17 Aug '20

17 Aug '20

HAOUAS Elyes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39148 ) Change subject: [WIP]crossgcc: Upgrade Python to version 3.8.2 ...................................................................... [WIP]crossgcc: Upgrade Python to version 3.8.2 Change-Id: I660994ece28f04d97de2fe3a074ebcf93fb4d2f4 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/sum/Python-3.8.1.tar.xz.cksum A util/crossgcc/sum/Python-3.8.2.tar.xz.cksum 3 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/39148/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index fef4b82..eb2e4e9 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -55,7 +55,7 @@ BINUTILS_VERSION=2.34 GDB_VERSION=8.3.1 IASL_VERSION=20200214 -PYTHON_VERSION=3.8.1 +PYTHON_VERSION=3.8.2 EXPAT_VERSION=2.2.9 # CLANG version number CLANG_VERSION=9.0.0 diff --git a/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum b/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum deleted file mode 100644 index e899a45..0000000 --- a/util/crossgcc/sum/Python-3.8.1.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -a48fd28a037c0bcd7b7fc4d914c023f584e910ed tarballs/Python-3.8.1.tar.xz diff --git a/util/crossgcc/sum/Python-3.8.2.tar.xz.cksum b/util/crossgcc/sum/Python-3.8.2.tar.xz.cksum new file mode 100644 index 0000000..1a0c784 --- /dev/null +++ b/util/crossgcc/sum/Python-3.8.2.tar.xz.cksum @@ -0,0 +1 @@ +5ae54baf26628a7ed74206650a31192e6d5c6f93 tarballs/Python-3.8.2.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/39148 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I660994ece28f04d97de2fe3a074ebcf93fb4d2f4 Gerrit-Change-Number: 39148 Gerrit-PatchSet: 1 Gerrit-Owner: HAOUAS Elyes <ehaouas(a)noos.fr> Gerrit-MessageType: newchange

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