coreboot-gerrit August 2020

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Change in coreboot[master]: soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug
by Felix Held (Code Review) 11 Aug '20

11 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44351 ) Change subject: soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug ...................................................................... soc/amd/common/espi_util: espi_std_io_decode: fix edge case bug When address and data register for the SIO control register access is passed as one I/O region with a size of 2, the corresponding special decode enable register should be used instead of a generic one to save the rather limited generic ones for other decode ranges. Change-Id: Ie54ff6afa2bd2156f7b3a3cf83091f1f932b6993 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/44351/1 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 3f26a29..4415615 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -104,6 +104,9 @@ */ static int espi_std_io_decode(uint16_t base, size_t size) { + if (size == 2 && base == 0x2e) + return ESPI_DECODE_IO_0X2E_0X2F_EN; + if (size != 1) return -1; -- To view, visit https://review.coreboot.org/c/coreboot/+/44351 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie54ff6afa2bd2156f7b3a3cf83091f1f932b6993 Gerrit-Change-Number: 44351 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/espi_util: simplify espi_std_io_decode function
by Felix Held (Code Review) 11 Aug '20

11 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44350 ) Change subject: soc/amd/common/espi_util: simplify espi_std_io_decode function ...................................................................... soc/amd/common/espi_util: simplify espi_std_io_decode function We can just return at all places where the ret variable was written before its value gets returned at the end of the function. Change-Id: Id87f41c0d9e3397879ac3d15b13179cca1a1263f Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 5 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/44350/1 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index ba633a9..3f26a29 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -104,29 +104,21 @@ */ static int espi_std_io_decode(uint16_t base, size_t size) { - int ret = -1; - if (size != 1) - return ret; + return -1; switch (base) { case 0x80: - ret = ESPI_DECODE_IO_0x80_EN; - break; + return ESPI_DECODE_IO_0x80_EN; case 0x60: case 0x64: - ret = ESPI_DECODE_IO_0X60_0X64_EN; - break; + return ESPI_DECODE_IO_0X60_0X64_EN; case 0x2e: case 0x2f: - ret = ESPI_DECODE_IO_0X2E_0X2F_EN; - break; + return ESPI_DECODE_IO_0X2E_0X2F_EN; default: - ret = -1; - break; + return -1; } - - return ret; } static size_t espi_get_io_window_size(int idx) -- To view, visit https://review.coreboot.org/c/coreboot/+/44350 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id87f41c0d9e3397879ac3d15b13179cca1a1263f Gerrit-Change-Number: 44350 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/espi_util: make decode enable parameter uint32_t
by Felix Held (Code Review) 11 Aug '20

11 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44349 ) Change subject: soc/amd/common/espi_util: make decode enable parameter uint32_t ...................................................................... soc/amd/common/espi_util: make decode enable parameter uint32_t Since this is a bit mask applied to the raw value of a 32 bit register, this should be a 32 bit unsigned type. Change-Id: I9d9930963d8c827a84dc1f67e2f2fa8f95ab40f2 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/44349/1 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index ae5edb6..ba633a9 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -54,7 +54,7 @@ write8((void *)(espi_get_bar() + reg), val); } -static void espi_enable_decode(int decode_en) +static void espi_enable_decode(uint32_t decode_en) { uint32_t val; @@ -63,7 +63,7 @@ espi_write32(ESPI_DECODE, val); } -static bool espi_is_decode_enabled(int decode) +static bool espi_is_decode_enabled(uint32_t decode) { uint32_t val; -- To view, visit https://review.coreboot.org/c/coreboot/+/44349 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9d9930963d8c827a84dc1f67e2f2fa8f95ab40f2 Gerrit-Change-Number: 44349 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/common/espi_util: make reg parameter unsigned
by Felix Held (Code Review) 11 Aug '20

11 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44348 ) Change subject: soc/amd/common/espi_util: make reg parameter unsigned ...................................................................... soc/amd/common/espi_util: make reg parameter unsigned Th register number passed to the low level read/write functions should never be negative. Change-Id: I5d7e117b3badab900d030be8e69ded026d659f8a Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/common/block/lpc/espi_util.c 1 file changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/44348/1 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 29028a4..ae5edb6 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -24,32 +24,32 @@ return espi_bar; } -static uint32_t espi_read32(int reg) +static uint32_t espi_read32(unsigned int reg) { return read32((void *)(espi_get_bar() + reg)); } -static void espi_write32(int reg, uint32_t val) +static void espi_write32(unsigned int reg, uint32_t val) { write32((void *)(espi_get_bar() + reg), val); } -static uint16_t espi_read16(int reg) +static uint16_t espi_read16(unsigned int reg) { return read16((void *)(espi_get_bar() + reg)); } -static void espi_write16(int reg, uint16_t val) +static void espi_write16(unsigned int reg, uint16_t val) { write16((void *)(espi_get_bar() + reg), val); } -static uint8_t espi_read8(int reg) +static uint8_t espi_read8(unsigned int reg) { return read8((void *)(espi_get_bar() + reg)); } -static void espi_write8(int reg, uint8_t val) +static void espi_write8(unsigned int reg, uint8_t val) { write8((void *)(espi_get_bar() + reg), val); } -- To view, visit https://review.coreboot.org/c/coreboot/+/44348 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5d7e117b3badab900d030be8e69ded026d659f8a Gerrit-Change-Number: 44348 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/amd/stoneyridge/acpi: clean up global NVS
by Felix Held (Code Review) 11 Aug '20

11 Aug '20

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44184 ) Change subject: soc/amd/stoneyridge/acpi: clean up global NVS ...................................................................... soc/amd/stoneyridge/acpi: clean up global NVS Some fields in GNVS seem to be copied over from Apollolake to Stoneyridge. This patch removes the unused fields. Change-Id: I135c4a4547668fe67e74d0ea9ae3a03c3687375f Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/stoneyridge/acpi/globalnvs.asl M src/soc/amd/stoneyridge/include/soc/nvs.h 2 files changed, 30 insertions(+), 50 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/44184/1 diff --git a/src/soc/amd/stoneyridge/acpi/globalnvs.asl b/src/soc/amd/stoneyridge/acpi/globalnvs.asl index 2865352..0acc408 100644 --- a/src/soc/amd/stoneyridge/acpi/globalnvs.asl +++ b/src/soc/amd/stoneyridge/acpi/globalnvs.asl @@ -14,25 +14,15 @@ /* Miscellaneous */ Offset (0x00), PCNT, 8, // 0x00 - Processor Count - PPCM, 8, // 0x01 - Max PPC State - LIDS, 8, // 0x02 - LID State - PWRS, 8, // 0x03 - AC Power State - DPTE, 8, // 0x04 - Enable DPTF - CBMC, 32, // 0x05 - 0x08 - coreboot Memory Console - PM1I, 64, // 0x09 - 0x10 - System Wake Source - PM1 Index - GPEI, 64, // 0x11 - 0x18 - GPE Wake Source - NHLA, 64, // 0x19 - 0x20 - NHLT Address - NHLL, 32, // 0x21 - 0x24 - NHLT Length - PRT0, 32, // 0x25 - 0x28 - PERST_0 Address - SCDP, 8, // 0x29 - SD_CD GPIO portid - SCDO, 8, // 0x2A - GPIO pad offset relative to the community - TMPS, 8, // 0x2B - Temperature Sensor ID - TLVL, 8, // 0x2C - Throttle Level Limit - FLVL, 8, // 0x2D - Current FAN Level - TCRT, 8, // 0x2E - Critical Threshold - TPSV, 8, // 0x2F - Passive Threshold - TMAX, 8, // 0x30 - CPU Tj_max - Offset (0x34), // 0x34 - AOAC Device Enables + LIDS, 8, // 0x01 - LID State + PWRS, 8, // 0x02 - AC Power State + CBMC, 32, // 0x03 - 0x06 - coreboot Memory Console + PM1I, 64, // 0x07 - 0x0e - System Wake Source - PM1 Index + GPEI, 64, // 0x0f - 0x16 - GPE Wake Source + TMPS, 8, // 0x17 - Temperature Sensor ID + TCRT, 8, // 0x18 - Critical Threshold + TPSV, 8, // 0x19 - Passive Threshold + Offset (0x20), // 0x20 - AOAC Device Enables , 5, IC0E, 1, // I2C0, 5 IC1E, 1, // I2C1, 6 @@ -51,11 +41,11 @@ , 2, ESPI, 1, // ESPI, 27 , 4, - FW00, 16, // 0x38 - xHCI FW ROM addr, boot RAM - FW02, 16, // 0x3A - xHCI FW ROM addr, Instruction RAM - FW01, 32, // 0x3C - xHCI FW RAM addr, boot RAM - FW03, 32, // 0x40 - xHCI FW RAM addr, Instruction RAM - EH10, 32, // 0x44 - EHCI BAR + FW00, 16, // 0x24 - xHCI FW ROM addr, boot RAM + FW02, 16, // 0x26 - xHCI FW ROM addr, Instruction RAM + FW01, 32, // 0x28 - xHCI FW RAM addr, boot RAM + FW03, 32, // 0x2c - xHCI FW RAM addr, Instruction RAM + EH10, 32, // 0x30 - EHCI BAR /* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */ Offset (0x100), #include <vendorcode/google/chromeos/acpi/gnvs.asl> diff --git a/src/soc/amd/stoneyridge/include/soc/nvs.h b/src/soc/amd/stoneyridge/include/soc/nvs.h index 864cfff..9c479c6 100644 --- a/src/soc/amd/stoneyridge/include/soc/nvs.h +++ b/src/soc/amd/stoneyridge/include/soc/nvs.h @@ -17,32 +17,22 @@ struct __packed global_nvs { /* Miscellaneous */ uint8_t pcnt; /* 0x00 - Processor Count */ - uint8_t ppcm; /* 0x01 - Max PPC State */ - uint8_t lids; /* 0x02 - LID State */ - uint8_t pwrs; /* 0x03 - AC Power State */ - uint8_t dpte; /* 0x04 - Enable DPTF */ - uint32_t cbmc; /* 0x05 - 0x08 - coreboot Memory Console */ - uint64_t pm1i; /* 0x09 - 0x10 - System Wake Source - PM1 Index */ - uint64_t gpei; /* 0x11 - 0x18 - GPE Wake Source */ - uint64_t nhla; /* 0x19 - 0x20 - NHLT Address */ - uint32_t nhll; /* 0x21 - 0x24 - NHLT Length */ - uint32_t prt0; /* 0x25 - 0x28 - PERST_0 Address */ - uint8_t scdp; /* 0x29 - SD_CD GPIO portid */ - uint8_t scdo; /* 0x2A - GPIO pad relative offset */ - uint8_t tmps; /* 0x2B - Temperature Sensor ID */ - uint8_t tlvl; /* 0x2C - Throttle Level Limit */ - uint8_t flvl; /* 0x2D - Current FAN Level */ - uint8_t tcrt; /* 0x2E - Critical Threshold */ - uint8_t tpsv; /* 0x2F - Passive Threshold */ - uint8_t tmax; /* 0x30 - CPU Tj_max */ - uint8_t pad1[3]; - aoac_devs_t aoac; /* 0x34 - AOAC device enables */ - uint16_t fw00; /* 0x38 - XhciFwRomAddr_Rom, Boot RAM */ - uint16_t fw02; /* 0x3A - XhciFwRomAddr_Ram, Instr RAM */ - uint32_t fw01; /* 0x3C - XhciFwRamAddr_Rom, Boot RAM sz/base */ - uint32_t fw03; /* 0x40 - XhciFwRomAddr_Ram, Instr RAM sz/base */ - uint32_t eh10; /* 0x40 - EHCI BAR */ - uint8_t unused[184]; + uint8_t lids; /* 0x01 - LID State */ + uint8_t pwrs; /* 0x02 - AC Power State */ + uint32_t cbmc; /* 0x03 - 0x06 - coreboot Memory Console */ + uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ + uint8_t tmps; /* 0x17 - Temperature Sensor ID */ + uint8_t tcrt; /* 0x18 - Critical Threshold */ + uint8_t tpsv; /* 0x19 - Passive Threshold */ + uint8_t pad1[6]; + aoac_devs_t aoac; /* 0x20 - AOAC device enables */ + uint16_t fw00; /* 0x24 - XhciFwRomAddr_Rom, Boot RAM */ + uint16_t fw02; /* 0x26 - XhciFwRomAddr_Ram, Instr RAM */ + uint32_t fw01; /* 0x28 - XhciFwRamAddr_Rom, Boot RAM sz/base */ + uint32_t fw03; /* 0x2c - XhciFwRomAddr_Ram, Instr RAM sz/base */ + uint32_t eh10; /* 0x30 - EHCI BAR */ + uint8_t unused[204]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; -- To view, visit https://review.coreboot.org/c/coreboot/+/44184 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I135c4a4547668fe67e74d0ea9ae3a03c3687375f Gerrit-Change-Number: 44184 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Shreesh Chhabbi (Code Review) 11 Aug '20

11 Aug '20

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > > Patch Set 4: > > > > > > > Patch Set 4: > > > > > > > > > Patch Set 4: > > > > > > > > > > FYI I was able to boot my Volteer with this patch & adding COS_MAPPED_TO_MSB and USE_CAR_NEM_ENHANCED_V1 to the Kconfig. > > > > > > > > Thanks for checking Tim :-) > > > > TGL can select USE_CAR_NEM_ENHANCED_V2. > > > > > > Oops, yeah that was a typo in Gerrit not in the code, I did use V2 in my Kconfig 😄 > > > > Hi Tim, did you use Volteer QS / Volteer EVT? Because on Volteer ES2, we would see that these 2 MSRs are not accessible. > > I just thought about that, no it was on proto2. I just received my other board, I will try it out soon. Ok. Thanks the info. -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 11 Aug 2020 17:13:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Tim Wawrzynczak (Code Review) 11 Aug '20

11 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > > Patch Set 4: > > > > > > > Patch Set 4: > > > > > > > > FYI I was able to boot my Volteer with this patch & adding COS_MAPPED_TO_MSB and USE_CAR_NEM_ENHANCED_V1 to the Kconfig. > > > > > > Thanks for checking Tim :-) > > > TGL can select USE_CAR_NEM_ENHANCED_V2. > > > > Oops, yeah that was a typo in Gerrit not in the code, I did use V2 in my Kconfig 😄 > > Hi Tim, did you use Volteer QS / Volteer EVT? Because on Volteer ES2, we would see that these 2 MSRs are not accessible. I just thought about that, no it was on proto2. I just received my other board, I will try it out soon. -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 11 Aug 2020 17:08:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Shreesh Chhabbi (Code Review) 11 Aug '20

11 Aug '20

Shreesh Chhabbi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 4: > Patch Set 4: > > > Patch Set 4: > > > > > Patch Set 4: > > > > > > FYI I was able to boot my Volteer with this patch & adding COS_MAPPED_TO_MSB and USE_CAR_NEM_ENHANCED_V1 to the Kconfig. > > > > Thanks for checking Tim :-) > > TGL can select USE_CAR_NEM_ENHANCED_V2. > > Oops, yeah that was a typo in Gerrit not in the code, I did use V2 in my Kconfig 😄 Hi Tim, did you use Volteer QS / Volteer EVT? Because on Volteer ES2, we would see that these 2 MSRs are not accessible. -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 11 Aug 2020 17:06:30 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/skylake/acpi.c: Name devices on secondary bus
by Benjamin Doron (Code Review) 11 Aug '20

11 Aug '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43074 ) Change subject: soc/intel/skylake/acpi.c: Name devices on secondary bus ...................................................................... Patch Set 6: (1 comment) https://review.coreboot.org/c/coreboot/+/43074/4//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43074/4//COMMIT_MSG@15 PS4, Line 15: obtains the vBIOS via ACPI. > Please note the Linux kernel version. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/43074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Gerrit-Change-Number: 43074 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Prasun Gera Gerrit-Comment-Date: Tue, 11 Aug 2020 17:05:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: comment

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Change in coreboot[master]: [WIP] soc/intel/skylake: Support NHLT 1ch DMIC
by Benjamin Doron (Code Review) 11 Aug '20

11 Aug '20

Benjamin Doron has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43072 ) Change subject: [WIP] soc/intel/skylake: Support NHLT 1ch DMIC ...................................................................... Patch Set 3: This change is ready for review. -- To view, visit https://review.coreboot.org/c/coreboot/+/43072 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Idba3a714faab5ca1958de7dcfc0fc667c60ea7fd Gerrit-Change-Number: 43072 Gerrit-PatchSet: 3 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 11 Aug 2020 17:04:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No Gerrit-MessageType: comment

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coreboot-gerrit August 2020