coreboot-gerrit August 2020

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Tim Wawrzynczak (Code Review) 11 Aug '20

11 Aug '20

Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 4: (2 comments) https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@20 PS3, Line 20: : Also the COS mask selection is mapped to bit 32:33 of MSR : IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before : MSR write instead of eax(mas 31:0). This implementation corrects that : as well. > for CNL, SKL and KBL i could check the mask selection is mapped to LSB. […] Ah ok, I think my confusion was the layout of the register being different between SoCs. Also I can't seem to find it documented in #575681 (not listed in the MSR chapter 12) https://review.coreboot.org/c/coreboot/+/43494/3/src/soc/intel/common/block… File src/soc/intel/common/block/cpu/car/cache_as_ram.S: https://review.coreboot.org/c/coreboot/+/43494/3/src/soc/intel/common/block… PS3, Line 394: mov %ebx, %ecx maybe comment %ecx is now way size? took me some tracing back to find it -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 11 Aug 2020 16:14:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Aamir Bohra (Code Review) 11 Aug '20

11 Aug '20

Aamir Bohra has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 4: (3 comments) https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@7 PS3, Line 7: nem > NEM Done https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@12 PS3, Line 12: upto > up to Done https://review.coreboot.org/c/coreboot/+/43494/3//COMMIT_MSG@20 PS3, Line 20: : Also the COS mask selection is mapped to bit 32:33 of MSR : IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before : MSR write instead of eax(mas 31:0). This implementation corrects that : as well. > Gotcha, thanks Aamir, I am finding the documentation around this register kind of confusing 😕 for CNL, SKL and KBL i could check the mask selection is mapped to LSB. For JSL it is documented in doc#618876 chapter 50. -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 11 Aug 2020 13:31:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Comment-In-Reply-To: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by build bot (Jenkins) (Code Review) 11 Aug '20

11 Aug '20

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/43494 ) Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... Patch Set 4: (1 comment) https://review.coreboot.org/c/coreboot/+/43494/4/src/soc/intel/common/block… File src/soc/intel/common/block/cpu/Kconfig: https://review.coreboot.org/c/coreboot/+/43494/4/src/soc/intel/common/block… PS4, Line 58: This config suppport INTEL_CAR_NEM_ENHANCED mode on 'suppport' may be misspelled - perhaps 'support'? -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Comment-Date: Tue, 11 Aug 2020 13:26:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode
by Aamir Bohra (Code Review) 11 Aug '20

11 Aug '20

Hello build bot (Jenkins), Furquan Shaikh, Tim Wawrzynczak, Duncan Laurie, Rizwan Qureshi, Subrata Banik, Usha P, Patrick Rudolph, Aaron Durbin, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43494 to look at the new patch set (#4). Change subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode ...................................................................... soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode Update the COS mask calculation to accomodate the RW data as per SoC configuration. Currently only one way is allocated for RW data and configured for non-eviction. For earlier platform this served fine, and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a single way. Hence update the number of ways to be configured for non- eviction as per total LLC size. The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/ way size gives the number of ways that need to be configured for non- eviction, instead of harcoding it to 1. TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892) as COS mask selection register and hence needs to be progarmmed accordingly. Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33 of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before MSR write instead of eax(maps 31:0). This implementation corrects that as well. BUG=b:149273819 TEST= Boot waddledoo(JSL), hatch(CML) with NEM enhanced CAR configuration. Pending test on ICL, TGL, KBL, SKL. Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 --- M src/include/cpu/x86/msr.h M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/car/cache_as_ram.S M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/skylake/Kconfig 7 files changed, 119 insertions(+), 43 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/43494/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/43494 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Gerrit-Change-Number: 43494 Gerrit-PatchSet: 4 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: Usha P <usha.p(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-MessageType: newpatchset

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Change in coreboot[master]: mb/clevo/n141cu: Add new Comet Lake mainboard
by Michael Niewöhner (Code Review) 11 Aug '20

11 Aug '20

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/40581 ) Change subject: mb/clevo/n141cu: Add new Comet Lake mainboard ...................................................................... Patch Set 36: (1 comment) https://review.coreboot.org/c/coreboot/+/40581/36//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/40581/36//COMMIT_MSG@25 PS36, Line 25: The ACPI code has been taken from System76 CML-U mainboard series. probably they won't work 100% on the stock ec; I will check that with L14xCU but I'm pretty sure we can do acpi platform-specific (cml, kbl, ...) or even more generic, since they are veeeeeery similiar -- To view, visit https://review.coreboot.org/c/coreboot/+/40581 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9f83fab64e4cc9036698ca0fdd5edbb677d77eb9 Gerrit-Change-Number: 40581 Gerrit-PatchSet: 36 Gerrit-Owner: Felix Singer <felixsinger(a)posteo.net> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Michael Niewöhner Gerrit-Comment-Date: Tue, 11 Aug 2020 12:16:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Add comments
by Patrick Rudolph (Code Review) 11 Aug '20

11 Aug '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40947 ) Change subject: nb/intel/sandybridge/raminit: Add comments ...................................................................... nb/intel/sandybridge/raminit: Add comments Add comments found when testing ECC scrubbing code. This is a cosmetic change. Change-Id: I7975f6070c2002930eec407a6b101a1295495b25 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit_common.c 1 file changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/40947/1 diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index e80abe7..609204e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -298,8 +298,14 @@ reg |= (dimmB->width / 8 - 1) << 20; } - reg |= 1 << 21; /* Rank interleave */ - reg |= 1 << 22; /* Enhanced interleave */ + /* + * Rank interleave: Bit 16 of the physical address space sets + * the rank to use in a dual single rank DIMM configuration. + * That results in every 64KiB being interleaved between two ranks. + */ + reg |= 1 << 21; + /* Enhanced interleave */ + reg |= 1 << 22; if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { ctrl->mad_dimm[channel] = reg; -- To view, visit https://review.coreboot.org/c/coreboot/+/40947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I7975f6070c2002930eec407a6b101a1295495b25 Gerrit-Change-Number: 40947 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib: Add ASan support to ramstage on x86 arch
by Werner Zeh (Code Review) 11 Aug '20

11 Aug '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42496 ) Change subject: lib: Add ASan support to ramstage on x86 arch ...................................................................... Patch Set 26: Code-Review+1 (2 comments) https://review.coreboot.org/c/coreboot/+/42496/26/src/include/asan.h File src/include/asan.h: https://review.coreboot.org/c/coreboot/+/42496/26/src/include/asan.h@42 PS26, Line 42: Would you mind to align this comment properly with the line before? https://review.coreboot.org/c/coreboot/+/42496/26/src/include/asan.h@45 PS26, Line 45: Same here. -- To view, visit https://review.coreboot.org/c/coreboot/+/42496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Gerrit-Change-Number: 42496 Gerrit-PatchSet: 26 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Tue, 11 Aug 2020 06:48:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: lib: Add ASan stub
by Werner Zeh (Code Review) 11 Aug '20

11 Aug '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42271 ) Change subject: lib: Add ASan stub ...................................................................... Patch Set 12: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42271 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6d87e48b6786f02dd46ea74e702f294082fd8891 Gerrit-Change-Number: 42271 Gerrit-PatchSet: 12 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Tue, 11 Aug 2020 06:33:28 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: crossgcc: Allow GCC to get asan shadow offset at runtime
by Werner Zeh (Code Review) 11 Aug '20

11 Aug '20

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42794 ) Change subject: crossgcc: Allow GCC to get asan shadow offset at runtime ...................................................................... Patch Set 18: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 18 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Tue, 11 Aug 2020 06:33:16 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: nb/intel/sandybridge/raminit: Fix ECC scrub
by Patrick Rudolph (Code Review) 11 Aug '20

11 Aug '20

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/40721 ) Change subject: nb/intel/sandybridge/raminit: Fix ECC scrub ...................................................................... nb/intel/sandybridge/raminit: Fix ECC scrub The scrubbing method was never correct nor tested. Fix that by observations made on mrc.bin. * Add ECC test code when DEBUG_RAM_SETUP * Move ECC srubbing after set_scrambling_seed() to be able to observe what has been cleared. * ECC scrubbing must happen after dram_dimm_set_mapping() * Move method out of try_init_dram_ddr3() * Add comments with observations made while fixing the code Tested on HPZ220 with ECC memory and XeonE3 CPU: The whole memory is now scrubbed. Change-Id: Ia9fcc236fbf73f51fe944c6dda5d22ba9d334ec7 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/northbridge/intel/sandybridge/raminit.c M src/northbridge/intel/sandybridge/raminit_common.c M src/northbridge/intel/sandybridge/raminit_native.c 3 files changed, 82 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/40721/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 6c8145d..2b0cb5e 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -366,10 +366,37 @@ set_scrambling_seed(&ctrl); + if (!s3resume && ctrl.ecc_enabled) + channel_scrub(&ctrl); + set_normal_operation(&ctrl); final_registers(&ctrl); + if (CONFIG(DEBUG_RAM_SETUP) && !s3resume && ctrl.ecc_enabled) { + /* Test ECC in normal mode! */ + + uint32_t tseg = pci_read_config32(HOST_BRIDGE, TSEGMB); + int i; + + printk(BIOS_INFO, "RAMINIT: ECC scrub test on first channel up to 0x%x\n", + tseg); + + /* Skip A-seg and test up to TSEG */ + for (i = 1; i < tseg >> 20; i++) { + for (int j = 0; j < 1 * MiB; j += 4096) { + uintptr_t addr = (i * MiB) + j; + if (read32((u32 *)addr) == 0) + continue; + + printk(BIOS_ERR, "RAMINIT: DRAM not clear at addr 0x%lx\n", + addr); + break; + } + } + printk(BIOS_INFO, "RAMINIT: ECC scrub test done.\n"); + } + /* Zone config */ dram_zones(&ctrl, 0); diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 087ba2b..9cbc769 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -18,8 +18,9 @@ /* FIXME: no support for 3-channel chipsets */ -/* length: [1..4] */ -#define IOSAV_RUN_ONCE(length) ((((length) - 1) << 18) | 1) +/* length: [1..4], repeat: [1..255] */ +#define IOSAV_RUN_MULTIPLE(length, repeat) ((((length) - 1) << 18) | (repeat)) +#define IOSAV_RUN_ONCE(length) IOSAV_RUN_MULTIPLE(length, 1) static void sfence(void) { @@ -297,8 +298,14 @@ reg |= (dimmB->width / 8 - 1) << 20; } - reg |= 1 << 21; /* Rank interleave */ - reg |= 1 << 22; /* Enhanced interleave */ + /* + * Rank interleave: Bit 16 of the physical address space sets + * the rank to use in a dual single rank DIMM configuration. + * That results in every 64KiB being interleaved between two ranks. + */ + reg |= 1 << 21; + /* Enhanced interleave */ + reg |= 1 << 22; if ((dimmA && (dimmA->ranks > 0)) || (dimmB && (dimmB->ranks > 0))) { ctrl->mad_dimm[channel] = reg; @@ -322,7 +329,7 @@ MCHBAR32(MAD_DIMM(channel)) = ctrl->mad_dimm[channel] | ecc; } - //udelay(10); /* TODO: Might be needed for ECC configurations; so far works without. */ + udelay(10); } void dram_zones(ramctr_timing *ctrl, int training) @@ -2948,39 +2955,56 @@ void channel_scrub(ramctr_timing *ctrl) { int channel, slotrank, row, rowsize; + u8 bank; + + + FOR_ALL_POPULATED_CHANNELS { + wait_for_iosav(channel); + fill_pattern0(ctrl, channel, 0, 0); + MCHBAR32(IOSAV_DATA_CTL_ch(channel)) = 0; + } FOR_ALL_POPULATED_CHANNELS FOR_ALL_POPULATED_RANKS { - rowsize = 1 << ctrl->info.dimm[channel][slotrank >> 1].row_bits; - for (row = 0; row < rowsize; row += 16) { + rowsize = 1 << ctrl->info.dimm[channel][!!(slotrank & 0xC)].row_bits; + /* Guessed based on oberservation: + * Writes 128 * 8 bytes + * Bank bits are located at 13:15 + * Rowbits start at bit 20 + */ + for (bank = 0; bank < 8; bank ++) { + for (row = 0; row < rowsize; row += 16) { - wait_for_iosav(channel); + /* DRAM command ACT */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = + (ctrl->tRCD << 16) | + (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) + | 1; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = + row | 0x60000 | (slotrank << 24) | (bank << 20); + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x00000241; - /* DRAM command ACT */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 0)) = IOSAV_ACT; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 0)) = - (MAX((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10) - | 1 | (ctrl->tRCD << 16); - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 0)) = - row | 0x00060000 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 0)) = 0x00000241; + /* DRAM command WR */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x08000000 | + ((ctrl->tWTR + ctrl->CWL + 8) << 16) | (4 << 10) | 0x81; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = row | + (slotrank << 24) | (bank << 20); + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x00000122; - /* DRAM command WR */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 1)) = IOSAV_WR; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 1)) = 0x08281081; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 1)) = row | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 1)) = 0x00000242; + /* DRAM command PRE */ + MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_PRE; + MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x00000000 | + (ctrl->tRP << 16) | (4 << 10) | 1; + MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = 0x60000 | + (slotrank << 24) | (bank << 20) | 0x400; + MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x00000240; - /* DRAM command PRE */ - MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(channel, 2)) = IOSAV_PRE; - MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(channel, 2)) = 0x00280c01; - MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(channel, 2)) = - 0x00060400 | (slotrank << 24); - MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(channel, 2)) = 0x00000240; + /* execute command queue */ + MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_MULTIPLE(3, 16); - /* execute command queue */ - MCHBAR32(IOSAV_SEQ_CTL_ch(channel)) = IOSAV_RUN_ONCE(3); - - wait_for_iosav(channel); + wait_for_iosav(channel); + } } } } diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 832391f..34299a3 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -685,9 +685,6 @@ err = channel_test(ctrl); if (err) return err; - - if (ctrl->ecc_enabled) - channel_scrub(ctrl); } /* Set MAD-DIMM registers */ -- To view, visit https://review.coreboot.org/c/coreboot/+/40721 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia9fcc236fbf73f51fe944c6dda5d22ba9d334ec7 Gerrit-Change-Number: 40721 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2020