August 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: soc/intel/tigerlake: Add USB4 _DSM for retimer firmware upgrade support
by John Zhao (Code Review) Aug. 10, 2020

Aug. 10, 2020

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44347 ) Change subject: soc/intel/tigerlake: Add USB4 _DSM for retimer firmware upgrade support ...................................................................... soc/intel/tigerlake: Add USB4 _DSM for retimer firmware upgrade support There is need to upgrade retimer firmware even if USB4 link is not up. This change adds USB4 _DSM method to support retimer firmware upgrade. The retimer force power GPIO state is queried and set accordingly. BUG=b:162528868 TEST=Built and booted to kernel successfully on Volteer and TGLRVP. TBD with kernel driver update to validate retimer firmware upgrade. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I34006972124fa7b04380410669b0cb5051c4f518 --- M src/soc/intel/tigerlake/acpi/tcss_dma.asl 1 file changed, 75 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/44347/1 diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index da2e8fe..39d55e9 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -105,7 +105,81 @@ ) } +/* + * Retimer Device Specific Method + * + * Arg0: UUID (set to 61788900-c470-42bb-80f0-23a313864593) + * Arg1: Revision ID (set to 1) + * Arg2: Function Index + * 0: Query command implemented + * 1: Query force power enable state + * 2: Set force power state + * 0x3 - 0xffff: Reserved + * Arg3: A package containing parameters for the function specified + * by the UUID, revsion ID and functon index. + */ Method (_DSM, 4, Serialized) { - Return (Buffer() { 0 }) + Name (PWR, 0) + If (Arg0 == ToUUID("61788900-c470-42bb-80f0-23a313864593")) { + switch (ToInteger(Arg2)) { + /* + * Function Index: 0 - Standard query + * Return: Bitmask of supported functions + */ + case (0) { + If (Arg1 == 1) { + /* Support all functions */ + Return (Buffer() { 0x07 }) + } + + /* Only support query if unknown revision */ + Return (Buffer() { 0x01 }) + } + + /* + * Function Index: 1 - Query force power state + * Arg3: Empty package + * Return: 0 - if force power is disabled + * 1 - if force power is enabled + */ + case (1) { + Return (PWR) + } + + /* + * Function Index: 2 - Set force power state + * Arg3: A package consisting a single integer + * 0: Turn off power + * 1: Turn on powe + * Return: 0 + */ + case (2) { + CreateDWordField (Arg3, 0, CDW1) + If (CDW1 == PWR) { + /* Already in the state */ + Return (0) + } + + If (CDW1 == 0) { + /* Turn off power to the retimer */ + CTXS(RT_FORCE_PWR) + } ElseIf (CDW1 == 1) { + /* Turn on power to the retimer */ + STXS(RT_FORCE_PWR) + } Else { + Return (0) + } + + PWR = CDW1 + Return (0) + } + + Default { + Return (Buffer() { 0 }) + } + } + } Else { + Return (Buffer() { 0 }) + } } -- To view, visit https://review.coreboot.org/c/coreboot/+/44347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I34006972124fa7b04380410669b0cb5051c4f518 Gerrit-Change-Number: 44347 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/volteer: Configure GPIO GPP_H10 for retimer force power
by John Zhao (Code Review) Aug. 10, 2020

Aug. 10, 2020

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44346 ) Change subject: mb/google/volteer: Configure GPIO GPP_H10 for retimer force power ...................................................................... mb/google/volteer: Configure GPIO GPP_H10 for retimer force power Retimer needs to be powered on during its firmware upgrade. This change configures the retimer force power GPIO to be output and 0 initially. This retimer force power GPIO will be set high during firmware upgrade and back to low once finished. BUG=b:162528868 TEST=Built and booted to kernel successfully on Volteer. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I2938882aa84a78b30da3b32cee7157bee389d37c --- M src/mainboard/google/volteer/variants/baseboard/gpio.c M src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h 2 files changed, 4 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/44346/1 diff --git a/src/mainboard/google/volteer/variants/baseboard/gpio.c b/src/mainboard/google/volteer/variants/baseboard/gpio.c index ad17a94..430203f 100644 --- a/src/mainboard/google/volteer/variants/baseboard/gpio.c +++ b/src/mainboard/google/volteer/variants/baseboard/gpio.c @@ -306,7 +306,7 @@ /* H9 : I2C4_SCL ==> NC */ PAD_NC(GPP_H9, NONE), /* H10 : SRCCLKREQ4# ==> USB_C1_RT_FORCE_PWR */ - PAD_CFG_GPO(GPP_H10, 1, DEEP), + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* H11 : SRCCLKREQ5# ==> NC */ PAD_NC(GPP_H11, NONE), /* H12 : M2_SKT2_CFG0 ==> NONE */ diff --git a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h index 4e2733e..7a34acd 100644 --- a/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/google/volteer/variants/baseboard/include/baseboard/gpio.h @@ -30,4 +30,7 @@ /* DRAM population strap (value 0=fully-populated, 1=half-populated) */ #define GPIO_MEM_CH_SEL GPP_A17 +/* Retimer force power */ +#define RT_FORCE_PWR GPP_H10 + #endif /* BASEBOARD_GPIO_H */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44346 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2938882aa84a78b30da3b32cee7157bee389d37c Gerrit-Change-Number: 44346 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: mb/intel/tglrvp: Configure GPIO GPP_A23 for retimer force power
by John Zhao (Code Review) Aug. 10, 2020

Aug. 10, 2020

John Zhao has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44345 ) Change subject: mb/intel/tglrvp: Configure GPIO GPP_A23 for retimer force power ...................................................................... mb/intel/tglrvp: Configure GPIO GPP_A23 for retimer force power Retimer needs to be powered on during its firmware upgrade. This change configures the retimer force power GPIO to be output and 0 initially. This retimer force power GPIO will be set high during firmware upgrade and back to low once finished. BUG=b:162528868 TEST=Built and booted to kernel successfully on TGLRVP board. Signed-off-by: John Zhao <john.zhao(a)intel.com> Change-Id: I2cb4414cf846ee9a5b0ae05140818da46490fb35 --- M src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h M src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c M src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c 3 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/44345/1 diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h index de0adf6..6b7aeaf 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h @@ -12,4 +12,7 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK +/* Retimer force power */ +#define RT_FORCE_PWR GPP_A23 + #endif /* __BASEBOARD_GPIO_H__ */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index 4457506..66a2d99 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -54,6 +54,9 @@ /* CNVi */ PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */ PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */ + + /* Retimer force power */ + PAD_CFG_GPO(GPP_A23, 0, DEEP), }; /* Early pad configuration in bootblock */ diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c index 679933a..aa33d5a 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/gpio.c @@ -51,6 +51,8 @@ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* I2S_MCLK1 */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* I2S_MCLK2 */ + /* Retimer force power */ + PAD_CFG_GPO(GPP_A23, 0, DEEP), }; /* Early pad configuration in bootblock */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44345 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2cb4414cf846ee9a5b0ae05140818da46490fb35 Gerrit-Change-Number: 44345 Gerrit-PatchSet: 1 Gerrit-Owner: John Zhao <john.zhao(a)intel.com> Gerrit-MessageType: newchange

1 0

Change in coreboot[master]: crossgcc: Allow GCC to get asan shadow offset at runtime
by Werner Zeh (Code Review) Aug. 10, 2020

Aug. 10, 2020

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42794 ) Change subject: crossgcc: Allow GCC to get asan shadow offset at runtime ...................................................................... Patch Set 17: Code-Review+1 (5 comments) OK, let's clean up some typos and bring this patch in. https://review.coreboot.org/c/coreboot/+/42794/17//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42794/17//COMMIT_MSG@11 PS17, Line 11: , Not needed. https://review.coreboot.org/c/coreboot/+/42794/17//COMMIT_MSG@11 PS17, Line 11: at each stage By "thus" a few words earlier you already mean "multiple stages". So no need to mention it here again, just skip these words. https://review.coreboot.org/c/coreboot/+/42794/17//COMMIT_MSG@16 PS17, Line 16: a callback function Maybe better "... a callback function named __asan_shadow_offset()"? https://review.coreboot.org/c/coreboot/+/42794/17//COMMIT_MSG@26 PS17, Line 26: the build fails "the build will fail." https://review.coreboot.org/c/coreboot/+/42794/17//COMMIT_MSG@34 PS17, Line 34: , Not needed here. -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 17 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Raul Rangel <rrangel(a)chromium.org> Gerrit-Comment-Date: Mon, 10 Aug 2020 17:00:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

1 0

Change in coreboot[master]: [TEST]mb/google/dedede: Reduce PL1
by Krishna P Bhat D (Code Review) Aug. 10, 2020

Aug. 10, 2020

Krishna P Bhat D has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43965 ) Change subject: [TEST]mb/google/dedede: Reduce PL1 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/43965 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I42b834ee5e393ca524d12c77e7c4baa5bd37c78f Gerrit-Change-Number: 43965 Gerrit-PatchSet: 1 Gerrit-Owner: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

1 0

Change in coreboot[master]: md/tgl: Enable SaGv for TGL-U RVP
by Shreesh Chhabbi (Code Review) Aug. 10, 2020

Aug. 10, 2020

Hello Shreesh Chhabbi, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/43276 to review the following change. Change subject: md/tgl: Enable SaGv for TGL-U RVP ...................................................................... md/tgl: Enable SaGv for TGL-U RVP Change-Id: I5b84457a1455edfe500ce80ba7f7ca6ccce43666 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/43276/1 diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4010772..ff3c96c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -13,7 +13,7 @@ register "pmc_gpe0_dw2" = "GPP_E" # FSP configuration - register "SaGv" = "SaGv_Disabled" + register "SaGv" = "SaGv_Enabled" register "SmbusEnable" = "1" register "usb2_ports[0]" = "USB2_PORT_MID(OC0)" # Type-C Port1 -- To view, visit https://review.coreboot.org/c/coreboot/+/43276 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5b84457a1455edfe500ce80ba7f7ca6ccce43666 Gerrit-Change-Number: 43276 Gerrit-PatchSet: 1 Gerrit-Owner: Shreesh Chhabbi <shreesh.chhabbi(a)intel.com> Gerrit-Reviewer: Shreesh Chhabbi <shreesh.chhabbi(a)intel.corp-partner.google.com> Gerrit-MessageType: newchange

5 9

Change in coreboot[master]: superio/ite: allow 24 MHz clock for external sensor interface
by Michael (Code Review) Aug. 10, 2020

Aug. 10, 2020

Michael has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44166 ) Change subject: superio/ite: allow 24 MHz clock for external sensor interface ...................................................................... superio/ite: allow 24 MHz clock for external sensor interface The interface selection register of the environment controller (EC) gives the choice between "Internal generated 32 MHz" and "24 MHz" for the "SST/PECI Host Controller Clock Selection". Previously the chip was always configured for the 32 MHz clock. Add an option that can be set from devicetree.cb to allow using the 24 MHz clock. Without this setting the automatic fan control on an Acer Aspire M3800 was slow to respond to temperature changes. Signed-off-by: Michael Büchler <michael.buechler(a)posteo.net> Change-Id: Ib2bce10a828fb4a7d837f6c5f5b1d00cc51be0ce --- M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl_chip.h 2 files changed, 12 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/44166/1 diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index 52981ec..a281ab6 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -262,6 +262,13 @@ ITE_EC_INTERFACE_SMB_ENABLE); } + /* Set SST/PECI Host Controller Clock to either 24 MHz or internal 32 MHz */ + if (conf->smbus_24mhz) { + pnp_write_hwm5_index(base, ITE_EC_INTERFACE_SELECT, + pnp_read_hwm5_index(base, ITE_EC_INTERFACE_SELECT) | + ITE_EC_INTERFACE_CLOCK_24MHZ); + } + /* Enable reading of voltage pins */ pnp_write_hwm5_index(base, ITE_EC_ADC_VOLTAGE_CHANNEL_ENABLE, conf->vin_mask); diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index 5f824be..149832d 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -92,6 +92,11 @@ * Enable SMBus for external thermal sensor. */ bool smbus_en; + /* + * Select 24 MHz clock for external host instead of an + * internally generated 32 MHz clock. + */ + bool smbus_24mhz; }; /* Some shorthands for device trees */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44166 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ib2bce10a828fb4a7d837f6c5f5b1d00cc51be0ce Gerrit-Change-Number: 44166 Gerrit-PatchSet: 1 Gerrit-Owner: Michael <michael.buechler(a)posteo.net> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

3 3

Change in coreboot[master]: superio/ite: configure EC for fans to full at thermal limit
by Michael (Code Review) Aug. 10, 2020

Aug. 10, 2020

Michael has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44165 ) Change subject: superio/ite: configure EC for fans to full at thermal limit ...................................................................... superio/ite: configure EC for fans to full at thermal limit This applies to the automatic fan control mode of the environment controller (EC). Previously the affected bit was always cleared while the default value is 1 according to datasheets. Add a variable that can be set per mainboard in devicetree.cb. In the IT8783E datasheet that bit is marked as reserved. Signed-off-by: Michael Büchler <michael.buechler(a)posteo.net> Change-Id: Ie74102ac0d54be33558c161c9c84594d121772b1 --- M src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb M src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/libretrend/lt1000/devicetree.cb M src/mainboard/roda/rv11/variants/rw11/devicetree.cb M src/superio/ite/common/env_ctrl.c M src/superio/ite/common/env_ctrl.h M src/superio/ite/common/env_ctrl_chip.h 10 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/44165/1 diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb index 08a74e8..11c4186 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m.cb @@ -49,6 +49,7 @@ register "FAN1.smart.tmp_start" = "20" register "FAN1.smart.tmp_full" = "70" register "FAN1.smart.tmp_delta" = "0" + register "FAN1.smart.full_lmt" = "0" register "FAN1.smart.smoothing" = "1" register "FAN1.smart.pwm_start" = "20" register "FAN1.smart.slope" = "32" diff --git a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb index bc0dc42..a1b1917 100644 --- a/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb +++ b/src/mainboard/asus/f2a85-m/devicetree_f2a85-m_le.cb @@ -49,6 +49,7 @@ register "FAN1.smart.tmp_start" = "20" register "FAN1.smart.tmp_full" = "70" register "FAN1.smart.tmp_delta" = "0" + register "FAN1.smart.full_lmt" = "0" register "FAN1.smart.smoothing" = "1" register "FAN1.smart.pwm_start" = "20" register "FAN1.smart.slope" = "32" diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 9bde4b2..89a801c 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -65,6 +65,7 @@ register "FAN1.smart.tmp_start" = "30" register "FAN1.smart.tmp_full" = "65" register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.full_lmt" = "0" register "FAN1.smart.smoothing" = "1" register "FAN1.smart.pwm_start" = "20" register "FAN1.smart.slope" = "10" @@ -74,6 +75,7 @@ register "FAN2.smart.tmp_start" = "30" register "FAN2.smart.tmp_full" = "65" register "FAN2.smart.tmp_delta" = "3" + register "FAN2.smart.full_lmt" = "0" register "FAN2.smart.smoothing" = "1" register "FAN2.smart.pwm_start" = "20" register "FAN2.smart.slope" = "10" diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index c0f198f..f80c02d 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -111,6 +111,7 @@ register "FAN1.smart.tmp_start" = "35" register "FAN1.smart.tmp_full" = "75" register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.full_lmt" = "0" register "FAN1.smart.smoothing" = "1" register "FAN1.smart.pwm_start" = "0" register "FAN1.smart.slope" = "10" @@ -121,6 +122,7 @@ register "FAN2.smart.tmp_start" = "35" register "FAN2.smart.tmp_full" = "75" register "FAN2.smart.tmp_delta" = "3" + register "FAN2.smart.full_lmt" = "0" register "FAN2.smart.smoothing" = "1" register "FAN2.smart.pwm_start" = "0" register "FAN2.smart.slope" = "10" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 6328bc6..d61342c 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -81,6 +81,7 @@ register "FAN1.smart.tmp_start" = "30" register "FAN1.smart.tmp_full" = "65" register "FAN1.smart.tmp_delta" = "3" + register "FAN1.smart.full_lmt" = "0" register "FAN1.smart.smoothing" = "1" register "FAN1.smart.pwm_start" = "0" register "FAN1.smart.slope" = "10" @@ -91,6 +92,7 @@ register "FAN2.smart.tmp_start" = "30" register "FAN2.smart.tmp_full" = "65" register "FAN2.smart.tmp_delta" = "3" + register "FAN2.smart.full_lmt" = "0" register "FAN2.smart.smoothing" = "1" register "FAN2.smart.pwm_start" = "0" register "FAN2.smart.slope" = "10" diff --git a/src/mainboard/libretrend/lt1000/devicetree.cb b/src/mainboard/libretrend/lt1000/devicetree.cb index a58e169..7fa941a 100644 --- a/src/mainboard/libretrend/lt1000/devicetree.cb +++ b/src/mainboard/libretrend/lt1000/devicetree.cb @@ -220,6 +220,7 @@ register "FAN1.smart.tmp_start" = "60" register "FAN1.smart.tmp_full" = "85" register "FAN1.smart.tmp_delta" = " 2" + register "FAN1.smart.full_lmt" = " 0" register "FAN1.smart.pwm_start" = "20" register "FAN1.smart.slope" = "24" # FAN2 is system fan (4 pin connector populated) diff --git a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb index 988c2a6..3e28ba8 100644 --- a/src/mainboard/roda/rv11/variants/rw11/devicetree.cb +++ b/src/mainboard/roda/rv11/variants/rw11/devicetree.cb @@ -105,6 +105,7 @@ register "FAN1.smart.tmp_off" = "60" register "FAN1.smart.tmp_start" = "64" register "FAN1.smart.tmp_delta" = " 2" + register "FAN1.smart.full_lmt" = " 0" register "FAN1.smart.pwm_start" = "30" register "FAN1.smart.slope" = "64" register "FAN2.mode" = "FAN_SMART_AUTOMATIC" @@ -112,6 +113,7 @@ register "FAN2.smart.tmp_off" = "60" register "FAN2.smart.tmp_start" = "64" register "FAN2.smart.tmp_delta" = " 2" + register "FAN2.smart.full_lmt" = " 0" register "FAN2.smart.pwm_start" = "30" register "FAN2.smart.slope" = "64" register "FAN3.mode" = "FAN_MODE_OFF" diff --git a/src/superio/ite/common/env_ctrl.c b/src/superio/ite/common/env_ctrl.c index f63bfd3..52981ec 100644 --- a/src/superio/ite/common/env_ctrl.c +++ b/src/superio/ite/common/env_ctrl.c @@ -147,6 +147,8 @@ conf->tmp_full ? conf->tmp_full : 127); pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_DELTA_TEMP(fan), ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(conf->tmp_delta)); + pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_DELTA_TEMP(fan), + ITE_EC_FAN_CTL_FULL_AT_THRML_LMT(conf->full_lmt)); } pnp_write_hwm5_index(base, ITE_EC_FAN_CTL_PWM_CONTROL(fan), pwm_ctrl); diff --git a/src/superio/ite/common/env_ctrl.h b/src/superio/ite/common/env_ctrl.h index e8fb1f5..7bce809 100644 --- a/src/superio/ite/common/env_ctrl.h +++ b/src/superio/ite/common/env_ctrl.h @@ -185,6 +185,7 @@ /* Common for ITE_EC_FAN_CTL_DELTA_TEMP */ #define ITE_EC_FAN_CTL_DELTA_TEMP_INTRVL(c) ((c) & 0x1f) +#define ITE_EC_FAN_CTL_FULL_AT_THRML_LMT(x) (((x) & 0x1) << 6) #define ITE_EC_FAN_CTL_TARGET_ZONE(x) (0x66 + ((x)-1) * 8) #define ITE_EC_FAN_CTL_TARGET_ZONE_MASK 0x0f diff --git a/src/superio/ite/common/env_ctrl_chip.h b/src/superio/ite/common/env_ctrl_chip.h index 6a027b9..5f824be 100644 --- a/src/superio/ite/common/env_ctrl_chip.h +++ b/src/superio/ite/common/env_ctrl_chip.h @@ -56,6 +56,8 @@ u8 tmp_full; /* 100% duty cycle above (°C) */ u8 tmp_delta; /* adapt fan speed when temperature changed by at least `tmp_delta`°C */ + u8 full_lmt; /* force fan to full PWM at thermal + limit */ u8 smoothing; /* enable smoothing */ u8 pwm_start; /* start at this duty cycle (%) */ u8 slope; /* increase duty cycle by `slope`%/°C */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44165 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie74102ac0d54be33558c161c9c84594d121772b1 Gerrit-Change-Number: 44165 Gerrit-PatchSet: 1 Gerrit-Owner: Michael <michael.buechler(a)posteo.net> Gerrit-MessageType: newchange

5 11

Change in coreboot[master]: soc/intel/skylake/acpi.c: Name devices on secondary bus
by Benjamin Doron (Code Review) Aug. 10, 2020

Aug. 10, 2020

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph, Angel Pons, Evgeny Zinoviev, Patrick Rudolph, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43074 to look at the new patch set (#6). Change subject: soc/intel/skylake/acpi.c: Name devices on secondary bus ...................................................................... soc/intel/skylake/acpi.c: Name devices on secondary bus Naming a device allows an ACPI _ROM method to be written for it. GPUs may require this to make the configuration data contained within available to an OS driver. This may be required for GPUs that do not contain their vBIOS, or perhaps the drivers require it in this form/fashion. Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully obtains the vBIOS via ACPI (kernel 5.7.11). Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/include/soc/pci_devs.h 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/43074/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/43074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Gerrit-Change-Number: 43074 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Prasun Gera Gerrit-MessageType: newpatchset

1 0

Change in coreboot[master]: soc/intel/skylake/acpi.c: Name devices on secondary bus
by Benjamin Doron (Code Review) Aug. 10, 2020

Aug. 10, 2020

Hello build bot (Jenkins), Patrick Georgi, Martin Roth, Patrick Rudolph, Angel Pons, Evgeny Zinoviev, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/43074 to look at the new patch set (#5). Change subject: soc/intel/skylake/acpi.c: Name devices on secondary bus ...................................................................... soc/intel/skylake/acpi.c: Name devices on secondary bus Naming a device allows an ACPI _ROM method to be written for it. GPUs may require this to make the configuration data contained within available to an OS driver. This may be required for GPUs that do not contain their vBIOS, or perhaps the drivers require it in this form/fashion. Working on an Acer Aspire VN7-572G (Skylake-U). nouveau successfully obtains the vBIOS via ACPI. Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Signed-off-by: Benjamin Doron <benjamin.doron00(a)gmail.com> --- M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/include/soc/pci_devs.h 2 files changed, 14 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/43074/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/43074 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ida87aebf8fdf341ab350c2bb3704d2ef695cf8f0 Gerrit-Change-Number: 43074 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Evgeny Zinoviev <me(a)ch1p.io> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jeremy Soller <jeremy(a)system76.com> Gerrit-CC: Patrick Rudolph <siro(a)das-labor.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-CC: Prasun Gera Gerrit-MessageType: newpatchset

1 0