coreboot-gerrit August 2020

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Change in coreboot[master]: cpu/amd/{agesa,pi}: Factor out common settings
by Angel Pons (Code Review) 09 Aug '20

09 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44233 ) Change subject: cpu/amd/{agesa,pi}: Factor out common settings ...................................................................... cpu/amd/{agesa,pi}: Factor out common settings Change-Id: I1dbf7514f8fa1a66eeb8a9e7c737df2667bb878b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/amd/agesa/Kconfig M src/cpu/amd/agesa/family14/Kconfig M src/cpu/amd/agesa/family15tn/Kconfig M src/cpu/amd/agesa/family16kb/Kconfig M src/cpu/amd/pi/00630F01/Kconfig M src/cpu/amd/pi/00660F01/Kconfig M src/cpu/amd/pi/00730F01/Kconfig M src/cpu/amd/pi/Kconfig 8 files changed, 12 insertions(+), 36 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/44233/1 diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 499cc5b..f8b924f 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -10,6 +10,12 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select CPU_X86_CACHE + select CPU_X86_LAPIC + select CPU_X86_MTRR + select CPU_X86_SMM + select CPU_X86_TSC + select X86_AMD_FIXED_MTRRS select DRIVERS_AMD_PI select TSC_SYNC_LFENCE select UDELAY_LAPIC diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 8667602..7fc917a 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -2,12 +2,6 @@ config CPU_AMD_AGESA_FAMILY14 bool - select CPU_X86_CACHE - select CPU_X86_LAPIC - select CPU_X86_MTRR - select CPU_X86_SMM - select CPU_X86_TSC - select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 4b6b40e..eb267df 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -2,12 +2,6 @@ config CPU_AMD_AGESA_FAMILY15_TN bool - select CPU_X86_CACHE - select CPU_X86_LAPIC - select CPU_X86_MTRR - select CPU_X86_SMM - select CPU_X86_TSC - select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_TN diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 1b43dbe..3342984 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -2,12 +2,6 @@ config CPU_AMD_AGESA_FAMILY16_KB bool - select CPU_X86_CACHE - select CPU_X86_LAPIC - select CPU_X86_MTRR - select CPU_X86_SMM - select CPU_X86_TSC - select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY16_KB diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index db921c3..b811f87 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -2,12 +2,6 @@ config CPU_AMD_PI_00630F01 bool - select CPU_X86_CACHE - select CPU_X86_LAPIC - select CPU_X86_MTRR - select CPU_X86_SMM - select CPU_X86_TSC - select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00630F01 diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index 859dda0..d56b063 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -2,12 +2,6 @@ config CPU_AMD_PI_00660F01 bool - select CPU_X86_CACHE - select CPU_X86_LAPIC - select CPU_X86_MTRR - select CPU_X86_SMM - select CPU_X86_TSC - select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00660F01 diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index c8c6e0a..96faa64 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -2,12 +2,6 @@ config CPU_AMD_PI_00730F01 bool - select CPU_X86_CACHE - select CPU_X86_LAPIC - select CPU_X86_MTRR - select CPU_X86_SMM - select CPU_X86_TSC - select X86_AMD_FIXED_MTRRS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_UNDISCLOSED diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 533507e..968431d 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -10,6 +10,12 @@ select ARCH_VERSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 + select CPU_X86_CACHE + select CPU_X86_LAPIC + select CPU_X86_MTRR + select CPU_X86_SMM + select CPU_X86_TSC + select X86_AMD_FIXED_MTRRS select DRIVERS_AMD_PI select TSC_SYNC_LFENCE select UDELAY_LAPIC -- To view, visit https://review.coreboot.org/c/coreboot/+/44233 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I1dbf7514f8fa1a66eeb8a9e7c737df2667bb878b Gerrit-Change-Number: 44233 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

1 3

Change in coreboot[master]: src: Drop meaningless `CPU_X86_TSC` symbol
by Angel Pons (Code Review) 09 Aug '20

09 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44313 ) Change subject: src: Drop meaningless `CPU_X86_TSC` symbol ...................................................................... src: Drop meaningless `CPU_X86_TSC` symbol The CPUs currently selecting it do not select `UDELAY_TSC`. Change-Id: Ie9961228ff0f32bb5ea7fdf4f0dc06adba35b122 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/amd/agesa/family14/Kconfig M src/cpu/amd/agesa/family15tn/Kconfig M src/cpu/amd/agesa/family16kb/Kconfig M src/cpu/amd/pi/00630F01/Kconfig M src/cpu/amd/pi/00660F01/Kconfig M src/cpu/amd/pi/00730F01/Kconfig M src/cpu/x86/Kconfig M src/cpu/x86/Makefile.inc M src/soc/amd/stoneyridge/Kconfig 9 files changed, 1 insertion(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44313/1 diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 8667602..de8e326 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -6,7 +6,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 4b6b40e..df7ac26 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -6,7 +6,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_TN diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 1b43dbe..0cafdf5 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -6,7 +6,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY16_KB diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index db921c3..65f66df 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -6,7 +6,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00630F01 diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index 859dda0..4b7a665 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -6,7 +6,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00660F01 diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index c8c6e0a..4247189 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -6,7 +6,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select X86_AMD_FIXED_MTRRS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_UNDISCLOSED diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 8d1dfa6..dddd911 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -14,10 +14,6 @@ bool default n -config CPU_X86_TSC - bool - default n - # TODO These two options look too similar config PARALLEL_CPU_INIT bool @@ -53,7 +49,6 @@ config UDELAY_TSC bool default n - select CPU_X86_TSC config UNKNOWN_TSC_RATE bool diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index c661d4a..258a405 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -3,7 +3,7 @@ subdirs-$(CONFIG_CPU_X86_LAPIC) += lapic subdirs-$(CONFIG_CPU_X86_MTRR) += mtrr subdirs-$(CONFIG_CPU_X86_SMM) += smm -subdirs-$(CONFIG_CPU_X86_TSC) += tsc +subdirs-y += tsc subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-y += backup_default_smm.c diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 64aec1f..59d2be5 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -16,7 +16,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select X86_AMD_FIXED_MTRRS select ACPI_AMD_HARDWARE_SLEEP_VALUES select COLLECT_TIMESTAMPS_NO_TSC -- To view, visit https://review.coreboot.org/c/coreboot/+/44313 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie9961228ff0f32bb5ea7fdf4f0dc06adba35b122 Gerrit-Change-Number: 44313 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: cpu/intel: Drop redundant `CPU_X86_TSC` from sockets
by Angel Pons (Code Review) 09 Aug '20

09 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44312 ) Change subject: cpu/intel: Drop redundant `CPU_X86_TSC` from sockets ...................................................................... cpu/intel: Drop redundant `CPU_X86_TSC` from sockets It is selected through `UDELAY_TSC` on the CPU models already. Change-Id: If859c02defc6caf4e952b50869f0a39eb4b46c31 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_BGA956/Kconfig M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_p/Kconfig 6 files changed, 0 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44312/1 diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index 8b4fdd1..c66e463 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -9,7 +9,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select MMX select SSE select SETUP_XIP_CACHE diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index da993f7..8b92d36 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -4,7 +4,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select MMX select SSE diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 71796ce..bb1e1a6 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -11,7 +11,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select MMX select SSE select CPU_HAS_L2_ENABLE_MSR diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 34eb5a2..ca0a513 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -12,7 +12,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select MMX select SSE select SIPI_VECTOR_IN_ROM diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 3676707..e13e1d0 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -10,7 +10,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select MMX select SSE diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index 3fba30b..6c8c3f7 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -5,7 +5,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select MMX select SSE -- To view, visit https://review.coreboot.org/c/coreboot/+/44312 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: If859c02defc6caf4e952b50869f0a39eb4b46c31 Gerrit-Change-Number: 44312 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: src: Select `CPU_X86_TSC` through `UDELAY_TSC`
by Angel Pons (Code Review) 09 Aug '20

09 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44311 ) Change subject: src: Select `CPU_X86_TSC` through `UDELAY_TSC` ...................................................................... src: Select `CPU_X86_TSC` through `UDELAY_TSC` The `CPU_X86_TSC` option does nothing if `UDELAY_TSC` is not enabled. Change-Id: Id2c55cc1b9e284694fff670a238c3c620f0f6c47 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/Kconfig M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/qemu-x86/Kconfig M src/cpu/x86/Kconfig M src/soc/amd/picasso/Kconfig M src/soc/intel/apollolake/Kconfig M src/soc/intel/baytrail/Kconfig M src/soc/intel/braswell/Kconfig M src/soc/intel/broadwell/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/icelake/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/quark/Kconfig M src/soc/intel/skylake/Kconfig M src/soc/intel/tigerlake/Kconfig M src/soc/intel/xeon_sp/Kconfig 20 files changed, 1 insertion(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/44311/1 diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index 6f84c99..e234cab 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -13,7 +13,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index d59afe9..9a7f6bb 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -13,7 +13,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index 239978d..cfb12d9 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -13,7 +13,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 4a246fb..ae48885 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -15,7 +15,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select NO_SMM select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 5c830b8..02145d5 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,7 +9,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select MMX select SSE select UDELAY_TSC diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index e45c1e21..6ab327f 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -9,7 +9,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select SMP select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index 5dad9dd..8d1dfa6 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -53,6 +53,7 @@ config UDELAY_TSC bool default n + select CPU_X86_TSC config UNKNOWN_TSC_RATE bool diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index dcb9cae..e6ed611 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -16,7 +16,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select RESET_VECTOR_IN_RAM select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 2358677..1b2337f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -32,7 +32,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select IOAPIC select PCR_COMMON_IOSF_1_0 select SMP diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index ed5cc90..1f7a804 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -17,7 +17,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index 1177292..c5ff0fa 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -17,7 +17,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select HAVE_SMI_HANDLER diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 2473728..bd810ad 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -20,7 +20,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 20482d0..9c7bad9 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -70,7 +70,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index a9899be..18dba59 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -18,7 +18,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select DEBUG_GPIO select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index 00ac262..b6453cd 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -19,7 +19,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 1527192..a3a673d 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -20,7 +20,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index ada39da..fa6861e 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -14,7 +14,6 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select CPU_X86_MTRR - select CPU_X86_TSC select NO_MMCONF_SUPPORT select REG_SCRIPT select PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 834cbe0..a753db8 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -32,7 +32,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index f902d8e..c3105c8 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -20,7 +20,6 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM - select CPU_X86_TSC select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 4f420e2..7ab0ed0 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -33,7 +33,6 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CPU_X86_LAPIC select CPU_X86_MTRR - select CPU_X86_TSC select POSTCAR_CONSOLE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET -- To view, visit https://review.coreboot.org/c/coreboot/+/44311 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id2c55cc1b9e284694fff670a238c3c620f0f6c47 Gerrit-Change-Number: 44311 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

1 1

Change in coreboot[master]: MAINTAINERS: Add myself to `Intel support`
by Angel Pons (Code Review) 09 Aug '20

09 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44303 ) Change subject: MAINTAINERS: Add myself to `Intel support` ...................................................................... MAINTAINERS: Add myself to `Intel support` I primarily battle with Intel platforms. Change-Id: Iddb46bf1d7e06bac7c5546502ad9f4dea8c358c1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M MAINTAINERS 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/44303/1 diff --git a/MAINTAINERS b/MAINTAINERS index 924247e..1bcaa89 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -489,6 +489,7 @@ INTEL SUPPORT M: Patrick Rudolph <siro(a)das-labor.org> +M: Angel Pons <th3fanbus(a)gmail.com> S: Maintained F: src/vendorcode/intel/ F: src/cpu/intel/ -- To view, visit https://review.coreboot.org/c/coreboot/+/44303 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iddb46bf1d7e06bac7c5546502ad9f4dea8c358c1 Gerrit-Change-Number: 44303 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: cpu/x86: Introduce `CPU_X86_TSC`
by Angel Pons (Code Review) 09 Aug '20

09 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44232 ) Change subject: cpu/x86: Introduce `CPU_X86_TSC` ...................................................................... cpu/x86: Introduce `CPU_X86_TSC` There's no need for relative paths with Kconfig options. Change-Id: Ie7d8229d23b3fa515e56f4a4541b246ac7a6fbc1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/amd/agesa/family14/Kconfig M src/cpu/amd/agesa/family14/Makefile.inc M src/cpu/amd/agesa/family15tn/Kconfig M src/cpu/amd/agesa/family15tn/Makefile.inc M src/cpu/amd/agesa/family16kb/Kconfig M src/cpu/amd/agesa/family16kb/Makefile.inc M src/cpu/amd/pi/00630F01/Kconfig M src/cpu/amd/pi/00630F01/Makefile.inc M src/cpu/amd/pi/00660F01/Kconfig M src/cpu/amd/pi/00660F01/Makefile.inc M src/cpu/amd/pi/00730F01/Kconfig M src/cpu/amd/pi/00730F01/Makefile.inc M src/cpu/intel/haswell/Kconfig M src/cpu/intel/haswell/Makefile.inc M src/cpu/intel/model_2065x/Kconfig M src/cpu/intel/model_2065x/Makefile.inc M src/cpu/intel/model_206ax/Kconfig M src/cpu/intel/model_206ax/Makefile.inc M src/cpu/intel/slot_1/Kconfig M src/cpu/intel/slot_1/Makefile.inc M src/cpu/intel/socket_441/Kconfig M src/cpu/intel/socket_441/Makefile.inc M src/cpu/intel/socket_BGA956/Kconfig M src/cpu/intel/socket_BGA956/Makefile.inc M src/cpu/intel/socket_FCBGA559/Kconfig M src/cpu/intel/socket_FCBGA559/Makefile.inc M src/cpu/intel/socket_LGA775/Kconfig M src/cpu/intel/socket_LGA775/Makefile.inc M src/cpu/intel/socket_m/Kconfig M src/cpu/intel/socket_m/Makefile.inc M src/cpu/intel/socket_mPGA604/Kconfig M src/cpu/intel/socket_mPGA604/Makefile.inc M src/cpu/intel/socket_p/Kconfig M src/cpu/intel/socket_p/Makefile.inc M src/cpu/qemu-x86/Kconfig M src/cpu/qemu-x86/Makefile.inc M src/cpu/x86/Kconfig M src/cpu/x86/Makefile.inc M src/soc/amd/picasso/Kconfig M src/soc/amd/picasso/Makefile.inc M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/Makefile.inc M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/baytrail/Kconfig M src/soc/intel/baytrail/Makefile.inc M src/soc/intel/braswell/Kconfig M src/soc/intel/braswell/Makefile.inc M src/soc/intel/broadwell/Kconfig M src/soc/intel/broadwell/Makefile.inc M src/soc/intel/cannonlake/Kconfig M src/soc/intel/cannonlake/Makefile.inc M src/soc/intel/denverton_ns/Kconfig M src/soc/intel/denverton_ns/Makefile.inc M src/soc/intel/icelake/Kconfig M src/soc/intel/icelake/Makefile.inc M src/soc/intel/jasperlake/Kconfig M src/soc/intel/jasperlake/Makefile.inc M src/soc/intel/quark/Kconfig M src/soc/intel/quark/Makefile.inc M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/tigerlake/Kconfig M src/soc/intel/tigerlake/Makefile.inc M src/soc/intel/xeon_sp/Kconfig M src/soc/intel/xeon_sp/cpx/Makefile.inc M src/soc/intel/xeon_sp/skx/Makefile.inc 67 files changed, 37 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/44232/1 diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index de8e326..8667602 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -6,6 +6,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family14/Makefile.inc b/src/cpu/amd/agesa/family14/Makefile.inc index 9576708..8ec1104 100644 --- a/src/cpu/amd/agesa/family14/Makefile.inc +++ b/src/cpu/amd/agesa/family14/Makefile.inc @@ -7,5 +7,4 @@ ramstage-y += model_14_init.c subdirs-y += ../../mtrr -subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/pae diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index df7ac26..4b6b40e 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -6,6 +6,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_TN diff --git a/src/cpu/amd/agesa/family15tn/Makefile.inc b/src/cpu/amd/agesa/family15tn/Makefile.inc index 1d5779d..707e700 100644 --- a/src/cpu/amd/agesa/family15tn/Makefile.inc +++ b/src/cpu/amd/agesa/family15tn/Makefile.inc @@ -10,5 +10,4 @@ subdirs-y += ../../mtrr subdirs-y += ../../smm -subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/pae diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 0cafdf5..1b43dbe 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -6,6 +6,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY16_KB diff --git a/src/cpu/amd/agesa/family16kb/Makefile.inc b/src/cpu/amd/agesa/family16kb/Makefile.inc index d775c54..a39673d 100644 --- a/src/cpu/amd/agesa/family16kb/Makefile.inc +++ b/src/cpu/amd/agesa/family16kb/Makefile.inc @@ -7,5 +7,4 @@ ramstage-y += model_16_init.c subdirs-y += ../../mtrr -subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/pae diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index 65f66df..db921c3 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -6,6 +6,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00630F01 diff --git a/src/cpu/amd/pi/00630F01/Makefile.inc b/src/cpu/amd/pi/00630F01/Makefile.inc index 1d5779d..707e700 100644 --- a/src/cpu/amd/pi/00630F01/Makefile.inc +++ b/src/cpu/amd/pi/00630F01/Makefile.inc @@ -10,5 +10,4 @@ subdirs-y += ../../mtrr subdirs-y += ../../smm -subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/pae diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index 4b7a665..859dda0 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -6,6 +6,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00660F01 diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc index bcbc7fe..95bd867 100644 --- a/src/cpu/amd/pi/00660F01/Makefile.inc +++ b/src/cpu/amd/pi/00660F01/Makefile.inc @@ -6,5 +6,4 @@ ramstage-y += model_15_init.c subdirs-y += ../../mtrr -subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/pae diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index 4247189..c8c6e0a 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -6,6 +6,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select X86_AMD_FIXED_MTRRS select SUPPORT_CPU_UCODE_IN_CBFS select MICROCODE_BLOB_UNDISCLOSED diff --git a/src/cpu/amd/pi/00730F01/Makefile.inc b/src/cpu/amd/pi/00730F01/Makefile.inc index c33c642..43c0c97 100644 --- a/src/cpu/amd/pi/00730F01/Makefile.inc +++ b/src/cpu/amd/pi/00730F01/Makefile.inc @@ -8,5 +8,4 @@ ramstage-y += update_microcode.c subdirs-y += ../../mtrr -subdirs-y += ../../../x86/tsc subdirs-y += ../../../x86/pae diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index e234cab..6f84c99 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -13,6 +13,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index 2f2c128..156699a 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -15,7 +15,6 @@ subdirs-y += ../microcode subdirs-y += ../turbo -subdirs-y += ../../x86/tsc cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*) diff --git a/src/cpu/intel/model_2065x/Kconfig b/src/cpu/intel/model_2065x/Kconfig index 9a7f6bb..d59afe9 100644 --- a/src/cpu/intel/model_2065x/Kconfig +++ b/src/cpu/intel/model_2065x/Kconfig @@ -13,6 +13,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select SSE2 select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 08b6191..9b28281 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -15,6 +15,5 @@ subdirs-y += ../smm/gen1 subdirs-y += ../turbo subdirs-y += ../../x86/name -subdirs-y += ../../x86/tsc cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*) diff --git a/src/cpu/intel/model_206ax/Kconfig b/src/cpu/intel/model_206ax/Kconfig index cfb12d9..239978d 100644 --- a/src/cpu/intel/model_206ax/Kconfig +++ b/src/cpu/intel/model_206ax/Kconfig @@ -13,6 +13,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select MMX select SSE2 select UDELAY_TSC diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index 00802fc..80c3306 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -19,7 +19,6 @@ subdirs-y += ../smm/gen1 subdirs-y += ../turbo subdirs-y += ../../x86/name -subdirs-y += ../../x86/tsc cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*) diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index ae48885..4a246fb 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -15,6 +15,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select NO_SMM select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/intel/slot_1/Makefile.inc b/src/cpu/intel/slot_1/Makefile.inc index c071ec8..856ecf6 100644 --- a/src/cpu/intel/slot_1/Makefile.inc +++ b/src/cpu/intel/slot_1/Makefile.inc @@ -7,7 +7,6 @@ subdirs-y += ../model_67x subdirs-y += ../model_68x subdirs-y += ../model_6bx -subdirs-y += ../../x86/tsc subdirs-y += ../microcode bootblock-y += ../car/p3/cache_as_ram.S diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index c66e463..8b4fdd1 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -9,6 +9,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select MMX select SSE select SETUP_XIP_CACHE diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index a502290..6db031d 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -10,4 +10,3 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 8b92d36..da993f7 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -4,6 +4,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select MMX select SSE diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index 7c7149d..ac796b5 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -10,4 +10,3 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index bb1e1a6..71796ce 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -11,6 +11,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select MMX select SSE select CPU_HAS_L2_ENABLE_MSR diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index 8f360f1..89c3a15 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -10,4 +10,3 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index ca0a513..34eb5a2 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -12,6 +12,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select MMX select SSE select SIPI_VECTOR_IN_ROM diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 5f3ef15..a028078 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -14,4 +14,3 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index e13e1d0..3676707 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -10,6 +10,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select MMX select SSE diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc index 6d28bab..25dc0bd 100644 --- a/src/cpu/intel/socket_m/Makefile.inc +++ b/src/cpu/intel/socket_m/Makefile.inc @@ -11,4 +11,3 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/tsc diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 02145d5..5c830b8 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -9,6 +9,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select MMX select SSE select UDELAY_TSC diff --git a/src/cpu/intel/socket_mPGA604/Makefile.inc b/src/cpu/intel/socket_mPGA604/Makefile.inc index 5e17ab8..380db8e 100644 --- a/src/cpu/intel/socket_mPGA604/Makefile.inc +++ b/src/cpu/intel/socket_mPGA604/Makefile.inc @@ -1,5 +1,4 @@ subdirs-y += ../model_f2x -subdirs-y += ../../x86/tsc subdirs-y += ../microcode subdirs-y += ../hyperthreading diff --git a/src/cpu/intel/socket_p/Kconfig b/src/cpu/intel/socket_p/Kconfig index 6c8c3f7..3fba30b 100644 --- a/src/cpu/intel/socket_p/Kconfig +++ b/src/cpu/intel/socket_p/Kconfig @@ -5,6 +5,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select MMX select SSE diff --git a/src/cpu/intel/socket_p/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc index 5d5f520..981ef1f 100644 --- a/src/cpu/intel/socket_p/Makefile.inc +++ b/src/cpu/intel/socket_p/Makefile.inc @@ -11,4 +11,3 @@ subdirs-y += ../hyperthreading subdirs-y += ../microcode subdirs-y += ../speedstep -subdirs-y += ../../x86/tsc diff --git a/src/cpu/qemu-x86/Kconfig b/src/cpu/qemu-x86/Kconfig index 6ab327f..e45c1e21 100644 --- a/src/cpu/qemu-x86/Kconfig +++ b/src/cpu/qemu-x86/Kconfig @@ -9,6 +9,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select SMP select UDELAY_TSC select TSC_MONOTONIC_TIMER diff --git a/src/cpu/qemu-x86/Makefile.inc b/src/cpu/qemu-x86/Makefile.inc index d2738cf..b50dee5 100644 --- a/src/cpu/qemu-x86/Makefile.inc +++ b/src/cpu/qemu-x86/Makefile.inc @@ -6,5 +6,3 @@ romstage-y += ../intel/car/romstage.c ramstage-y += qemu.c - -subdirs-y += ../x86/tsc diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig index dddd911..5dad9dd 100644 --- a/src/cpu/x86/Kconfig +++ b/src/cpu/x86/Kconfig @@ -14,6 +14,10 @@ bool default n +config CPU_X86_TSC + bool + default n + # TODO These two options look too similar config PARALLEL_CPU_INIT bool diff --git a/src/cpu/x86/Makefile.inc b/src/cpu/x86/Makefile.inc index 9616bb4..c661d4a 100644 --- a/src/cpu/x86/Makefile.inc +++ b/src/cpu/x86/Makefile.inc @@ -3,6 +3,7 @@ subdirs-$(CONFIG_CPU_X86_LAPIC) += lapic subdirs-$(CONFIG_CPU_X86_MTRR) += mtrr subdirs-$(CONFIG_CPU_X86_SMM) += smm +subdirs-$(CONFIG_CPU_X86_TSC) += tsc subdirs-$(CONFIG_PARALLEL_MP) += name ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c ramstage-y += backup_default_smm.c diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index e6ed611..dcb9cae 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -16,6 +16,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select RESET_VECTOR_IN_RAM select X86_AMD_FIXED_MTRRS select X86_AMD_INIT_SIPI diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index b293eb6..bb1d7b1 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_AMD_PICASSO),y) subdirs-y += ../../../cpu/amd/mtrr/ -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/pae subdirs-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += psp_verstage diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 59d2be5..64aec1f 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -16,6 +16,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select X86_AMD_FIXED_MTRRS select ACPI_AMD_HARDWARE_SLEEP_VALUES select COLLECT_TIMESTAMPS_NO_TSC diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index 231f0d9..06270a2 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_AMD_STONEYRIDGE),y) subdirs-y += ../../../cpu/amd/mtrr/ -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/pae bootblock-$(CONFIG_STONEYRIDGE_UART) += uart.c diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 1b2337f..2358677 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -32,6 +32,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select IOAPIC select PCR_COMMON_IOSF_1_0 select SMP diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1058cf2..9450339 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c bootblock-$(CONFIG_FSP_CAR) += fspcar.c diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 1f7a804..ed5cc90 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -17,6 +17,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER diff --git a/src/soc/intel/baytrail/Makefile.inc b/src/soc/intel/baytrail/Makefile.inc index fa8519e..771f9d4 100644 --- a/src/soc/intel/baytrail/Makefile.inc +++ b/src/soc/intel/baytrail/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_BAYTRAIL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index c5ff0fa..1177292 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -17,6 +17,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select SUPPORT_CPU_UCODE_IN_CBFS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED select HAVE_SMI_HANDLER diff --git a/src/soc/intel/braswell/Makefile.inc b/src/soc/intel/braswell/Makefile.inc index df52b7f..4ecb4e7 100644 --- a/src/soc/intel/braswell/Makefile.inc +++ b/src/soc/intel/braswell/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_BRASWELL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index bd810ad..2473728 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -20,6 +20,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select SOUTHBRIDGE_INTEL_COMMON_RESET diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 1a361e5..7932967 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -1,7 +1,6 @@ ifeq ($(CONFIG_SOC_INTEL_BROADWELL),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 9c7bad9..20482d0 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -70,6 +70,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select FSP_COMPRESS_FSP_S_LZMA select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/cannonlake/Makefile.inc b/src/soc/intel/cannonlake/Makefile.inc index c4ef987..bf57e94 100644 --- a/src/soc/intel/cannonlake/Makefile.inc +++ b/src/soc/intel/cannonlake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/intel/common bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index 18dba59..a9899be 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -18,6 +18,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select DEBUG_GPIO select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/denverton_ns/Makefile.inc b/src/soc/intel/denverton_ns/Makefile.inc index 84dc846..73ac3b2 100644 --- a/src/soc/intel/denverton_ns/Makefile.inc +++ b/src/soc/intel/denverton_ns/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c bootblock-y += spi.c diff --git a/src/soc/intel/icelake/Kconfig b/src/soc/intel/icelake/Kconfig index b6453cd..00ac262 100644 --- a/src/soc/intel/icelake/Kconfig +++ b/src/soc/intel/icelake/Kconfig @@ -19,6 +19,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP diff --git a/src/soc/intel/icelake/Makefile.inc b/src/soc/intel/icelake/Makefile.inc index 4d744bc..81ccb86 100644 --- a/src/soc/intel/icelake/Makefile.inc +++ b/src/soc/intel/icelake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index a3a673d..1527192 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -20,6 +20,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/jasperlake/Makefile.inc b/src/soc/intel/jasperlake/Makefile.inc index 8262c32..72a6906 100644 --- a/src/soc/intel/jasperlake/Makefile.inc +++ b/src/soc/intel/jasperlake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index fa6861e..ada39da 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -14,6 +14,7 @@ select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 select CPU_X86_MTRR + select CPU_X86_TSC select NO_MMCONF_SUPPORT select REG_SCRIPT select PLATFORM_USES_FSP2_0 diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 5800e04..8b0c8bf 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_QUARK),y) subdirs-y += romstage -subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/esram_init.S bootblock-y += bootblock/bootblock.c diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index a753db8..834cbe0 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -32,6 +32,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 9dbfa26..41ceeac 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -5,7 +5,6 @@ subdirs-y += ../../../cpu/intel/common subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/tsc bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cpu.c diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index c3105c8..f902d8e 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -20,6 +20,7 @@ select CPU_X86_LAPIC select CPU_X86_MTRR select CPU_X86_SMM + select CPU_X86_TSC select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP select GENERIC_GPIO_LIB diff --git a/src/soc/intel/tigerlake/Makefile.inc b/src/soc/intel/tigerlake/Makefile.inc index 848a5b0..65d9976 100644 --- a/src/soc/intel/tigerlake/Makefile.inc +++ b/src/soc/intel/tigerlake/Makefile.inc @@ -3,7 +3,6 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo -subdirs-y += ../../../cpu/x86/tsc # all (bootblock, verstage, romstage, postcar, ramstage) all-y += gspi.c diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index 7ab0ed0..4f420e2 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -33,6 +33,7 @@ select BOOT_DEVICE_SUPPORTS_WRITES select CPU_X86_LAPIC select CPU_X86_MTRR + select CPU_X86_TSC select POSTCAR_CONSOLE select SOC_INTEL_COMMON select SOC_INTEL_COMMON_RESET diff --git a/src/soc/intel/xeon_sp/cpx/Makefile.inc b/src/soc/intel/xeon_sp/cpx/Makefile.inc index 59ca104..ec8d791 100644 --- a/src/soc/intel/xeon_sp/cpx/Makefile.inc +++ b/src/soc/intel/xeon_sp/cpx/Makefile.inc @@ -3,7 +3,6 @@ ifeq ($(CONFIG_SOC_INTEL_COOPERLAKE_SP),y) subdirs-y += ../../../../cpu/intel/turbo -subdirs-y += ../../../../cpu/x86/tsc subdirs-y += ../../../../cpu/intel/microcode romstage-y += romstage.c diff --git a/src/soc/intel/xeon_sp/skx/Makefile.inc b/src/soc/intel/xeon_sp/skx/Makefile.inc index 7d4ece7..2149115 100644 --- a/src/soc/intel/xeon_sp/skx/Makefile.inc +++ b/src/soc/intel/xeon_sp/skx/Makefile.inc @@ -4,7 +4,6 @@ subdirs-y += ../../../../cpu/intel/microcode subdirs-y += ../../../../cpu/intel/turbo -subdirs-y += ../../../../cpu/x86/tsc postcar-y += soc_util.c -- To view, visit https://review.coreboot.org/c/coreboot/+/44232 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie7d8229d23b3fa515e56f4a4541b246ac7a6fbc1 Gerrit-Change-Number: 44232 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: David Guckian <david.guckian(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Vanessa Eusebio <vanessa.f.eusebio(a)intel.com> Gerrit-MessageType: newchange

3 8

Change in coreboot[master]: include/cpu/x86/cache.h: Rename include guard
by Angel Pons (Code Review) 09 Aug '20

09 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44225 ) Change subject: include/cpu/x86/cache.h: Rename include guard ...................................................................... include/cpu/x86/cache.h: Rename include guard Change-Id: Ibe4d9ff696755f4326509b6307c5a4dcca81ec4c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/include/cpu/x86/cache.h 1 file changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/44225/1 diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 01b202e..b272a42 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef CPU_X86_CACHE -#define CPU_X86_CACHE +#ifndef __CPU_X86_CACHE__ +#define __CPU_X86_CACHE__ #include <cpu/x86/cr.h> @@ -57,4 +57,4 @@ void x86_enable_cache(void); #endif /* !__ASSEMBLER__ */ -#endif /* CPU_X86_CACHE */ +#endif /* __CPU_X86_CACHE__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/44225 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ibe4d9ff696755f4326509b6307c5a4dcca81ec4c Gerrit-Change-Number: 44225 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 5

Change in coreboot[master]: cpu/intel/model_106cx/Makefile.inc: Order entries
by Angel Pons (Code Review) 09 Aug '20

09 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44224 ) Change subject: cpu/intel/model_106cx/Makefile.inc: Order entries ...................................................................... cpu/intel/model_106cx/Makefile.inc: Order entries Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Group CPU models separately from other subdirs, as they are special. Tested with BUILD_TIMELESS=1, Intel D945GCLF remains identical. Change-Id: I0aa6b46ae2f114fe1fa6b0a74669e09e142e2b05 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_106cx/Makefile.inc 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/44224/1 diff --git a/src/cpu/intel/model_106cx/Makefile.inc b/src/cpu/intel/model_106cx/Makefile.inc index 6d8414e..8b1be1e 100644 --- a/src/cpu/intel/model_106cx/Makefile.inc +++ b/src/cpu/intel/model_106cx/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += model_106cx_init.c -subdirs-y += ../../x86/name -subdirs-y += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c +subdirs-y += ../smm/gen1 +subdirs-y += ../../x86/name + cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-1c-*) -- To view, visit https://review.coreboot.org/c/coreboot/+/44224 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0aa6b46ae2f114fe1fa6b0a74669e09e142e2b05 Gerrit-Change-Number: 44224 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/socket_441/Makefile.inc: Order entries
by Angel Pons (Code Review) 09 Aug '20

09 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44223 ) Change subject: cpu/intel/socket_441/Makefile.inc: Order entries ...................................................................... cpu/intel/socket_441/Makefile.inc: Order entries Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Group CPU models separately from other subdirs, as they are special. Tested with BUILD_TIMELESS=1, Intel D945GCLF remains identical. Change-Id: I6762a00e12a2290fb566df3149746731c5f675a5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/socket_441/Makefile.inc 1 file changed, 14 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/44223/1 diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index e21bf03..d827747 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -1,15 +1,17 @@ -subdirs-y += ../model_106cx -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../hyperthreading -subdirs-y += ../speedstep - -bootblock-y += ../car/p4-netburst/cache_as_ram.S bootblock-y += ../car/bootblock.c -postcar-y += ../car/p4-netburst/exit_car.S +bootblock-y += ../car/p4-netburst/cache_as_ram.S romstage-y += ../car/romstage.c + +postcar-y += ../car/p4-netburst/exit_car.S + +subdirs-y += ../model_106cx + +subdirs-y += ../hyperthreading +subdirs-y += ../microcode +subdirs-y += ../speedstep +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/tsc -- To view, visit https://review.coreboot.org/c/coreboot/+/44223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6762a00e12a2290fb566df3149746731c5f675a5 Gerrit-Change-Number: 44223 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/socket_FCBGA559/Makefile.inc: Order entries
by Angel Pons (Code Review) 09 Aug '20

09 Aug '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44222 ) Change subject: cpu/intel/socket_FCBGA559/Makefile.inc: Order entries ...................................................................... cpu/intel/socket_FCBGA559/Makefile.inc: Order entries Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Group CPU models separately from other subdirs, as they are special. Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical. Change-Id: I5e95e609dcbf97a9448299171262ed6499686f73 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/socket_FCBGA559/Makefile.inc 1 file changed, 12 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/44222/1 diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index c95e135..08f88b6 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -1,16 +1,17 @@ -subdirs-y += ../model_106cx -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../hyperthreading -subdirs-y += ../speedstep - bootblock-y += ../car/bootblock.c bootblock-y += ../car/non-evict/cache_as_ram.S +romstage-y += ../car/romstage.c + postcar-y += ../car/non-evict/exit_car.S -romstage-y += ../car/romstage.c +subdirs-y += ../model_106cx + +subdirs-y += ../hyperthreading +subdirs-y += ../microcode +subdirs-y += ../speedstep +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/tsc -- To view, visit https://review.coreboot.org/c/coreboot/+/44222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e95e609dcbf97a9448299171262ed6499686f73 Gerrit-Change-Number: 44222 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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