August 2020 - coreboot-gerrit - mail.coreboot.org

Change in coreboot[master]: cpu/intel/socket_441/Makefile.inc: Order entries
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44223 ) Change subject: cpu/intel/socket_441/Makefile.inc: Order entries ...................................................................... cpu/intel/socket_441/Makefile.inc: Order entries Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Group CPU models separately from other subdirs, as they are special. Tested with BUILD_TIMELESS=1, Intel D945GCLF remains identical. Change-Id: I6762a00e12a2290fb566df3149746731c5f675a5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/socket_441/Makefile.inc 1 file changed, 14 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/44223/1 diff --git a/src/cpu/intel/socket_441/Makefile.inc b/src/cpu/intel/socket_441/Makefile.inc index e21bf03..d827747 100644 --- a/src/cpu/intel/socket_441/Makefile.inc +++ b/src/cpu/intel/socket_441/Makefile.inc @@ -1,15 +1,17 @@ -subdirs-y += ../model_106cx -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../hyperthreading -subdirs-y += ../speedstep - -bootblock-y += ../car/p4-netburst/cache_as_ram.S bootblock-y += ../car/bootblock.c -postcar-y += ../car/p4-netburst/exit_car.S +bootblock-y += ../car/p4-netburst/cache_as_ram.S romstage-y += ../car/romstage.c + +postcar-y += ../car/p4-netburst/exit_car.S + +subdirs-y += ../model_106cx + +subdirs-y += ../hyperthreading +subdirs-y += ../microcode +subdirs-y += ../speedstep +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/tsc -- To view, visit https://review.coreboot.org/c/coreboot/+/44223 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6762a00e12a2290fb566df3149746731c5f675a5 Gerrit-Change-Number: 44223 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/socket_FCBGA559/Makefile.inc: Order entries
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44222 ) Change subject: cpu/intel/socket_FCBGA559/Makefile.inc: Order entries ...................................................................... cpu/intel/socket_FCBGA559/Makefile.inc: Order entries Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Group CPU models separately from other subdirs, as they are special. Tested with BUILD_TIMELESS=1, Foxconn D41S remains identical. Change-Id: I5e95e609dcbf97a9448299171262ed6499686f73 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/socket_FCBGA559/Makefile.inc 1 file changed, 12 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/44222/1 diff --git a/src/cpu/intel/socket_FCBGA559/Makefile.inc b/src/cpu/intel/socket_FCBGA559/Makefile.inc index c95e135..08f88b6 100644 --- a/src/cpu/intel/socket_FCBGA559/Makefile.inc +++ b/src/cpu/intel/socket_FCBGA559/Makefile.inc @@ -1,16 +1,17 @@ -subdirs-y += ../model_106cx -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../hyperthreading -subdirs-y += ../speedstep - bootblock-y += ../car/bootblock.c bootblock-y += ../car/non-evict/cache_as_ram.S +romstage-y += ../car/romstage.c + postcar-y += ../car/non-evict/exit_car.S -romstage-y += ../car/romstage.c +subdirs-y += ../model_106cx + +subdirs-y += ../hyperthreading +subdirs-y += ../microcode +subdirs-y += ../speedstep +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/tsc -- To view, visit https://review.coreboot.org/c/coreboot/+/44222 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5e95e609dcbf97a9448299171262ed6499686f73 Gerrit-Change-Number: 44222 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/socket_m/Makefile.inc: Order entries
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44221 ) Change subject: cpu/intel/socket_m/Makefile.inc: Order entries ...................................................................... cpu/intel/socket_m/Makefile.inc: Order entries Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Group CPU models separately from other subdirs, as they are special. Tested with BUILD_TIMELESS=1, Getac P470 remains identical. Change-Id: Ie3e4574512e6f3e3f12209ba72e90e87c180b0cb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/socket_m/Makefile.inc 1 file changed, 16 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/44221/1 diff --git a/src/cpu/intel/socket_m/Makefile.inc b/src/cpu/intel/socket_m/Makefile.inc index 61e4e58..d79e082 100644 --- a/src/cpu/intel/socket_m/Makefile.inc +++ b/src/cpu/intel/socket_m/Makefile.inc @@ -1,16 +1,19 @@ -subdirs-y += ../model_6ex -subdirs-y += ../model_6fx -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../hyperthreading -subdirs-y += ../speedstep - -bootblock-y += ../car/core2/cache_as_ram.S bootblock-y += ../car/bootblock.c -postcar-y += ../car/p4-netburst/exit_car.S +bootblock-y += ../car/core2/cache_as_ram.S romstage-y += ../car/romstage.c + +postcar-y += ../car/p4-netburst/exit_car.S + +subdirs-y += ../model_6ex +subdirs-y += ../model_6fx + +subdirs-y += ../hyperthreading +subdirs-y += ../microcode +subdirs-y += ../speedstep +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/tsc + -- To view, visit https://review.coreboot.org/c/coreboot/+/44221 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3e4574512e6f3e3f12209ba72e90e87c180b0cb Gerrit-Change-Number: 44221 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/socket_p/Makefile.inc: Sort entries
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44220 ) Change subject: cpu/intel/socket_p/Makefile.inc: Sort entries ...................................................................... cpu/intel/socket_p/Makefile.inc: Sort entries Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Group CPU models separately from other subdirs, as they are special. Tested with BUILD_TIMELESS=1, Lenovo ThinkPad T400 remains identical. Change-Id: I368d1bca59cc7c2ef5728a66ec9b59f9f8190355 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/socket_p/Makefile.inc 1 file changed, 16 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/44220/1 diff --git a/src/cpu/intel/socket_p/Makefile.inc b/src/cpu/intel/socket_p/Makefile.inc index 76c4127..b644fce 100644 --- a/src/cpu/intel/socket_p/Makefile.inc +++ b/src/cpu/intel/socket_p/Makefile.inc @@ -1,16 +1,19 @@ -subdirs-y += ../model_6fx -subdirs-y += ../model_1067x -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../hyperthreading -subdirs-y += ../speedstep - -bootblock-y += ../car/core2/cache_as_ram.S bootblock-y += ../car/bootblock.c -postcar-y += ../car/p4-netburst/exit_car.S +bootblock-y += ../car/core2/cache_as_ram.S romstage-y += ../car/romstage.c + +postcar-y += ../car/p4-netburst/exit_car.S + +subdirs-y += ../model_6fx +subdirs-y += ../model_1067x + +subdirs-y += ../hyperthreading +subdirs-y += ../microcode +subdirs-y += ../speedstep +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/tsc + -- To view, visit https://review.coreboot.org/c/coreboot/+/44220 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I368d1bca59cc7c2ef5728a66ec9b59f9f8190355 Gerrit-Change-Number: 44220 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/socket_BGA956: Order entries
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44219 ) Change subject: cpu/intel/socket_BGA956: Order entries ...................................................................... cpu/intel/socket_BGA956: Order entries Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Group CPU models separately from other subdirs, as they are special. Tested with BUILD_TIMELESS=1, Roda RK9 remains identical. Change-Id: I29e2ab3db9dceb64505a47d1493970f025b4bea0 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/socket_BGA956/Makefile.inc 1 file changed, 14 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/44219/1 diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index 7656416..fb18f2e 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -1,15 +1,17 @@ -subdirs-y += ../model_1067x -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../hyperthreading -subdirs-y += ../speedstep - -bootblock-y += ../car/core2/cache_as_ram.S bootblock-y += ../car/bootblock.c -postcar-y += ../car/p4-netburst/exit_car.S +bootblock-y += ../car/core2/cache_as_ram.S romstage-y += ../car/romstage.c + +postcar-y += ../car/p4-netburst/exit_car.S + +subdirs-y += ../model_1067x + +subdirs-y += ../hyperthreading +subdirs-y += ../microcode +subdirs-y += ../speedstep +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/tsc -- To view, visit https://review.coreboot.org/c/coreboot/+/44219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I29e2ab3db9dceb64505a47d1493970f025b4bea0 Gerrit-Change-Number: 44219 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/socket_LGA775: Order entries
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44217 ) Change subject: cpu/intel/socket_LGA775: Order entries ...................................................................... cpu/intel/socket_LGA775: Order entries Sort the entries of this socket's Makefile.inc, as well as its CPUs. Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Group CPU models separately from other subdirs, as they are special. Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical. Change-Id: Iea1f561144a46f5d1b49b9d332d55ccfb85e923f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/cpu/intel/socket_LGA775/Makefile.inc 5 files changed, 24 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44217/1 diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc index 545f04d..d70bee3 100644 --- a/src/cpu/intel/model_1067x/Makefile.inc +++ b/src/cpu/intel/model_1067x/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += model_1067x_init.c ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c -subdirs-y += ../../x86/name + subdirs-y += ../smm/gen1 +subdirs-y += ../../x86/name cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*) diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index f1d64b7..3f7dd47 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -1,7 +1,8 @@ ramstage-y += model_6fx_init.c -subdirs-y += ../../x86/name -subdirs-y += ../common ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c + +subdirs-y += ../common subdirs-y += ../smm/gen1 +subdirs-y += ../../x86/name cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index 1f2b564..6037ccd 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += model_f3x_init.c -subdirs-y += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c +subdirs-y += ../smm/gen1 + cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-03-*) diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index 7e853b0..ed220d5 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += model_f4x_init.c -subdirs-y += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c +subdirs-y += ../smm/gen1 + cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-04-*) diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 2f1c6b4..35a5ad2 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -1,22 +1,23 @@ +bootblock-y += ../car/bootblock.c +bootblock-y += ../car/p4-netburst/cache_as_ram.S +bootblock-y += ../../x86/early_reset.S + +romstage-y += ../car/romstage.c + +postcar-y += ../car/p4-netburst/exit_car.S + subdirs-y += ../model_6fx subdirs-y += ../model_f3x subdirs-y += ../model_f4x #subdirs-y += ../model_f6x #subdirs-y += ../model_1066x subdirs-y += ../model_1067x -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode + subdirs-y += ../hyperthreading +subdirs-y += ../microcode subdirs-y += ../speedstep - -bootblock-y += ../car/p4-netburst/cache_as_ram.S -bootblock-y += ../car/bootblock.c -bootblock-y += ../../x86/early_reset.S - -postcar-y += ../car/p4-netburst/exit_car.S - -romstage-y += ../car/romstage.c +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/tsc -- To view, visit https://review.coreboot.org/c/coreboot/+/44217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iea1f561144a46f5d1b49b9d332d55ccfb85e923f Gerrit-Change-Number: 44217 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/haswell/Makefile.inc: Order entries
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44214 ) Change subject: cpu/intel/haswell/Makefile.inc: Order entries ...................................................................... cpu/intel/haswell/Makefile.inc: Order entries Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Tested with BUILD_TIMELESS=1, Asrock B85M Pro4 remains identical. Change-Id: I0f792ccd54c2c77545d5e1e1392b5ee954634314 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/haswell/Makefile.inc 1 file changed, 13 insertions(+), 13 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/44214/1 diff --git a/src/cpu/intel/haswell/Makefile.inc b/src/cpu/intel/haswell/Makefile.inc index b93b911..cf4e812 100644 --- a/src/cpu/intel/haswell/Makefile.inc +++ b/src/cpu/intel/haswell/Makefile.inc @@ -1,25 +1,25 @@ -ramstage-y += haswell_init.c +bootblock-y += bootblock.c +bootblock-y += ../car/bootblock.c +bootblock-y += ../car/non-evict/cache_as_ram.S +bootblock-y += ../../x86/early_reset.S + romstage-y += ../car/romstage.c +postcar-y += ../car/non-evict/exit_car.S + ramstage-y += acpi.c +ramstage-y += haswell_init.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smmrelocate.c smm-y += finalize.c -bootblock-y += ../car/non-evict/cache_as_ram.S -bootblock-y += ../car/bootblock.c -bootblock-y += ../../x86/early_reset.S -bootblock-y += bootblock.c - -postcar-y += ../car/non-evict/exit_car.S - -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm subdirs-y += ../microcode subdirs-y += ../turbo +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/tsc cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*) cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*) -- To view, visit https://review.coreboot.org/c/coreboot/+/44214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0f792ccd54c2c77545d5e1e1392b5ee954634314 Gerrit-Change-Number: 44214 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/model_206ax/Makefile.inc: Order entries
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44213 ) Change subject: cpu/intel/model_206ax/Makefile.inc: Order entries ...................................................................... cpu/intel/model_206ax/Makefile.inc: Order entries Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Tested with BUILD_TIMELESS=1, Lenovo ThinkPad X230 remains identical. Change-Id: I168d37305852ffe91c5df1e6f805221d18516908 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_206ax/Makefile.inc 1 file changed, 23 insertions(+), 25 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/44213/1 diff --git a/src/cpu/intel/model_206ax/Makefile.inc b/src/cpu/intel/model_206ax/Makefile.inc index d824da1..557bbd1 100644 --- a/src/cpu/intel/model_206ax/Makefile.inc +++ b/src/cpu/intel/model_206ax/Makefile.inc @@ -1,31 +1,29 @@ -ramstage-y += model_206ax_init.c -subdirs-y += ../../x86/name -subdirs-y += ../smm/gen1 - -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode -subdirs-y += ../turbo - -ramstage-y += acpi.c - -ramstage-y += common.c -romstage-y += common.c -smm-y += common.c - -smm-y += finalize.c - -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*) - bootblock-y += bootblock.c +bootblock-y += ../car/bootblock.c bootblock-y += ../car/non-evict/cache_as_ram.S bootblock-y += ../../x86/early_reset.S -bootblock-y += ../car/bootblock.c + +romstage-y += common.c +romstage-y += ../car/romstage.c postcar-y += ../car/non-evict/exit_car.S -romstage-y += ../car/romstage.c +ramstage-y += acpi.c +ramstage-y += common.c +ramstage-y += model_206ax_init.c + +smm-y += common.c +smm-y += finalize.c + +subdirs-y += ../microcode +subdirs-y += ../smm/gen1 +subdirs-y += ../turbo +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/name +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/tsc + +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*) +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*) -- To view, visit https://review.coreboot.org/c/coreboot/+/44213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I168d37305852ffe91c5df1e6f805221d18516908 Gerrit-Change-Number: 44213 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: cpu/intel/model_2065x/Makefile.inc: Order entries
by Angel Pons (Code Review) Aug. 9, 2020

Aug. 9, 2020

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44212 ) Change subject: cpu/intel/model_2065x/Makefile.inc: Order entries ...................................................................... cpu/intel/model_2065x/Makefile.inc: Order entries Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Tested with BUILD_TIMELESS=1, Packard Bell MS2290 remains identical. Change-Id: I33a1624b3714200262c412a066218dab1fca4e51 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_2065x/Makefile.inc 1 file changed, 22 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/44212/1 diff --git a/src/cpu/intel/model_2065x/Makefile.inc b/src/cpu/intel/model_2065x/Makefile.inc index 1428421..72ed621 100644 --- a/src/cpu/intel/model_2065x/Makefile.inc +++ b/src/cpu/intel/model_2065x/Makefile.inc @@ -1,24 +1,27 @@ -ramstage-y += model_2065x_init.c -subdirs-y += ../../x86/name -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/tsc -subdirs-y += ../../intel/turbo -subdirs-y += ../../intel/microcode -subdirs-y += ../../x86/smm -subdirs-y += ../smm/gen1 - -ramstage-y += acpi.c - -smm-y += finalize.c - -cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*) - -bootblock-y += ../car/non-evict/cache_as_ram.S bootblock-y += ../car/bootblock.c +bootblock-y += ../car/non-evict/cache_as_ram.S bootblock-y += ../../x86/early_reset.S +romstage-y += ../car/romstage.c + postcar-y += ../car/non-evict/exit_car.S -romstage-y += ../car/romstage.c +ramstage-y += acpi.c +ramstage-y += model_2065x_init.c + +smm-y += finalize.c + +subdirs-y += ../microcode +subdirs-y += ../smm/gen1 +subdirs-y += ../turbo +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/name +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/tsc + +cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*) + + + -- To view, visit https://review.coreboot.org/c/coreboot/+/44212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I33a1624b3714200262c412a066218dab1fca4e51 Gerrit-Change-Number: 44212 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming
by Aamir Bohra (Code Review) Aug. 9, 2020

Aug. 9, 2020

Aamir Bohra has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44060 ) Change subject: soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming ...................................................................... soc/intel/{icl.tgl,jsl}: Remove SMRAM register programming SA SMRAMC register PCI offset 0x88 is depcrecated ICL. JSL and TGL. Removing the resgiter programming for these platforms. The write to this register does not take effect and remains configured to 0, even when programmed. Signed-off-by: Aamir Bohra <aamir.bohra(a)intel.com> Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 --- M src/soc/intel/icelake/cpu.c M src/soc/intel/icelake/include/soc/systemagent.h M src/soc/intel/icelake/smmrelocate.c M src/soc/intel/jasperlake/cpu.c M src/soc/intel/jasperlake/include/soc/systemagent.h M src/soc/intel/jasperlake/smmrelocate.c M src/soc/intel/tigerlake/cpu.c M src/soc/intel/tigerlake/include/soc/systemagent.h M src/soc/intel/tigerlake/smmrelocate.c 9 files changed, 0 insertions(+), 66 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/44060/1 diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 45c81ca..2823fd7 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -221,9 +221,6 @@ * start flowing. */ global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/icelake/include/soc/systemagent.h b/src/soc/intel/icelake/include/soc/systemagent.h index 90465a24..ef648a6 100644 --- a/src/soc/intel/icelake/include/soc/systemagent.h +++ b/src/soc/intel/icelake/include/soc/systemagent.h @@ -9,12 +9,6 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define CAPID0_A 0xe4 #define BIOS_RESET_CPL 0x5da8 diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index f1a7033..a847db9 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -17,7 +17,6 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> -#include <soc/systemagent.h> static void update_save_state(int cpu, uintptr_t curr_smbase, @@ -234,15 +233,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index 99cbef2..3a50929 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -185,9 +185,6 @@ * start flowing. */ global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/jasperlake/include/soc/systemagent.h b/src/soc/intel/jasperlake/include/soc/systemagent.h index 2ad98f7..e21c9af 100644 --- a/src/soc/intel/jasperlake/include/soc/systemagent.h +++ b/src/soc/intel/jasperlake/include/soc/systemagent.h @@ -9,12 +9,6 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define CAPID0_A 0xe4 #define VTD_DISABLE (1 << 23) diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c index 664ea6c..bbdcb68 100644 --- a/src/soc/intel/jasperlake/smmrelocate.c +++ b/src/soc/intel/jasperlake/smmrelocate.c @@ -17,7 +17,6 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> -#include <soc/systemagent.h> static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, @@ -233,15 +232,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index 9a96f8f..be056fb 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -191,9 +191,6 @@ * start flowing. */ global_smi_enable(); - - /* Lock down the SMRAM space. */ - smm_lock(); } static const struct mp_ops mp_ops = { diff --git a/src/soc/intel/tigerlake/include/soc/systemagent.h b/src/soc/intel/tigerlake/include/soc/systemagent.h index 3e43843..fca9b2b 100644 --- a/src/soc/intel/tigerlake/include/soc/systemagent.h +++ b/src/soc/intel/tigerlake/include/soc/systemagent.h @@ -15,12 +15,6 @@ #define EPBAR 0x40 #define DMIBAR 0x68 -#define SMRAM 0x88 /* System Management RAM Control */ -#define D_OPEN (1 << 6) -#define D_CLS (1 << 5) -#define D_LCK (1 << 4) -#define G_SMRAME (1 << 3) -#define C_BASE_SEG ((0 << 2) | (1 << 1) | (0 << 0)) #define CAPID0_A 0xe4 #define VTD_DISABLE (1 << 23) diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index 664ea6c..bbdcb68 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -17,7 +17,6 @@ #include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/soc_chip.h> -#include <soc/systemagent.h> static void update_save_state(int cpu, uintptr_t curr_smbase, uintptr_t staggered_smbase, @@ -233,15 +232,3 @@ else if (!boot_cpu()) smm_initiate_relocation(); } - -void smm_lock(void) -{ - struct device *sa_dev = pcidev_path_on_root(SA_DEVFN_ROOT); - /* - * LOCK the SMM memory window and enable normal SMM. - * After running this function, only a full reset can - * make the SMM registers writable again. - */ - printk(BIOS_DEBUG, "Locking SMM.\n"); - pci_write_config8(sa_dev, SMRAM, D_LCK | G_SMRAME | C_BASE_SEG); -} -- To view, visit https://review.coreboot.org/c/coreboot/+/44060 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f581b90ea99012980f439a7914e8d901585b004 Gerrit-Change-Number: 44060 Gerrit-PatchSet: 1 Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-MessageType: newchange

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