Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44217 )
Change subject: cpu/intel/socket_LGA775: Order entries ......................................................................
cpu/intel/socket_LGA775: Order entries
Sort the entries of this socket's Makefile.inc, as well as its CPUs.
Group lines by stages, then subdirs, then microcode. Within groups, order in ascending count of `../` in prefix and then alphabetically. Group CPU models separately from other subdirs, as they are special.
Tested with BUILD_TIMELESS=1, Asus P5QL PRO remains identical.
Change-Id: Iea1f561144a46f5d1b49b9d332d55ccfb85e923f Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/model_1067x/Makefile.inc M src/cpu/intel/model_6fx/Makefile.inc M src/cpu/intel/model_f3x/Makefile.inc M src/cpu/intel/model_f4x/Makefile.inc M src/cpu/intel/socket_LGA775/Makefile.inc 5 files changed, 24 insertions(+), 19 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/44217/1
diff --git a/src/cpu/intel/model_1067x/Makefile.inc b/src/cpu/intel/model_1067x/Makefile.inc index 545f04d..d70bee3 100644 --- a/src/cpu/intel/model_1067x/Makefile.inc +++ b/src/cpu/intel/model_1067x/Makefile.inc @@ -1,6 +1,7 @@ ramstage-y += model_1067x_init.c ramstage-$(CONFIG_PARALLEL_MP) += mp_init.c -subdirs-y += ../../x86/name + subdirs-y += ../smm/gen1 +subdirs-y += ../../x86/name
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*) diff --git a/src/cpu/intel/model_6fx/Makefile.inc b/src/cpu/intel/model_6fx/Makefile.inc index f1d64b7..3f7dd47 100644 --- a/src/cpu/intel/model_6fx/Makefile.inc +++ b/src/cpu/intel/model_6fx/Makefile.inc @@ -1,7 +1,8 @@ ramstage-y += model_6fx_init.c -subdirs-y += ../../x86/name -subdirs-y += ../common ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c + +subdirs-y += ../common subdirs-y += ../smm/gen1 +subdirs-y += ../../x86/name
cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0f-*) diff --git a/src/cpu/intel/model_f3x/Makefile.inc b/src/cpu/intel/model_f3x/Makefile.inc index 1f2b564..6037ccd 100644 --- a/src/cpu/intel/model_f3x/Makefile.inc +++ b/src/cpu/intel/model_f3x/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += model_f3x_init.c -subdirs-y += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
+subdirs-y += ../smm/gen1 + cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-03-*) diff --git a/src/cpu/intel/model_f4x/Makefile.inc b/src/cpu/intel/model_f4x/Makefile.inc index 7e853b0..ed220d5 100644 --- a/src/cpu/intel/model_f4x/Makefile.inc +++ b/src/cpu/intel/model_f4x/Makefile.inc @@ -1,5 +1,6 @@ ramstage-y += model_f4x_init.c -subdirs-y += ../smm/gen1 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
+subdirs-y += ../smm/gen1 + cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/0f-04-*) diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index 2f1c6b4..35a5ad2 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -1,22 +1,23 @@ +bootblock-y += ../car/bootblock.c +bootblock-y += ../car/p4-netburst/cache_as_ram.S +bootblock-y += ../../x86/early_reset.S + +romstage-y += ../car/romstage.c + +postcar-y += ../car/p4-netburst/exit_car.S + subdirs-y += ../model_6fx subdirs-y += ../model_f3x subdirs-y += ../model_f4x #subdirs-y += ../model_f6x #subdirs-y += ../model_1066x subdirs-y += ../model_1067x -subdirs-y += ../../x86/tsc -subdirs-y += ../../x86/mtrr -subdirs-y += ../../x86/lapic -subdirs-y += ../../x86/cache -subdirs-y += ../../x86/smm -subdirs-y += ../microcode + subdirs-y += ../hyperthreading +subdirs-y += ../microcode subdirs-y += ../speedstep - -bootblock-y += ../car/p4-netburst/cache_as_ram.S -bootblock-y += ../car/bootblock.c -bootblock-y += ../../x86/early_reset.S - -postcar-y += ../car/p4-netburst/exit_car.S - -romstage-y += ../car/romstage.c +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/smm +subdirs-y += ../../x86/tsc
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44217 )
Change subject: cpu/intel/socket_LGA775: Order entries ......................................................................
Patch Set 1:
why? will it fix something?
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44217 )
Change subject: cpu/intel/socket_LGA775: Order entries ......................................................................
Patch Set 1:
Patch Set 1:
why? will it fix something?
It doesn't fix nor break anything, because cleaning and rebuilding after this patch results in the same binary. It simply makes it easier to diff between files because the order is the same on all of them.
Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44217 )
Change subject: cpu/intel/socket_LGA775: Order entries ......................................................................
Abandoned
Sorry, I ran out of patience and energy to care about these changes any longer.
-
Angel Pons (Code Review) -
HAOUAS Elyes (Code Review)