Change in coreboot[master]: soc/amd/common/espi_util: espi_send_command: improve error message

[Felix Held (Code Review)]

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44352 )

Change subject: soc/amd/common/espi_util: espi_send_command: improve error message
......................................................................

soc/amd/common/espi_util: espi_send_command: improve error message

It's only an error if bits other than ESPI_STATUS_DNCMD_COMPLETE are set
in the status register. If ESPI_STATUS_DNCMD_COMPLETE isn't set, the
command failed, so we expect that one to be set.

Change-Id: I6f1fb5a59b1ecadd6724a07212626f21fb90e7e7
Signed-off-by: Felix Held 
---
M src/soc/amd/common/block/lpc/espi_util.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/44352/1

diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 4415615..c1145d0 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -470,7 +470,7 @@
    }

if (status & ~ESPI_STATUS_DNCMD_COMPLETE) {
-		espi_show_failure(cmd, "Error: eSPI status register bits set", status);
+		espi_show_failure(cmd, "Error: unexpected eSPI status register bits set", status);
    	return -1;
    }

[build bot (Jenkins) (Code Review)]

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44352 )

Change subject: soc/amd/common/espi_util: espi_send_command: improve error message
......................................................................

Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44352/1/src/soc/amd/common/block/lp... 
File src/soc/amd/common/block/lpc/espi_util.c:

https://review.coreboot.org/c/coreboot/+/44352/1/src/soc/amd/common/block/lp... 
PS1, Line 473: 		espi_show_failure(cmd, "Error: unexpected eSPI status register bits set", status);
line over 96 characters

[Felix Held (Code Review)]

Hello build bot (Jenkins), Furquan Shaikh,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44352

to look at the new patch set (#2).

Change subject: soc/amd/common/espi_util: espi_send_command: improve error message
......................................................................

soc/amd/common/espi_util: espi_send_command: improve error message

It's only an error if bits other than ESPI_STATUS_DNCMD_COMPLETE are set
in the status register. If ESPI_STATUS_DNCMD_COMPLETE isn't set, the
command failed, so we expect that one to be set.

Change-Id: I6f1fb5a59b1ecadd6724a07212626f21fb90e7e7
Signed-off-by: Felix Held 
---
M src/soc/amd/common/block/lpc/espi_util.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/44352/2

[Furquan Shaikh (Code Review)]

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44352 )

Change subject: soc/amd/common/espi_util: espi_send_command: improve error message
......................................................................

Patch Set 2: Code-Review+2

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/44352 )

Change subject: soc/amd/common/espi_util: espi_send_command: improve error message
......................................................................

soc/amd/common/espi_util: espi_send_command: improve error message

It's only an error if bits other than ESPI_STATUS_DNCMD_COMPLETE are set
in the status register. If ESPI_STATUS_DNCMD_COMPLETE isn't set, the
command failed, so we expect that one to be set.

Change-Id: I6f1fb5a59b1ecadd6724a07212626f21fb90e7e7
Signed-off-by: Felix Held 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44352
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/soc/amd/common/block/lpc/espi_util.c
1 file changed, 2 insertions(+), 1 deletion(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c
index 4415615..b09d61d 100644
--- a/src/soc/amd/common/block/lpc/espi_util.c
+++ b/src/soc/amd/common/block/lpc/espi_util.c
@@ -470,7 +470,8 @@
    }

if (status & ~ESPI_STATUS_DNCMD_COMPLETE) {
-		espi_show_failure(cmd, "Error: eSPI status register bits set", status);
+		espi_show_failure(cmd, "Error: unexpected eSPI status register bits set",
+				  status);
    	return -1;
    }