Change in coreboot[master]: cpu/intel/model_6xx: Update ucode before enabling cache

[Angel Pons (Code Review)]

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44239 )


Change subject: cpu/intel/model_6xx: Update ucode before enabling cache
......................................................................

cpu/intel/model_6xx: Update ucode before enabling cache

Other similar CPUs update the microcode first, so do the same here.

Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d
Signed-off-by: Angel Pons <[e-mail]>
---
M src/cpu/intel/model_6xx/model_6xx_init.c
1 file changed, 3 insertions(+), 3 deletions(-)



  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44239/1

diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c
index a6944d3..f394b5f 100644
--- a/src/cpu/intel/model_6xx/model_6xx_init.c
+++ b/src/cpu/intel/model_6xx/model_6xx_init.c
@@ -9,14 +9,14 @@
 
 static void model_6xx_init(struct device *dev)
 {
+	/* Update the microcode */
+	intel_update_microcode_from_cbfs();
+
 	/* Turn on caching if we haven't already */
 	x86_enable_cache();
 	x86_setup_mtrrs();
 	x86_mtrr_check();
 
-	/* Update the microcode */
-	intel_update_microcode_from_cbfs();
-
 	/* Enable the local CPU APICs */
 	setup_lapic();
 };

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d
Gerrit-Change-Number: 44239
Gerrit-PatchSet: 1
Gerrit-Owner: Angel Pons <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
Gerrit-MessageType: newchange

[Angel Pons (Code Review)]

Hello Keith Hui, build bot (Jenkins), Patrick Rudolph, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/44239

to look at the new patch set (#2).

Change subject: cpu/intel/model_6xx: Update ucode before enabling cache
......................................................................

cpu/intel/model_6xx: Update ucode before enabling cache

Other similar CPUs update the microcode first, so do the same here.

Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d
Signed-off-by: Angel Pons <[e-mail]>
---
M src/cpu/intel/model_6xx/model_6xx_init.c
1 file changed, 3 insertions(+), 3 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44239/2
-- 
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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d
Gerrit-Change-Number: 44239
Gerrit-PatchSet: 2
Gerrit-Owner: Angel Pons <[e-mail]>
Gerrit-Reviewer: Keith Hui <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-CC: Paul Menzel <[e-mail]>
Gerrit-MessageType: newpatchset

[Angel Pons (Code Review)]

Hello Keith Hui, build bot (Jenkins), Patrick Rudolph, 

I'd like you to reexamine a change. Please visit

    https://review.coreboot.org/c/coreboot/+/44239

to look at the new patch set (#4).

Change subject: cpu/intel/model_6xx: Update ucode before enabling cache
......................................................................

cpu/intel/model_6xx: Update ucode before enabling cache

Other similar CPUs update the microcode first, so do the same here.

Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d
Signed-off-by: Angel Pons <[e-mail]>
---
M src/cpu/intel/model_6xx/model_6xx_init.c
1 file changed, 3 insertions(+), 3 deletions(-)


  git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44239/4
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Gerrit-Project: coreboot
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Gerrit-Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d
Gerrit-Change-Number: 44239
Gerrit-PatchSet: 4
Gerrit-Owner: Angel Pons <[e-mail]>
Gerrit-Reviewer: Keith Hui <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-CC: Paul Menzel <[e-mail]>
Gerrit-MessageType: newpatchset

[HAOUAS Elyes (Code Review)]

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44239 )

Change subject: cpu/intel/model_6xx: Update ucode before enabling cache
......................................................................


Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44239/4/src/cpu/intel/model_6xx/mod... 
File src/cpu/intel/model_6xx/model_6xx_init.c:

https://review.coreboot.org/c/coreboot/+/44239/4/src/cpu/intel/model_6xx/mod... 
PS4, Line 13: intel_update_microcode_from_cbfs();
is this tested ?



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Gerrit-Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d
Gerrit-Change-Number: 44239
Gerrit-PatchSet: 4
Gerrit-Owner: Angel Pons <[e-mail]>
Gerrit-Reviewer: Keith Hui <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
Gerrit-Reviewer: build bot (Jenkins) <[e-mail]>
Gerrit-CC: HAOUAS Elyes <[e-mail]>
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Gerrit-Comment-Date: Fri, 07 Aug 2020 06:17:15 +0000
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[Angel Pons (Code Review)]

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44239 )

Change subject: cpu/intel/model_6xx: Update ucode before enabling cache
......................................................................


Patch Set 4:

(1 comment)

Keith, could you please boot-test this change?

https://review.coreboot.org/c/coreboot/+/44239/4/src/cpu/intel/model_6xx/mod... 
File src/cpu/intel/model_6xx/model_6xx_init.c:

https://review.coreboot.org/c/coreboot/+/44239/4/src/cpu/intel/model_6xx/mod... 
PS4, Line 13: intel_update_microcode_from_cbfs();
> is this tested ?
> That's why I added Keith as a reviewer.

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44239 )

Change subject: cpu/intel/model_6xx: Update ucode before enabling cache
......................................................................


Patch Set 4: Code-Review+1

Cache should already be enabled. You probably want to check if the ROM is still cached after that code. Or just check timestamps ;-)


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Gerrit-PatchSet: 4
Gerrit-Owner: Angel Pons <[e-mail]>
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Gerrit-Reviewer: Keith Hui <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
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[Angel Pons (Code Review)]

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44239 )

Change subject: cpu/intel/model_6xx: Update ucode before enabling cache
......................................................................


Abandoned

Sorry, I ran out of patience and energy to care about these changes any longer.
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Gerrit-Project: coreboot
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Gerrit-Change-Number: 44239
Gerrit-PatchSet: 6
Gerrit-Owner: Angel Pons <[e-mail]>
Gerrit-Reviewer: Arthur Heymans <[e-mail]>
Gerrit-Reviewer: Keith Hui <[e-mail]>
Gerrit-Reviewer: Patrick Rudolph <[e-mail]>
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