Change in coreboot[master]: cpu/intel/model_6xx: Update ucode before enabling cache

List overview All Threads
Download

newer

older

Change in coreboot[master]:...

Angel Pons (Code Review)

5 Aug 2020 5 Aug '20

7:37 p.m.

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/44239 )

Change subject: cpu/intel/model_6xx: Update ucode before enabling cache ......................................................................

cpu/intel/model_6xx: Update ucode before enabling cache

Other similar CPUs update the microcode first, so do the same here.

Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/model_6xx/model_6xx_init.c 1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44239/1

diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index a6944d3..f394b5f 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -9,14 +9,14 @@

static void model_6xx_init(struct device *dev) { + /* Update the microcode */ + intel_update_microcode_from_cbfs(); + /* Turn on caching if we haven't already */ x86_enable_cache(); x86_setup_mtrrs(); x86_mtrr_check();

- /* Update the microcode */ - intel_update_microcode_from_cbfs(); - /* Enable the local CPU APICs */ setup_lapic(); };

Attachments:

attachment.htm (text/html — 3.0 KB)

Show replies by thread

Angel Pons (Code Review)

6 Aug 6 Aug

7:18 a.m.

Hello Keith Hui, build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44239

to look at the new patch set (#2).

Change subject: cpu/intel/model_6xx: Update ucode before enabling cache ......................................................................

cpu/intel/model_6xx: Update ucode before enabling cache

Other similar CPUs update the microcode first, so do the same here.

Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/model_6xx/model_6xx_init.c 1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44239/2

-- To view, visit https://review.coreboot.org/c/coreboot/+/44239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d Gerrit-Change-Number: 44239 Gerrit-PatchSet: 2 Gerrit-Owner: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Keith Hui buurin@gmail.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

Angel Pons (Code Review)

11:44 a.m.

Hello Keith Hui, build bot (Jenkins), Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/44239

to look at the new patch set (#4).

Change subject: cpu/intel/model_6xx: Update ucode before enabling cache ......................................................................

cpu/intel/model_6xx: Update ucode before enabling cache

Other similar CPUs update the microcode first, so do the same here.

Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/cpu/intel/model_6xx/model_6xx_init.c 1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44239/4

-- To view, visit https://review.coreboot.org/c/coreboot/+/44239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d Gerrit-Change-Number: 44239 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Keith Hui buurin@gmail.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: newpatchset

HAOUAS Elyes (Code Review)

7 Aug 7 Aug

6:17 a.m.

HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44239 )

Change subject: cpu/intel/model_6xx: Update ucode before enabling cache ......................................................................

Patch Set 4:

(1 comment)

https://review.coreboot.org/c/coreboot/+/44239/4/src/cpu/intel/model_6xx/mod... File src/cpu/intel/model_6xx/model_6xx_init.c:

https://review.coreboot.org/c/coreboot/+/44239/4/src/cpu/intel/model_6xx/mod... PS4, Line 13: intel_update_microcode_from_cbfs(); is this tested ?

-- To view, visit https://review.coreboot.org/c/coreboot/+/44239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d Gerrit-Change-Number: 44239 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Keith Hui buurin@gmail.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: HAOUAS Elyes ehaouas@noos.fr Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 07 Aug 2020 06:17:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

Angel Pons (Code Review)

10:01 a.m.

Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44239 )

Change subject: cpu/intel/model_6xx: Update ucode before enabling cache ......................................................................

Patch Set 4:

(1 comment)

Keith, could you please boot-test this change?

https://review.coreboot.org/c/coreboot/+/44239/4/src/cpu/intel/model_6xx/mod... File src/cpu/intel/model_6xx/model_6xx_init.c:

https://review.coreboot.org/c/coreboot/+/44239/4/src/cpu/intel/model_6xx/mod... PS4, Line 13: intel_update_microcode_from_cbfs();

...

is this tested ?

That's why I added Keith as a reviewer.

-- To view, visit https://review.coreboot.org/c/coreboot/+/44239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d Gerrit-Change-Number: 44239 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Keith Hui buurin@gmail.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: HAOUAS Elyes ehaouas@noos.fr Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 07 Aug 2020 10:01:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: HAOUAS Elyes ehaouas@noos.fr Gerrit-MessageType: comment

Arthur Heymans (Code Review)

10:31 a.m.

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/44239 )

Change subject: cpu/intel/model_6xx: Update ucode before enabling cache ......................................................................

Patch Set 4: Code-Review+1

Cache should already be enabled. You probably want to check if the ROM is still cached after that code. Or just check timestamps ;-)

-- To view, visit https://review.coreboot.org/c/coreboot/+/44239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d Gerrit-Change-Number: 44239 Gerrit-PatchSet: 4 Gerrit-Owner: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Keith Hui buurin@gmail.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: HAOUAS Elyes ehaouas@noos.fr Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-Comment-Date: Fri, 07 Aug 2020 10:31:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

Angel Pons (Code Review)

9 Aug 9 Aug

1:08 p.m.

Angel Pons has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/44239 )

Change subject: cpu/intel/model_6xx: Update ucode before enabling cache ......................................................................

Abandoned

Sorry, I ran out of patience and energy to care about these changes any longer.

-- To view, visit https://review.coreboot.org/c/coreboot/+/44239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d Gerrit-Change-Number: 44239 Gerrit-PatchSet: 6 Gerrit-Owner: Angel Pons th3fanbus@gmail.com Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz Gerrit-Reviewer: Keith Hui buurin@gmail.com Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org Gerrit-CC: HAOUAS Elyes ehaouas@noos.fr Gerrit-CC: Paul Menzel paulepanter@users.sourceforge.net Gerrit-MessageType: abandon

1380

days inactive

1384

days old

coreboot-gerrit@coreboot.org

6 comments

3 participants

tags (0)

participants (3)

Angel Pons (Code Review)
Arthur Heymans (Code Review)
HAOUAS Elyes (Code Review)