Angel Pons uploaded patch set #4 to this change.

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cpu/intel/model_6xx: Update ucode before enabling cache

Other similar CPUs update the microcode first, so do the same here.

Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
---
M src/cpu/intel/model_6xx/model_6xx_init.c
1 file changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/44239/4

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I66f197cc8cf10eac2815961043e8c343aa3c204d
Gerrit-Change-Number: 44239
Gerrit-PatchSet: 4
Gerrit-Owner: Angel Pons <th3fanbus@gmail.com>
Gerrit-Reviewer: Keith Hui <buurin@gmail.com>
Gerrit-Reviewer: Patrick Rudolph <siro@das-labor.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: newpatchset