Change in coreboot[master]: temporary: Revert "soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS"

[Jonathan Zhang (Code Review)]

Jonathan Zhang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43325 )

Change subject: temporary: Revert "soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS"
......................................................................

temporary: Revert "soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS"

This reverts commit 7454005a4fd611cc2ad4b490442834e50272fd1b.

CPX-SP FSP ww28 release has a regression that boot hangs at FSP-M
execution when boot mode is BOOT_ASSUMING_NO_CONFIGURATION_CHANGES.

Signed-off-by: Jonathan Zhang 
Change-Id: I495b4242a0c6a8796fab21a8057053744739df04
---
M src/soc/intel/xeon_sp/cpx/Kconfig
1 file changed, 0 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/43325/1

diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 9c6450e..59ccc6f 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -66,6 +66,4 @@
 config SOC_INTEL_COMMON_BLOCK_P2SB
    def_bool y

-select CACHE_MRC_SETTINGS
-
 endif

[Jonathan Zhang (Code Review)]

Jonathan Zhang has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43325 )

Change subject: temporary: Revert "soc/intel/xeon_sp/cpx: select CACHE_MRC_SETTINGS"
......................................................................

Abandoned

Not needed any more with newer FSP releases fixed this issue.