Change in coreboot[master]: cpu/x86/mtrr: Add helper function to cache cbmem in romstage
Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37199 )
Change subject: cpu/x86/mtrr: Add helper function to cache cbmem in romstage ......................................................................
cpu/x86/mtrr: Add helper function to cache cbmem in romstage
Romstage has some operations on cbmem and external stage cache. In most circumstances this memory is set up as UC, so to speed up these operations like decompressing postcar, this has to be set up as WB.
Note: This should only be attempted on platforms where some form of non eviction mode is used to guarantee not blowing up CAR.
Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/cbmem_cache.c M src/include/cpu/x86/mtrr.h 3 files changed, 79 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37199/1
diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index 129d05d..2658388 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -11,3 +11,5 @@
bootblock-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c verstage-$(CONFIG_SETUP_XIP_CACHE) += xip_cache.c + +romstage-y += cbmem_cache.c \ No newline at end of file diff --git a/src/cpu/x86/mtrr/cbmem_cache.c b/src/cpu/x86/mtrr/cbmem_cache.c new file mode 100644 index 0000000..8753e9e --- /dev/null +++ b/src/cpu/x86/mtrr/cbmem_cache.c @@ -0,0 +1,75 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cbmem.h> +#include <stage_cache.h> +#include <cpu/x86/cache.h> +#include <arch/cpu.h> +#include <program_loading.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <cpu/x86/mtrr.h> + +void setup_romstage_wb_cbmem_cache(void) +{ + int mtrr_num = get_free_var_mtrr(); + uintptr_t top_of_ram = (uintptr_t)cbmem_top(); + uintptr_t stage_cache_base, stage_cache_end; + size_t stage_cache_size; + size_t stage_cache_mtrr_size = 4 * KiB; + + printk(BIOS_DEBUG, "Setting MTRR's for cbmem and stage cache\n"); + + /* postcar will do invd so we need a way to make sure things are in memory + which is only possible if clflush is supported. */ + if (!clflush_supported()) { + printk(BIOS_WARNING, "CLFLUSH not supported, not caching cbmem!\n"); + if (CONFIG(COMPRESS_POSTCAR)) + printk(BIOS_WARNING, "Decompressing POSTCAR will be slow!\n"); + + return; + } + if (mtrr_num < 0) { + printk(BIOS_DEBUG, "No MTRR free to cache cbmem\n!"); + return; + } + /* Often cbmem_top is chosen to be aligned already to optimize MTRR + usage in the postcar frame so this should not be too worrisome. */ + top_of_ram = ALIGN_DOWN(top_of_ram, 4 * MiB); + set_var_mtrr(mtrr_num, top_of_ram - 4 * MiB, 4 * MiB, MTRR_TYPE_WRBACK); + + if (!CONFIG(TSEG_STAGE_CACHE)) + return; + mtrr_num = get_free_var_mtrr(); + if (mtrr_num < 0) { + printk(BIOS_DEBUG, "No MTRR free to cache TSEG stage cache\n!"); + return; + } + stage_cache_external_region((void **)&stage_cache_base, &stage_cache_size); + stage_cache_end = stage_cache_base + stage_cache_size; + + /* Find MTRR to cover TSEG stage cache */ + while (1) { + /* Do some sanity check before it gets absurdly. */ + if (stage_cache_mtrr_size > 64 * MiB) { + printk(BIOS_WARNING, "Not caching stage cache, too large\n"); + return; + } + if (ALIGN_DOWN(stage_cache_base, stage_cache_mtrr_size) + + stage_cache_mtrr_size > stage_cache_end) + break; + stage_cache_mtrr_size *= 2; + } + set_var_mtrr(mtrr_num, ALIGN_DOWN(stage_cache_base, stage_cache_mtrr_size), + stage_cache_mtrr_size, MTRR_TYPE_WRBACK); +} diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 29256c8..abdecfe 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -95,6 +95,8 @@ void x86_setup_fixed_mtrrs_no_enable(void); void x86_mtrr_check(void);
+void setup_romstage_wb_cbmem_cache(void); + /* Insert a temporary MTRR range for the duration of coreboot's runtime. * This function needs to be called after the first MTRR solution is derived. */ void mtrr_use_temp_range(uintptr_t begin, size_t size, int type);
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37199
to look at the new patch set (#2).
Change subject: [WIP]cpu/x86/mtrr: Add helper function to cache cbmem in romstage ......................................................................
[WIP]cpu/x86/mtrr: Add helper function to cache cbmem in romstage
Romstage has some operations on cbmem and external stage cache. In most circumstances this memory is set up as UC, so to speed up these operations like decompressing postcar, this has to be set up as WB.
Note: This should only be attempted on platforms where some form of non eviction mode is used to guarantee not blowing up CAR.
TODO: The size that should be cached below cbmem top should be aligned across platforms.
Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/cbmem_cache.c M src/include/cpu/x86/mtrr.h 3 files changed, 91 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37199/2
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37199
to look at the new patch set (#3).
Change subject: [WIP]cpu/x86/mtrr: Add helper function to cache cbmem in romstage ......................................................................
[WIP]cpu/x86/mtrr: Add helper function to cache cbmem in romstage
Romstage has some operations on cbmem and external stage cache. In most circumstances this memory is set up as UC, so to speed up these operations like decompressing postcar, this has to be set up as WB.
Note: This should only be attempted on platforms where some form of non eviction mode is used to guarantee not blowing up CAR.
TODO: The size that should be cached below cbmem top should be aligned across platforms.
Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/cbmem_cache.c M src/include/cpu/x86/mtrr.h 3 files changed, 91 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37199/3
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37199
to look at the new patch set (#7).
Change subject: [WIP]cpu/x86/mtrr: Add helper function to cache cbmem in romstage ......................................................................
[WIP]cpu/x86/mtrr: Add helper function to cache cbmem in romstage
Romstage has some operations on cbmem and external stage cache. In most circumstances this memory is set up as UC, so to speed up these operations like decompressing postcar, this has to be set up as WB.
Note: This should only be attempted on platforms where some form of non eviction mode is used to guarantee not blowing up CAR.
TODO: The size that should be cached below cbmem top should be aligned across platforms.
Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/cbmem_cache.c M src/include/cpu/x86/mtrr.h 3 files changed, 91 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37199/7
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37199
to look at the new patch set (#8).
Change subject: cpu/x86/mtrr: Add helper function to cache cbmem in romstage ......................................................................
cpu/x86/mtrr: Add helper function to cache cbmem in romstage
Romstage has some operations on cbmem and external stage cache. In most circumstances this memory is set up as UC, so to speed up these operations like decompressing postcar, this has to be set up as WB.
Note: This should only be attempted on platforms where some form of non eviction mode is used to guarantee not blowing up CAR.
Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/cbmem_cache.c M src/include/cpu/x86/mtrr.h 3 files changed, 76 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37199/8
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37199
to look at the new patch set (#9).
Change subject: cpu/x86/mtrr: Add helper function to cache cbmem in romstage ......................................................................
cpu/x86/mtrr: Add helper function to cache cbmem in romstage
Romstage has some operations on cbmem and external stage cache. In most circumstances this memory is set up as UC, so to speed up these operations like decompressing postcar, this has to be set up as WB.
Note: This should only be attempted on platforms where some form of non eviction mode is used to guarantee not blowing up CAR.
Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/cbmem_cache.c M src/include/cpu/x86/mtrr.h 3 files changed, 76 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37199/9
HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37199 )
Change subject: cpu/x86/mtrr: Add helper function to cache cbmem in romstage ......................................................................
Patch Set 11:
(1 comment)
https://review.coreboot.org/c/coreboot/+/37199/11/src/cpu/x86/mtrr/cbmem_cac... File src/cpu/x86/mtrr/cbmem_cache.c:
https://review.coreboot.org/c/coreboot/+/37199/11/src/cpu/x86/mtrr/cbmem_cac... PS11, Line 1: /* : * This file is part of the coreboot project. : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; version 2 of the License. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */ SPDX license?
Hello build bot (Jenkins), Patrick Georgi, Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/37199
to look at the new patch set (#12).
Change subject: cpu/x86/mtrr: Add helper function to cache cbmem in romstage ......................................................................
cpu/x86/mtrr: Add helper function to cache cbmem in romstage
Romstage has some operations on cbmem and external stage cache. In most circumstances this memory is set up as UC, so to speed up these operations like decompressing postcar, this has to be set up as WB.
Note: This should only be attempted on platforms where some form of non eviction mode is used to guarantee not blowing up CAR.
Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/cpu/x86/mtrr/Makefile.inc A src/cpu/x86/mtrr/cbmem_cache.c M src/include/cpu/x86/mtrr.h 3 files changed, 65 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37199/12
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Arthur Heymans (Code Review) -
HAOUAS Elyes (Code Review)