Arthur Heymans uploaded patch set #9 to this change.

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cpu/x86/mtrr: Add helper function to cache cbmem in romstage

Romstage has some operations on cbmem and external stage cache.
In most circumstances this memory is set up as UC, so to speed
up these operations like decompressing postcar, this has to be
set up as WB.

Note: This should only be attempted on platforms where some form
of non eviction mode is used to guarantee not blowing up CAR.

Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
---
M src/cpu/x86/mtrr/Makefile.inc
A src/cpu/x86/mtrr/cbmem_cache.c
M src/include/cpu/x86/mtrr.h
3 files changed, 76 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/37199/9

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Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Ic0bc487a11cd0f5c489383364c729547031beccc
Gerrit-Change-Number: 37199
Gerrit-PatchSet: 9
Gerrit-Owner: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Arthur Heymans <arthur@aheymans.xyz>
Gerrit-Reviewer: Martin Roth <martinroth@google.com>
Gerrit-Reviewer: Patrick Georgi <pgeorgi@google.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply@coreboot.org>
Gerrit-CC: Paul Menzel <paulepanter@users.sourceforge.net>
Gerrit-MessageType: newpatchset