coreboot-gerrit July 2020

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Change in coreboot[master]: sb/intel/lynxpoint/pcie.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43217 ) Change subject: sb/intel/lynxpoint/pcie.c: Drop dead code ...................................................................... sb/intel/lynxpoint/pcie.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I2fff78231d6dfbed56bb885aa23d5cd2a745325e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/43217/1 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index d957e8d..883dfc7 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -670,17 +670,6 @@ reg16 |= PCI_BRIDGE_CTL_NO_ISA; pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); -#ifdef EVEN_MORE_DEBUG - reg32 = pci_read_config32(dev, 0x20); - printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x24); - printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x28); - printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x2c); - printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); -#endif - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, 0x06); pci_write_config16(dev, 0x06, reg16); -- To view, visit https://review.coreboot.org/c/coreboot/+/43217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fff78231d6dfbed56bb885aa23d5cd2a745325e Gerrit-Change-Number: 43217 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

4 4

Change in coreboot[master]: mb/google/zork: Always load and run display oprom
by Rob Barnes (Code Review) 09 Jul '20

09 Jul '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43257 ) Change subject: mb/google/zork: Always load and run display oprom ...................................................................... mb/google/zork: Always load and run display oprom The kernel requires the display oprom is loaded and ran in order for the kernel to not panic. Therefore, select the correct settings such that normal mode works for Chrome OS. BUG=b:160560510 TEST=Boot Trembyle in developer mode and normal mode Change-Id: Ia6bcc99f8880a45818f959a957660c2c43b1bfdf Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/Kconfig 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/43257/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index e24f78a..fec844d 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -13,6 +13,8 @@ select SOC_AMD_COMMON_BLOCK_USE_ESPI select SOC_AMD_PICASSO select VGA_BIOS + select ALWAYS_LOAD_OPROM + select ALWAYS_RUN_OPROM select BOARD_ROMSIZE_KB_16384 select DISABLE_SPI_FLASH_ROM_SHARING select DRIVERS_GENERIC_GPIO_KEYS -- To view, visit https://review.coreboot.org/c/coreboot/+/43257 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia6bcc99f8880a45818f959a957660c2c43b1bfdf Gerrit-Change-Number: 43257 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

7 19

Change in coreboot[master]: mb/google/zork: Add VBOOT_VBNV_CMOS flag
by Rob Barnes (Code Review) 09 Jul '20

09 Jul '20

Rob Barnes has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43176 ) Change subject: mb/google/zork: Add VBOOT_VBNV_CMOS flag ...................................................................... mb/google/zork: Add VBOOT_VBNV_CMOS flag Add VBOOT_VBNV_CMOS flag for zork boards. BUG=b:160297933 TEST=Enter and leave developer mode on Ezkinil Change-Id: I19ec139c8f098da630eeab199fec55297e3d977c Signed-off-by: Rob Barnes <robbarnes(a)google.com> --- M src/mainboard/google/zork/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/43176/1 diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index e24f78a..16fa6e8 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -102,6 +102,7 @@ select VBOOT_LID_SWITCH select VBOOT_STARTS_IN_BOOTBLOCK select VBOOT_SEPARATE_VERSTAGE + select VBOOT_VBNV_CMOS config VBOOT_VBNV_OFFSET hex -- To view, visit https://review.coreboot.org/c/coreboot/+/43176 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I19ec139c8f098da630eeab199fec55297e3d977c Gerrit-Change-Number: 43176 Gerrit-PatchSet: 1 Gerrit-Owner: Rob Barnes <robbarnes(a)google.com> Gerrit-MessageType: newchange

3 15

Change in coreboot[master]: mb/asrock/b85m_pro4: Add Super I/O GPIO table
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42404 ) Change subject: mb/asrock/b85m_pro4: Add Super I/O GPIO table ...................................................................... mb/asrock/b85m_pro4: Add Super I/O GPIO table Information taken from the boardviews. We are not configuring any GPIO in bootblock, but we may want to do so in the future. Change-Id: Iac16f02490adcccd9486718847ca2b1a47f4e6cf Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/bootblock.c 1 file changed, 35 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/04/42404/1 diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c index ad2a4c3..3bf4c3e 100644 --- a/src/mainboard/asrock/b85m_pro4/bootblock.c +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -9,6 +9,41 @@ #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1) #define ACPI_DEV PNP_DEV(0x2e, NCT6776_ACPI) +/* + * Asrock B85M Pro4 Super I/O GPIOs + * + * +------+-----+---------------------------+ + * | GPIO | Pin | Description | + * +------+-----+---------------------------+ + * | GP00 | 2 | N/C | + * | GP01 | 4 | CPU Fan 4-pin tach enable | + * | GP02 | 5 | CPU Fan 3-pin tach enable | + * | GP03 | 8 | CPU Fan 3-pin FON# signal | + * | GP04 | 9 | N/C | + * | GP05 | 11 | N/C (+1.05V_PCH_GPIO) | + * | GP06 | 12 | N/C (+1.5V_PCH_GPIO) | + * | GP07 | 13 | N/C | + * +------+-----+---------------------------+ + * | GP10 | 123 | N/C (VCCM_OV1) | + * | GP11 | 122 | N/C (VCCM_OV2) | + * | GP12 | 121 | N/C (VCCM_OV3) | + * | GP13 | 120 | N/C (VCCM_STEP) | + * | GP14 | 119 | Assert HDA_SDO (SIO_GP14) | + * | GP15 | 118 | N/C (PWM_THROTTLE) | + * | GP16 | 117 | OTP for VCORE (OTE_GATE1) | + * | GP17 | 116 | N/C (IMON_GPIO) | + * +------+-----+---------------------------+ + * | GP70 | 93 | PWR_FANIN | + * | GP71 | 92 | N/C | + * | GP72 | 91 | N/C (SIO_PIN91) | + * | GP73 | 90 | CHA2_FANIN | + * | GP74 | 89 | N/C (SIO_PIN89) | + * | GP75 | 88 | N/C (SIO_PIN88) | + * | GP76 | 87 | HDA reset gate (GP76) | + * | GP77 | 86 | HDD_LED gate | + * +------+-----+---------------------------+ + */ + void mainboard_config_superio(void) { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); -- To view, visit https://review.coreboot.org/c/coreboot/+/42404 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iac16f02490adcccd9486718847ca2b1a47f4e6cf Gerrit-Change-Number: 42404 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/asrock/b85m_pro4: Properly select muxed functions
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42403 ) Change subject: mb/asrock/b85m_pro4: Properly select muxed functions ...................................................................... mb/asrock/b85m_pro4: Properly select muxed functions The old values were completely out of whack. Use the same settings as vendor firmware. Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/bootblock.c 1 file changed, 7 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/42403/1 diff --git a/src/mainboard/asrock/b85m_pro4/bootblock.c b/src/mainboard/asrock/b85m_pro4/bootblock.c index f95fb52..ad2a4c3 100644 --- a/src/mainboard/asrock/b85m_pro4/bootblock.c +++ b/src/mainboard/asrock/b85m_pro4/bootblock.c @@ -13,9 +13,13 @@ { nuvoton_pnp_enter_conf_state(GLOBAL_DEV); - /* Select HWM/LED functions instead of floppy functions */ - pnp_write_config(GLOBAL_DEV, 0x1c, 0x03); - pnp_write_config(GLOBAL_DEV, 0x24, 0x24); + /* Select SIO pin states */ + pnp_write_config(GLOBAL_DEV, 0x1b, 0x68); + pnp_write_config(GLOBAL_DEV, 0x1c, 0x80); + pnp_write_config(GLOBAL_DEV, 0x24, 0x1c); + pnp_write_config(GLOBAL_DEV, 0x27, 0xd0); + pnp_write_config(GLOBAL_DEV, 0x2a, 0x62); + pnp_write_config(GLOBAL_DEV, 0x2f, 0x03); /* Power RAM in S3 and let the PCH handle power failure actions */ pnp_set_logical_device(ACPI_DEV); -- To view, visit https://review.coreboot.org/c/coreboot/+/42403 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1 Gerrit-Change-Number: 42403 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 8

Change in coreboot[master]: haswell: Drop GPIO indirection layers
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43103 ) Change subject: haswell: Drop GPIO indirection layers ...................................................................... haswell: Drop GPIO indirection layers This simplifies things and makes type checking possible. Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/pch.h 10 files changed, 6 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/43103/1 diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index c29e219..a72418a 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -72,7 +72,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, }; romstage_common(&romstage_params); diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 078e87c..73c38e7 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -72,7 +72,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, }; romstage_common(&romstage_params); diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index c49d94f..5d9c37c 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -11,8 +11,6 @@ #include <superio/ite/it8772f/it8772f.h> #include "onboard.h" -extern const struct pch_lp_gpio_map mainboard_gpio_map[]; - void mainboard_config_rcba(void) { /* @@ -107,7 +105,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, }; /* Early SuperIO setup */ diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index bc14ee0..5261ddc 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -8,8 +8,6 @@ #include <southbridge/intel/lynxpoint/lp_gpio.h> #include "variant.h" -extern const struct pch_lp_gpio_map mainboard_gpio_map[]; - void mainboard_config_rcba(void) { /* @@ -77,7 +75,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, }; variant_romstage_entry(&romstage_params); diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index 2b5fe41..b1f9854 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -114,7 +114,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, .copy_spd = NULL, }; diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 05725ff..8bcabd9 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -70,7 +70,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .gpio_map = &mainboard_gpio_map, }; romstage_common(&romstage_params); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index fa4c240..eab1ef6 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -192,7 +192,6 @@ struct pei_data; struct romstage_params { struct pei_data *pei_data; - const void *gpio_map; void (*copy_spd)(struct pei_data *peid); }; void romstage_common(const struct romstage_params *params); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index 906404d..9c70743 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -23,7 +23,7 @@ enable_lapic(); - wake_from_s3 = early_pch_init(params->gpio_map); + wake_from_s3 = early_pch_init(); /* Perform some early chipset initialization required * before RAM initialization can work diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 4d29564..06f295c 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -13,6 +13,7 @@ #if CONFIG(INTEL_LYNXPOINT_LP) #include "lp_gpio.h" +extern const struct pch_lp_gpio_map mainboard_gpio_map[]; #else #include <southbridge/intel/common/gpio.h> #endif @@ -77,16 +78,16 @@ { } -int early_pch_init(const void *gpio_map) +int early_pch_init(void) { int wake_from_s3; pch_enable_bars(); #if CONFIG(INTEL_LYNXPOINT_LP) - setup_pch_lp_gpios(gpio_map); + setup_pch_lp_gpios(mainboard_gpio_map); #else - setup_pch_gpios(gpio_map); + setup_pch_gpios(mainboard_gpio_map); #endif pch_generic_setup(); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 7987486..c59878e 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -121,7 +121,7 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void enable_usb_bar(void); -int early_pch_init(const void *gpio_map); +int early_pch_init(void); void pch_enable_lpc(void); void mainboard_config_superio(void); void mainboard_config_rcba(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/43103 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f Gerrit-Change-Number: 43103 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: mb/google/slippy: Put GPIOs in a C file
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43102 ) Change subject: mb/google/slippy: Put GPIOs in a C file ...................................................................... mb/google/slippy: Put GPIOs in a C file This will allow dropping the pointer inside romstage_params. Change-Id: Iec6dac1a271b22d6c09b4064a9e8a310e57026a6 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/slippy/Makefile.inc M src/mainboard/google/slippy/romstage.c R src/mainboard/google/slippy/variants/falco/gpio.c M src/mainboard/google/slippy/variants/falco/romstage.c R src/mainboard/google/slippy/variants/leon/gpio.c M src/mainboard/google/slippy/variants/leon/romstage.c R src/mainboard/google/slippy/variants/peppy/gpio.c M src/mainboard/google/slippy/variants/peppy/romstage.c R src/mainboard/google/slippy/variants/wolf/gpio.c M src/mainboard/google/slippy/variants/wolf/romstage.c 10 files changed, 9 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/43102/1 diff --git a/src/mainboard/google/slippy/Makefile.inc b/src/mainboard/google/slippy/Makefile.inc index e652dac..8f75d72 100644 --- a/src/mainboard/google/slippy/Makefile.inc +++ b/src/mainboard/google/slippy/Makefile.inc @@ -7,6 +7,7 @@ smm-y += smihandler.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/romstage.c subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index 0b43adf..bc14ee0 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -5,8 +5,11 @@ #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> +#include <southbridge/intel/lynxpoint/lp_gpio.h> #include "variant.h" +extern const struct pch_lp_gpio_map mainboard_gpio_map[]; + void mainboard_config_rcba(void) { /* @@ -74,6 +77,7 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, + .gpio_map = &mainboard_gpio_map, }; variant_romstage_entry(&romstage_params); diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h b/src/mainboard/google/slippy/variants/falco/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/falco/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/falco/gpio.c index c6fc5ca..86efbb8 100644 --- a/src/mainboard/google/slippy/variants/falco/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/falco/gpio.c @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef FALCO_GPIO_H -#define FALCO_GPIO_H - -struct pch_lp_gpio_map; +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -103,5 +100,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 134c797..96fbbab 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -10,7 +10,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../variant.h" /* Copy SPD data for on-board memory */ @@ -86,6 +85,5 @@ memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); - rp->gpio_map = &mainboard_gpio_map; rp->copy_spd = copy_spd; } diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h b/src/mainboard/google/slippy/variants/leon/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/leon/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/leon/gpio.c index f40341a..63babd6 100644 --- a/src/mainboard/google/slippy/variants/leon/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/leon/gpio.c @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef LEON_GPIO_H -#define LEON_GPIO_H - -struct pch_lp_gpio_map; +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -103,5 +100,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index 1e20e09..35c5ef5 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -9,7 +9,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../variant.h" /* Copy SPD data for on-board memory */ @@ -80,6 +79,5 @@ memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); - rp->gpio_map = &mainboard_gpio_map; rp->copy_spd = copy_spd; } diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h b/src/mainboard/google/slippy/variants/peppy/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/peppy/gpio.c index 825e712..fb9ab95 100644 --- a/src/mainboard/google/slippy/variants/peppy/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/peppy/gpio.c @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef PEPPY_GPIO_H -#define PEPPY_GPIO_H - -struct pch_lp_gpio_map; +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -103,5 +100,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index e37787c..b7daf89 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -10,7 +10,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../onboard.h" #include "../../variant.h" @@ -97,6 +96,5 @@ memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); - rp->gpio_map = &mainboard_gpio_map; rp->copy_spd = copy_spd; } diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h b/src/mainboard/google/slippy/variants/wolf/gpio.c similarity index 97% rename from src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h rename to src/mainboard/google/slippy/variants/wolf/gpio.c index 7b1276a..9be9077 100644 --- a/src/mainboard/google/slippy/variants/wolf/include/variant/gpio.h +++ b/src/mainboard/google/slippy/variants/wolf/gpio.c @@ -1,9 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef WOLF_GPIO_H -#define WOLF_GPIO_H - -struct pch_lp_gpio_map; +#include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { LP_GPIO_UNUSED, /* 0: UNUSED */ @@ -103,5 +100,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index fd8e632..b35160f 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -10,7 +10,6 @@ #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> #include <southbridge/intel/lynxpoint/lp_gpio.h> -#include <variant/gpio.h> #include "../../variant.h" /* Copy SPD data for on-board memory */ @@ -84,6 +83,5 @@ memcpy(rp->pei_data->usb2_ports, usb2_ports, sizeof(usb2_ports)); memcpy(rp->pei_data->usb3_ports, usb3_ports, sizeof(usb3_ports)); - rp->gpio_map = &mainboard_gpio_map; rp->copy_spd = copy_spd; } -- To view, visit https://review.coreboot.org/c/coreboot/+/43102 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iec6dac1a271b22d6c09b4064a9e8a310e57026a6 Gerrit-Change-Number: 43102 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: mb/google/beltino: Put GPIOs in a C file
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43101 ) Change subject: mb/google/beltino: Put GPIOs in a C file ...................................................................... mb/google/beltino: Put GPIOs in a C file This will allow dropping the pointer inside romstage_params. Change-Id: I536225351a0353298381c16cff25f39098c19bba Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/google/beltino/Makefile.inc M src/mainboard/google/beltino/romstage.c R src/mainboard/google/beltino/variants/mccloud/gpio.c R src/mainboard/google/beltino/variants/monroe/gpio.c R src/mainboard/google/beltino/variants/panther/gpio.c R src/mainboard/google/beltino/variants/tricky/gpio.c R src/mainboard/google/beltino/variants/zako/gpio.c 7 files changed, 3 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/43101/1 diff --git a/src/mainboard/google/beltino/Makefile.inc b/src/mainboard/google/beltino/Makefile.inc index 0b448fc..ee8b8e5 100644 --- a/src/mainboard/google/beltino/Makefile.inc +++ b/src/mainboard/google/beltino/Makefile.inc @@ -7,6 +7,7 @@ smm-y += smihandler.c variants/$(VARIANT_DIR)/led.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c romstage-y += variants/$(VARIANT_DIR)/led.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 2b36b01..c49d94f 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -9,9 +9,10 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8772f/it8772f.h> -#include <variant/gpio.h> #include "onboard.h" +extern const struct pch_lp_gpio_map mainboard_gpio_map[]; + void mainboard_config_rcba(void) { /* diff --git a/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h b/src/mainboard/google/beltino/variants/mccloud/gpio.c similarity index 97% rename from src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/mccloud/gpio.c index 92a30e8..91e808d 100644 --- a/src/mainboard/google/beltino/variants/mccloud/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/mccloud/gpio.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef MCCLOUD_GPIO_H -#define MCCLOUD_GPIO_H - #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -103,5 +100,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h b/src/mainboard/google/beltino/variants/monroe/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/monroe/gpio.c index a51d60e..4aead21 100644 --- a/src/mainboard/google/beltino/variants/monroe/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/monroe/gpio.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef MONROE_GPIO_H -#define MONROE_GPIO_H - #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -103,5 +100,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h b/src/mainboard/google/beltino/variants/panther/gpio.c similarity index 97% rename from src/mainboard/google/beltino/variants/panther/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/panther/gpio.c index ede463f..19e44e2 100644 --- a/src/mainboard/google/beltino/variants/panther/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/panther/gpio.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef PANTHER_GPIO_H -#define PANTHER_GPIO_H - #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -103,5 +100,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h b/src/mainboard/google/beltino/variants/tricky/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/tricky/gpio.c index 62b67fd..809a448 100644 --- a/src/mainboard/google/beltino/variants/tricky/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/tricky/gpio.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef TRICKY_GPIO_H -#define TRICKY_GPIO_H - #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -103,5 +100,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif diff --git a/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h b/src/mainboard/google/beltino/variants/zako/gpio.c similarity index 98% rename from src/mainboard/google/beltino/variants/zako/include/variant/gpio.h rename to src/mainboard/google/beltino/variants/zako/gpio.c index e391756..15cb0c0 100644 --- a/src/mainboard/google/beltino/variants/zako/include/variant/gpio.h +++ b/src/mainboard/google/beltino/variants/zako/gpio.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef ZAKO_GPIO_H -#define ZAKO_GPIO_H - #include <southbridge/intel/lynxpoint/lp_gpio.h> const struct pch_lp_gpio_map mainboard_gpio_map[] = { @@ -103,5 +100,3 @@ LP_GPIO_UNUSED, /* 94: UNUSED */ LP_GPIO_END }; - -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43101 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I536225351a0353298381c16cff25f39098c19bba Gerrit-Change-Number: 43101 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-MessageType: newchange

2 4

Change in coreboot[master]: sb/intel/lynxpoint: Drop RCBA reg script mechanism
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43099 ) Change subject: sb/intel/lynxpoint: Drop RCBA reg script mechanism ...................................................................... sb/intel/lynxpoint: Drop RCBA reg script mechanism It is no longer used anywhere. Drop it before it rots. Change-Id: I4bc3d5bd898058e575144a3c6c3fccb78dcff2e2 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/Makefile.inc M src/southbridge/intel/lynxpoint/pch.h D src/southbridge/intel/lynxpoint/rcba.c 3 files changed, 1 insertion(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/43099/1 diff --git a/src/southbridge/intel/lynxpoint/Makefile.inc b/src/southbridge/intel/lynxpoint/Makefile.inc index fa0ef0b..e3d056d 100644 --- a/src/southbridge/intel/lynxpoint/Makefile.inc +++ b/src/southbridge/intel/lynxpoint/Makefile.inc @@ -22,7 +22,6 @@ ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/hda_verb.c endif -ramstage-y += rcba.c ramstage-y += me_status.c ramstage-y += acpi.c @@ -34,7 +33,7 @@ bootblock-y += early_pch.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c early_pch.c -romstage-y += rcba.c pmutil.c +romstage-y += pmutil.c ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y) romstage-y += lp_gpio.c diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 77377c4..7987486 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -79,46 +79,6 @@ void usb_xhci_sleep_prepare(pci_devfn_t dev, u8 slp_typ); void usb_xhci_route_all(void); -/* State Machine configuration. */ -#define RCBA_REG_SIZE_MASK 0x8000 -#define RCBA_REG_SIZE_16 0x8000 -#define RCBA_REG_SIZE_32 0x0000 -#define RCBA_COMMAND_MASK 0x000f -#define RCBA_COMMAND_SET 0x0001 -#define RCBA_COMMAND_READ 0x0002 -#define RCBA_COMMAND_RMW 0x0003 -#define RCBA_COMMAND_END 0x0007 - -#define RCBA_ENCODE_COMMAND(command_, reg_, mask_, or_value_) \ - { .command = command_, \ - .reg = reg_, \ - .mask = mask_, \ - .or_value = or_value_ \ - } -#define RCBA_SET_REG_32(reg_, value_) \ - RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_32|RCBA_COMMAND_SET, reg_, 0, value_) -#define RCBA_READ_REG_32(reg_) \ - RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_32|RCBA_COMMAND_READ, reg_, 0, 0) -#define RCBA_RMW_REG_32(reg_, mask_, or_) \ - RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_32|RCBA_COMMAND_RMW, reg_, mask_, or_) -#define RCBA_SET_REG_16(reg_, value_) \ - RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_16|RCBA_COMMAND_SET, reg_, 0, value_) -#define RCBA_READ_REG_16(reg_) \ - RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_16|RCBA_COMMAND_READ, reg_, 0, 0) -#define RCBA_RMW_REG_16(reg_, mask_, or_) \ - RCBA_ENCODE_COMMAND(RCBA_REG_SIZE_16|RCBA_COMMAND_RMW, reg_, mask_, or_) -#define RCBA_END_CONFIG \ - RCBA_ENCODE_COMMAND(RCBA_COMMAND_END, 0, 0, 0) - -struct rcba_config_instruction -{ - u16 command; - u16 reg; - u32 mask; - u32 or_value; -}; - -void pch_config_rcba(const struct rcba_config_instruction *rcba_config); int pch_silicon_revision(void); int pch_silicon_id(void); int pch_silicon_type(void); diff --git a/src/southbridge/intel/lynxpoint/rcba.c b/src/southbridge/intel/lynxpoint/rcba.c deleted file mode 100644 index 9f62cd3..0000000 --- a/src/southbridge/intel/lynxpoint/rcba.c +++ /dev/null @@ -1,49 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <device/pci_def.h> -#include <device/device.h> -#include <device/pci.h> -#include "pch.h" - -void pch_config_rcba(const struct rcba_config_instruction *rcba_config) -{ - const struct rcba_config_instruction *rc; - u32 value; - - rc = rcba_config; - while (rc->command != RCBA_COMMAND_END) - { - if ((rc->command & RCBA_REG_SIZE_MASK) == RCBA_REG_SIZE_16) { - switch (rc->command & RCBA_COMMAND_MASK) { - case RCBA_COMMAND_SET: - RCBA16(rc->reg) = (u16)rc->or_value; - break; - case RCBA_COMMAND_READ: - (void)RCBA16(rc->reg); - break; - case RCBA_COMMAND_RMW: - value = RCBA16(rc->reg); - value &= rc->mask; - value |= rc->or_value; - RCBA16(rc->reg) = (u16)value; - break; - } - } else { - switch (rc->command & RCBA_COMMAND_MASK) { - case RCBA_COMMAND_SET: - RCBA32(rc->reg) = rc->or_value; - break; - case RCBA_COMMAND_READ: - (void)RCBA32(rc->reg); - break; - case RCBA_COMMAND_RMW: - value = RCBA32(rc->reg); - value &= rc->mask; - value |= rc->or_value; - RCBA32(rc->reg) = value; - break; - } - } - rc++; - } -} -- To view, visit https://review.coreboot.org/c/coreboot/+/43099 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4bc3d5bd898058e575144a3c6c3fccb78dcff2e2 Gerrit-Change-Number: 43099 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: haswell: Turn RCBA configuration into a function
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43097 ) Change subject: haswell: Turn RCBA configuration into a function ...................................................................... haswell: Turn RCBA configuration into a function Instead of passing around a pointer to an array, just write the relevant registers directly. Note that intel/baskingridge used spaces to indent line continuations and had to be replaced with tabs to quell Jenkins. Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/asrock/b85m_pro4/romstage.c M src/mainboard/asrock/h81m-hds/romstage.c M src/mainboard/google/beltino/romstage.c M src/mainboard/google/slippy/romstage.c M src/mainboard/intel/baskingridge/romstage.c M src/mainboard/lenovo/t440p/romstage.c M src/mainboard/supermicro/x10slm-f/romstage.c M src/northbridge/intel/haswell/haswell.h M src/northbridge/intel/haswell/romstage.c M src/southbridge/intel/lynxpoint/early_pch.c M src/southbridge/intel/lynxpoint/pch.h 11 files changed, 109 insertions(+), 128 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/43097/1 diff --git a/src/mainboard/asrock/b85m_pro4/romstage.c b/src/mainboard/asrock/b85m_pro4/romstage.c index 5206e96..c29e219 100644 --- a/src/mainboard/asrock/b85m_pro4/romstage.c +++ b/src/mainboard/asrock/b85m_pro4/romstage.c @@ -9,18 +9,17 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h> -static const struct rcba_config_instruction rcba_config[] = { - RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), - RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), - RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), - RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), - RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), - RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} void mainboard_romstage_entry(void) { @@ -74,7 +73,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], }; romstage_common(&romstage_params); diff --git a/src/mainboard/asrock/h81m-hds/romstage.c b/src/mainboard/asrock/h81m-hds/romstage.c index 3ea03cb..078e87c 100644 --- a/src/mainboard/asrock/h81m-hds/romstage.c +++ b/src/mainboard/asrock/h81m-hds/romstage.c @@ -9,18 +9,17 @@ #include <southbridge/intel/common/gpio.h> #include <southbridge/intel/lynxpoint/pch.h> -static const struct rcba_config_instruction rcba_config[] = { - RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), - RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), - RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), - RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB)), - RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQB); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} void mainboard_romstage_entry(void) { @@ -74,7 +73,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], }; romstage_common(&romstage_params); diff --git a/src/mainboard/google/beltino/romstage.c b/src/mainboard/google/beltino/romstage.c index 3a19d57..2b36b01 100644 --- a/src/mainboard/google/beltino/romstage.c +++ b/src/mainboard/google/beltino/romstage.c @@ -12,8 +12,8 @@ #include <variant/gpio.h> #include "onboard.h" -const struct rcba_config_instruction rcba_config[] = { - +void mainboard_config_rcba(void) +{ /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP PCIE INTA -> PIRQA @@ -26,28 +26,26 @@ */ /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCI); /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - - RCBA_END_CONFIG, -}; + RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ + RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ + RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ + RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ + RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ + RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ + RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ + RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ +} void mainboard_romstage_entry(void) { @@ -109,7 +107,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], }; /* Early SuperIO setup */ diff --git a/src/mainboard/google/slippy/romstage.c b/src/mainboard/google/slippy/romstage.c index fdb887b..0b43adf 100644 --- a/src/mainboard/google/slippy/romstage.c +++ b/src/mainboard/google/slippy/romstage.c @@ -7,8 +7,8 @@ #include <southbridge/intel/lynxpoint/pch.h> #include "variant.h" -const struct rcba_config_instruction rcba_config[] = { - +void mainboard_config_rcba(void) +{ /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP PCIE INTA -> PIRQA @@ -21,28 +21,26 @@ */ /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), - RCBA_SET_REG_32(D20IP, (INTA << D20IP_XHCI)), + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); + RCBA32(D20IP) = (INTA << D20IP_XHCI); /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA)),/* LPC */ - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD)),/* EHCI */ - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)),/* PCIE */ - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG)),/* HDA */ - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)),/* ME */ - RCBA_SET_REG_32(D21IR, DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF)),/* SIO */ - RCBA_SET_REG_32(D20IR, DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC)),/* XHCI */ - RCBA_SET_REG_32(D23IR, DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH)),/* SDIO */ - - RCBA_END_CONFIG, -}; + RCBA32(D31IR) = DIR_ROUTE(PIRQG, PIRQC, PIRQB, PIRQA); /* LPC */ + RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQD, PIRQD, PIRQD); /* EHCI */ + RCBA32(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); /* PCIE */ + RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQG, PIRQG, PIRQG); /* HDA */ + RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); /* ME */ + RCBA32(D21IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQF, PIRQF); /* SIO */ + RCBA32(D20IR) = DIR_ROUTE(PIRQC, PIRQC, PIRQC, PIRQC); /* XHCI */ + RCBA32(D23IR) = DIR_ROUTE(PIRQH, PIRQH, PIRQH, PIRQH); /* SDIO */ +} void mainboard_romstage_entry(void) { @@ -76,7 +74,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, - .rcba_config = rcba_config, }; variant_romstage_entry(&romstage_params); diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index a71d0bd..2b5fe41 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -9,7 +9,8 @@ #include <southbridge/intel/lynxpoint/pch.h> #include "gpio.h" -const struct rcba_config_instruction rcba_config[] = { +void mainboard_config_rcba(void) +{ /* * GFX INTA -> PIRQA (MSI) * D28IP_P1IP WLAN INTA -> PIRQB @@ -23,28 +24,26 @@ */ /* Device interrupt pin register (board specific) */ - RCBA_SET_REG_32(D31IP, (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | - (INTB << D31IP_SMIP) | (INTA << D31IP_SIP)), - RCBA_SET_REG_32(D30IP, (NOINT << D30IP_PIP)), - RCBA_SET_REG_32(D29IP, (INTA << D29IP_E1P)), - RCBA_SET_REG_32(D28IP, (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | - (INTB << D28IP_P4IP)), - RCBA_SET_REG_32(D27IP, (INTA << D27IP_ZIP)), - RCBA_SET_REG_32(D26IP, (INTA << D26IP_E2P)), - RCBA_SET_REG_32(D25IP, (NOINT << D25IP_LIP)), - RCBA_SET_REG_32(D22IP, (NOINT << D22IP_MEI1IP)), + RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) | + (INTB << D31IP_SMIP) | (INTA << D31IP_SIP); + RCBA32(D30IP) = (NOINT << D30IP_PIP); + RCBA32(D29IP) = (INTA << D29IP_E1P); + RCBA32(D28IP) = (INTA << D28IP_P1IP) | (INTC << D28IP_P3IP) | + (INTB << D28IP_P4IP); + RCBA32(D27IP) = (INTA << D27IP_ZIP); + RCBA32(D26IP) = (INTA << D26IP_E2P); + RCBA32(D25IP) = (NOINT << D25IP_LIP); + RCBA32(D22IP) = (NOINT << D22IP_MEI1IP); /* Device interrupt route registers */ - RCBA_SET_REG_32(D31IR, DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA)), - RCBA_SET_REG_32(D29IR, DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG)), - RCBA_SET_REG_32(D28IR, DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE)), - RCBA_SET_REG_32(D27IR, DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB)), - RCBA_SET_REG_32(D26IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_32(D25IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_32(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; + RCBA32(D31IR) = DIR_ROUTE(PIRQF, PIRQG, PIRQH, PIRQA); + RCBA32(D29IR) = DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG); + RCBA32(D28IR) = DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE); + RCBA32(D27IR) = DIR_ROUTE(PIRQG, PIRQH, PIRQA, PIRQB); + RCBA32(D26IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA32(D25IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA32(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} void mainboard_romstage_entry(void) { @@ -116,7 +115,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = &rcba_config[0], .copy_spd = NULL, }; diff --git a/src/mainboard/lenovo/t440p/romstage.c b/src/mainboard/lenovo/t440p/romstage.c index fec05c6..df1b04c 100644 --- a/src/mainboard/lenovo/t440p/romstage.c +++ b/src/mainboard/lenovo/t440p/romstage.c @@ -11,18 +11,17 @@ #include <ec/lenovo/pmh7/pmh7.h> #include <device/pci_ops.h> -static const struct rcba_config_instruction rcba_config[] = { - RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), - RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), - RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA)), - RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), - RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQA, PIRQA, PIRQA); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} void mb_post_raminit_setup(void) { @@ -96,7 +95,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = rcba_config, }; romstage_common(&romstage_params); diff --git a/src/mainboard/supermicro/x10slm-f/romstage.c b/src/mainboard/supermicro/x10slm-f/romstage.c index 5f30eb8..05725ff 100644 --- a/src/mainboard/supermicro/x10slm-f/romstage.c +++ b/src/mainboard/supermicro/x10slm-f/romstage.c @@ -8,18 +8,17 @@ #include <southbridge/intel/lynxpoint/pch.h> #include <stdint.h> -static const struct rcba_config_instruction rcba_config[] = { - RCBA_SET_REG_16(D31IR, DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA)), - RCBA_SET_REG_16(D29IR, DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC)), - RCBA_SET_REG_16(D28IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D27IR, DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D26IR, DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD)), - RCBA_SET_REG_16(D25IR, DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH)), - RCBA_SET_REG_16(D22IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - RCBA_SET_REG_16(D20IR, DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD)), - - RCBA_END_CONFIG, -}; +void mainboard_config_rcba(void) +{ + RCBA16(D31IR) = DIR_ROUTE(PIRQA, PIRQD, PIRQC, PIRQA); + RCBA16(D29IR) = DIR_ROUTE(PIRQH, PIRQD, PIRQA, PIRQC); + RCBA16(D28IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D27IR) = DIR_ROUTE(PIRQG, PIRQB, PIRQC, PIRQD); + RCBA16(D26IR) = DIR_ROUTE(PIRQA, PIRQF, PIRQC, PIRQD); + RCBA16(D25IR) = DIR_ROUTE(PIRQE, PIRQF, PIRQG, PIRQH); + RCBA16(D22IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); + RCBA16(D20IR) = DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD); +} void mainboard_romstage_entry(void) { @@ -72,7 +71,6 @@ struct romstage_params romstage_params = { .pei_data = &pei_data, .gpio_map = &mainboard_gpio_map, - .rcba_config = rcba_config, }; romstage_common(&romstage_params); diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h index 0b35acb..fa4c240 100644 --- a/src/northbridge/intel/haswell/haswell.h +++ b/src/northbridge/intel/haswell/haswell.h @@ -190,11 +190,9 @@ void intel_northbridge_haswell_finalize_smm(void); struct pei_data; -struct rcba_config_instruction; struct romstage_params { struct pei_data *pei_data; const void *gpio_map; - const struct rcba_config_instruction *rcba_config; void (*copy_spd)(struct pei_data *peid); }; void romstage_common(const struct romstage_params *params); diff --git a/src/northbridge/intel/haswell/romstage.c b/src/northbridge/intel/haswell/romstage.c index e5e29c1..906404d 100644 --- a/src/northbridge/intel/haswell/romstage.c +++ b/src/northbridge/intel/haswell/romstage.c @@ -23,7 +23,7 @@ enable_lapic(); - wake_from_s3 = early_pch_init(params->gpio_map, params->rcba_config); + wake_from_s3 = early_pch_init(params->gpio_map); /* Perform some early chipset initialization required * before RAM initialization can work diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index c6999a4..4d29564 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -77,8 +77,7 @@ { } -int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config) +int early_pch_init(const void *gpio_map) { int wake_from_s3; @@ -101,7 +100,7 @@ (void) RCBA16(OIC); /* Mainboard RCBA settings */ - pch_config_rcba(rcba_config); + mainboard_config_rcba(); RCBA32_OR(FD, PCH_DISABLE_ALWAYS); diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 093ebfa..77377c4 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -161,10 +161,10 @@ void acpi_create_serialio_ssdt(acpi_header_t *ssdt); void enable_usb_bar(void); -int early_pch_init(const void *gpio_map, - const struct rcba_config_instruction *rcba_config); +int early_pch_init(const void *gpio_map); void pch_enable_lpc(void); void mainboard_config_superio(void); +void mainboard_config_rcba(void); #define MAINBOARD_POWER_OFF 0 #define MAINBOARD_POWER_ON 1 -- To view, visit https://review.coreboot.org/c/coreboot/+/43097 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe Gerrit-Change-Number: 43097 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Tristan Corrick <tristan(a)corrick.kiwi> Gerrit-MessageType: newchange

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coreboot-gerrit July 2020