coreboot-gerrit July 2020

coreboot-gerrit@coreboot.org

1 participants
3167 discussions

Change in coreboot[master]: mb/aopen/dxplplusu: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43242 ) Change subject: mb/aopen/dxplplusu: Drop dead code ...................................................................... mb/aopen/dxplplusu: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I3f9b31a2bfb85ceb9ff833c076e062291c944923 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/aopen/dxplplusu/acpi/scsi.asl 1 file changed, 0 insertions(+), 16 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/43242/1 diff --git a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl index 6f51825..c34dd4e 100644 --- a/src/mainboard/aopen/dxplplusu/acpi/scsi.asl +++ b/src/mainboard/aopen/dxplplusu/acpi/scsi.asl @@ -27,19 +27,3 @@ Offset (0xFF), IDW, 8 } } - -#if 0 -/* Set subsystem id for both SCSI devices. - * It may require some delay on wake-up before this can be done. - */ - Method ( ) - { - Or (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS0.IDW) - Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS0.SID) - And (\_SB.PCI0.HLIB.P64A.SCS0.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS0.IDW) - - Or (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0x01, \_SB.PCI0.HLIB.P64A.SCS1.IDW) - Store (0x1106A0A0, \_SB.PCI0.HLIB.P64A.SCS1.SID) - And (\_SB.PCI0.HLIB.P64A.SCS1.IDW, 0xFE, \_SB.PCI0.HLIB.P64A.SCS1.IDW) - } -#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/43242 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I3f9b31a2bfb85ceb9ff833c076e062291c944923 Gerrit-Change-Number: 43242 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: mb/intel/glkrvp: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43239 ) Change subject: mb/intel/glkrvp: Drop dead code ...................................................................... mb/intel/glkrvp: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I6948a0b9a6b699cb44e3e02d9e134180bac2fa14 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/mainboard/intel/glkrvp/variants/baseboard/gpio.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/43239/1 diff --git a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c index 118b49e..56df526 100644 --- a/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c +++ b/src/mainboard/intel/glkrvp/variants/baseboard/gpio.c @@ -247,10 +247,6 @@ /* GPIO settings before entering sleep. */ static const struct pad_config sleep_gpio_table[] = { -#if 0 - PAD_CFG_GPO(GPIO_150, 0, DEEP), /* NFC_RESET_ODL */ - PAD_CFG_GPI_APIC_LOW(GPIO_20, NONE, DEEP), /* NFC_INT_L */ -#endif }; const struct pad_config * __weak @@ -261,10 +257,6 @@ } static const struct cros_gpio cros_gpios[] = { -#if 0 - CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), - CROS_GPIO_WP_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), -#endif }; const struct cros_gpio * __weak variant_cros_gpios(size_t *num) -- To view, visit https://review.coreboot.org/c/coreboot/+/43239 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I6948a0b9a6b699cb44e3e02d9e134180bac2fa14 Gerrit-Change-Number: 43239 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: nb/intel/ironlake/raminit.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43231 ) Change subject: nb/intel/ironlake/raminit.c: Drop dead code ...................................................................... nb/intel/ironlake/raminit.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I36500c1f0eb3c37d08c691d22382ceca732d1355 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/northbridge/intel/ironlake/raminit.c 1 file changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/43231/1 diff --git a/src/northbridge/intel/ironlake/raminit.c b/src/northbridge/intel/ironlake/raminit.c index 13f0c35..017951c 100644 --- a/src/northbridge/intel/ironlake/raminit.c +++ b/src/northbridge/intel/ironlake/raminit.c @@ -3652,12 +3652,6 @@ MCHBAR8(0x2ca8) = 0; system_reset(); } -#if 0 - if (!s3resume) { - pre_raminit_3(x2ca8); - } - pre_raminit_4a(x2ca8); -#endif dmi_setup(); @@ -3851,10 +3845,6 @@ collect_system_info(&info); calculate_timings(&info); -#if 0 - pci_write_config8(NORTHBRIDGE, 0xdf, 0x82); -#endif - if (!s3resume) { u8 reg8 = pci_read_config8(SOUTHBRIDGE, GEN_PMCON_2); if (x2ca8 == 0 && (reg8 & 0x80)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/43231 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I36500c1f0eb3c37d08c691d22382ceca732d1355 Gerrit-Change-Number: 43231 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 3

Change in coreboot[master]: sb/intel/lynxpoint/me_9.x.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43229 ) Change subject: sb/intel/lynxpoint/me_9.x.c: Drop dead code ...................................................................... sb/intel/lynxpoint/me_9.x.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I88cb6116c112b76336846d01e31f2cd40d6ca4cb Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/me_9.x.c 1 file changed, 0 insertions(+), 42 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/43229/1 diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index cdae271..77b3573 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -515,32 +515,6 @@ print_cap("Wireless LAN (WLAN)", cap->wlan); } -#if CONFIG(CHROMEOS) && 0 /* DISABLED */ -/* Tell ME to issue a global reset */ -static int mkhi_global_reset(void) -{ - struct me_global_reset reset = { - .request_origin = GLOBAL_RESET_BIOS_POST, - .reset_type = CBM_RR_GLOBAL_RESET, - }; - struct mkhi_header mkhi = { - .group_id = MKHI_GROUP_ID_CBM, - .command = MKHI_GLOBAL_RESET, - }; - - /* Send request and wait for response */ - printk(BIOS_NOTICE, "ME: %s\n", __func__); - if (mei_sendrecv_mkhi(&mkhi, &reset, sizeof(reset), NULL, 0) < 0) { - /* No response means reset will happen shortly... */ - halt(); - } - - /* If the ME responded it rejected the reset request */ - printk(BIOS_ERR, "ME: Global Reset failed\n"); - return -1; -} -#endif - /* Send END OF POST message to the ME */ static int __unused mkhi_end_of_post(void) { @@ -892,22 +866,6 @@ (me.buffer_depth - 1); } -#if 0 -/* This function is not yet being used, keep it in for the future. */ -static u32 host_to_me_words_room(void) -{ - struct mei_csr csr; - - read_me_csr(&csr); - if (!csr.ready) - return 0; - - read_host_csr(&csr); - return (csr.buffer_read_ptr - csr.buffer_write_ptr - 1) & - (csr.buffer_depth - 1); -} -#endif - struct mbp_payload { mbp_header header; u32 data[0]; -- To view, visit https://review.coreboot.org/c/coreboot/+/43229 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I88cb6116c112b76336846d01e31f2cd40d6ca4cb Gerrit-Change-Number: 43229 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: sb/intel/i82801gx/azalia.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43228 ) Change subject: sb/intel/i82801gx/azalia.c: Drop dead code ...................................................................... sb/intel/i82801gx/azalia.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I0fbdf8d7a3d89fefcd321dc3ba4ddd82c309e667 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801gx/azalia.c 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/43228/1 diff --git a/src/southbridge/intel/i82801gx/azalia.c b/src/southbridge/intel/i82801gx/azalia.c index 91f5857..cea75bd9 100644 --- a/src/southbridge/intel/i82801gx/azalia.c +++ b/src/southbridge/intel/i82801gx/azalia.c @@ -252,17 +252,6 @@ reg8 = pci_read_config8(dev, 0x4d); // Docking Status reg8 &= ~(1 << 7); // Docking not supported pci_write_config8(dev, 0x4d, reg8); -#if 0 - /* Set routing pin */ - pci_write_config32(dev, 0xf8, 0x0); - pci_write_config8(dev, 0xfc, 0xAA); - - /* Set INTA */ - pci_write_config8(dev, 0x63, 0x0); - - /* Enable azalia, disable ac97 */ - // pm_iowrite(0x59, 0xB); -#endif res = find_resource(dev, 0x10); if (!res) -- To view, visit https://review.coreboot.org/c/coreboot/+/43228 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0fbdf8d7a3d89fefcd321dc3ba4ddd82c309e667 Gerrit-Change-Number: 43228 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: sb/ti/pci7420: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43219 ) Change subject: sb/ti/pci7420: Drop dead code ...................................................................... sb/ti/pci7420: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I51a2b71abc7762b550f69f2980dd34f0e4947ab5 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/ti/pci7420/cardbus.c M src/southbridge/ti/pci7420/firewire.c 2 files changed, 0 insertions(+), 27 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/43219/1 diff --git a/src/southbridge/ti/pci7420/cardbus.c b/src/southbridge/ti/pci7420/cardbus.c index 02c4a01..6ef08a3 100644 --- a/src/southbridge/ti/pci7420/cardbus.c +++ b/src/southbridge/ti/pci7420/cardbus.c @@ -8,10 +8,6 @@ #include "pci7420.h" #include "chip.h" -#ifdef ODD_IRQ_FIXUP -static int cardbus_count = 0; -#endif - static void pci7420_cardbus_init(struct device *dev) { u8 reg8; @@ -47,20 +43,6 @@ /* Multifunction routing status */ pci_write_config32(dev, MFUNC, 0x018a1b22); - -#ifdef ODD_IRQ_FIXUP - /* This is a workaround for buggy kernels. This should - * probably be read from the device tree, but as long - * as only one mainboard is using this bridge it does - * not matter. - * - * Basically what we do here is assign INTA to the first - * cardbus controller, and INTB to the second one. We know - * there are only two of them. - */ - pci_write_config8(dev, PCI_INTERRUPT_PIN, cardbus_count); - cardbus_count++; -#endif } static void pci7420_cardbus_read_resources(struct device *dev) diff --git a/src/southbridge/ti/pci7420/firewire.c b/src/southbridge/ti/pci7420/firewire.c index ef06ea6..a327745 100644 --- a/src/southbridge/ti/pci7420/firewire.c +++ b/src/southbridge/ti/pci7420/firewire.c @@ -11,15 +11,6 @@ static void pci7420_firewire_init(struct device *dev) { printk(BIOS_DEBUG, "TI PCI7420/7620 FireWire init\n"); - -#ifdef ODD_IRQ_FIXUP - /* This is a workaround for buggy kernels. This should - * probably be read from the device tree, but as long - * as only one mainboard is using this bridge it does - * not matter - */ - pci_write_config8(dev, PCI_INTERRUPT_PIN, INTC); -#endif } static struct device_operations ti_pci7420_firewire_ops = { -- To view, visit https://review.coreboot.org/c/coreboot/+/43219 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I51a2b71abc7762b550f69f2980dd34f0e4947ab5 Gerrit-Change-Number: 43219 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: drivers/pc80/pc/i8259c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43211 ) Change subject: drivers/pc80/pc/i8259c: Drop dead code ...................................................................... drivers/pc80/pc/i8259c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I5bafcda2f8958e1ea4467749b40802deebe1cd3a Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/drivers/pc80/pc/i8259.c 1 file changed, 0 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/43211/1 diff --git a/src/drivers/pc80/pc/i8259.c b/src/drivers/pc80/pc/i8259.c index 1126f14..c6aaef3 100644 --- a/src/drivers/pc80/pc/i8259.c +++ b/src/drivers/pc80/pc/i8259.c @@ -108,18 +108,4 @@ /* Write new values */ outb((u8)(int_bits & 0xff), ELCR1); outb((u8)(int_bits >> 8), ELCR2); - -#ifdef PARANOID_IRQ_TRIGGERS - /* Try reading back the new values. This seems like an error - * but it is not. */ - if (inb(ELCR1) != (int_bits & 0xff)) { - printk(BIOS_ERR, "%s: lower order bits are wrong: want 0x%x, got 0x%x\n", - __func__, (int_bits & 0xff), inb(ELCR1)); - } - - if (inb(ELCR2) != (int_bits >> 8)) { - printk(BIOS_ERR, "%s: higher order bits are wrong: want 0x%x, got 0x%x\n", - __func__, (int_bits>>8), inb(ELCR2)); - } -#endif } -- To view, visit https://review.coreboot.org/c/coreboot/+/43211 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I5bafcda2f8958e1ea4467749b40802deebe1cd3a Gerrit-Change-Number: 43211 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: device/pci_device.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43210 ) Change subject: device/pci_device.c: Drop dead code ...................................................................... device/pci_device.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: Id3f9dd264e82f93a438422e388d70e3f88ae0df9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/device/pci_device.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/43210/1 diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 032e15c..3623c3b 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1631,11 +1631,6 @@ pci_write_config8(dev, PCI_INTERRUPT_LINE, pIntAtoD[line - 1]); -#ifdef PARANOID_IRQ_ASSIGNMENTS - irq = pci_read_config8(pdev, PCI_INTERRUPT_LINE); - printk(BIOS_DEBUG, " Readback = %d\n", irq); -#endif - #if CONFIG(PC80_SYSTEM) /* Change to level triggered. */ i8259_configure_irq_trigger(pIntAtoD[line - 1], -- To view, visit https://review.coreboot.org/c/coreboot/+/43210 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Id3f9dd264e82f93a438422e388d70e3f88ae0df9 Gerrit-Change-Number: 43210 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: cpu/intel/model_2065x/model_2065x_init.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43208 ) Change subject: cpu/intel/model_2065x/model_2065x_init.c: Drop dead code ...................................................................... cpu/intel/model_2065x/model_2065x_init.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I16fe12368ce7ffe2fd4d2a5580dd92c19a695848 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_2065x/model_2065x_init.c 1 file changed, 0 insertions(+), 26 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/43208/1 diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index 6f41ac5..3208e10 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -147,13 +147,6 @@ msr.lo = 0; msr.hi = 0; wrmsr(IA32_THERM_INTERRUPT, msr); - -#ifdef DISABLED - /* Enable package critical interrupt only */ - msr.lo = 1 << 4; - msr.hi = 0; - wrmsr(IA32_PACKAGE_THERM_INTERRUPT, msr); -#endif } static void enable_lapic_tpr(void) @@ -188,22 +181,6 @@ ((perf_ctl.lo >> 8) & 0xff) * IRONLAKE_BCLK); } -static void set_energy_perf_bias(u8 policy) -{ -#ifdef DISABLED - msr_t msr; - - /* Energy Policy is bits 3:0 */ - msr = rdmsr(IA32_ENERGY_PERF_BIAS); - msr.lo &= ~0xf; - msr.lo |= policy & 0xf; - wrmsr(IA32_ENERGY_PERF_BIAS, msr); - - printk(BIOS_DEBUG, "model_x06ax: energy policy set to %u\n", - policy); -#endif -} - static void configure_mca(void) { msr_t msr; @@ -247,9 +224,6 @@ /* Thermal throttle activation offset */ configure_thermal_target(); - /* Set energy policy */ - set_energy_perf_bias(ENERGY_POLICY_NORMAL); - /* Set Max Ratio */ set_max_ratio(); -- To view, visit https://review.coreboot.org/c/coreboot/+/43208 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I16fe12368ce7ffe2fd4d2a5580dd92c19a695848 Gerrit-Change-Number: 43208 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

2 2

Change in coreboot[master]: cpu/intel/model_206ax/finalize.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43206 ) Change subject: cpu/intel/model_206ax/finalize.c: Drop dead code ...................................................................... cpu/intel/model_206ax/finalize.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I76bf20bb2ec1cdd7ffee4430c80609978afaa1a4 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/model_206ax/finalize.c 1 file changed, 0 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/43206/1 diff --git a/src/cpu/intel/model_206ax/finalize.c b/src/cpu/intel/model_206ax/finalize.c index 10a95a2..c7579f1 100644 --- a/src/cpu/intel/model_206ax/finalize.c +++ b/src/cpu/intel/model_206ax/finalize.c @@ -16,24 +16,6 @@ if (cpuid_ecx(1) & (1 << 25)) msr_set_bit(MSR_FEATURE_CONFIG, 0); -#ifdef LOCK_POWER_CONTROL_REGISTERS - /* - * Lock the power control registers. - * - * These registers can be left unlocked if modifying power - * limits from the OS is desirable. Modifying power limits - * from the OS can be especially useful for experimentation - * during early phases of system bringup while the thermal - * power envelope is being proven. - */ - - msr_set_bit(MSR_PP0_CURRENT_CONFIG, 31); - msr_set_bit(MSR_PP1_CURRENT_CONFIG, 31); - msr_set_bit(MSR_PKG_POWER_LIMIT, 63); - msr_set_bit(MSR_PP0_POWER_LIMIT, 31); - msr_set_bit(MSR_PP1_POWER_LIMIT, 31); -#endif - /* Lock TM interrupts - route thermal events to all processors */ msr_set_bit(MSR_MISC_PWR_MGMT, 22); -- To view, visit https://review.coreboot.org/c/coreboot/+/43206 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I76bf20bb2ec1cdd7ffee4430c80609978afaa1a4 Gerrit-Change-Number: 43206 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

2 2

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit July 2020