coreboot-gerrit July 2020

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Change in coreboot[master]: soc/intel/broadwell/pcie.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43214 ) Change subject: soc/intel/broadwell/pcie.c: Drop dead code ...................................................................... soc/intel/broadwell/pcie.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: Ia314148abc900685d85aede3add480614fa8e99c Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/broadwell/pcie.c 1 file changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/43214/1 diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 9eb14d9..14dcd3f 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -590,18 +590,6 @@ reg16 |= PCI_BRIDGE_CTL_NO_ISA; pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); -#ifdef EVEN_MORE_DEBUG - u32 reg32; - reg32 = pci_read_config32(dev, 0x20); - printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x24); - printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x28); - printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x2c); - printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); -#endif - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, 0x06); pci_write_config16(dev, 0x06, reg16); -- To view, visit https://review.coreboot.org/c/coreboot/+/43214 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ia314148abc900685d85aede3add480614fa8e99c Gerrit-Change-Number: 43214 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/vboot/secdata_tpm.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43213 ) Change subject: security/vboot/secdata_tpm.c: Drop dead code ...................................................................... security/vboot/secdata_tpm.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: Ie01d65f80caf32a8318d5109ad48321661c5a87b Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/security/vboot/secdata_tpm.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/43213/1 diff --git a/src/security/vboot/secdata_tpm.c b/src/security/vboot/secdata_tpm.c index d350b38..dcb3c44 100644 --- a/src/security/vboot/secdata_tpm.c +++ b/src/security/vboot/secdata_tpm.c @@ -13,13 +13,8 @@ #include <vb2_api.h> #include <console/console.h> -#ifdef FOR_TEST -#include <stdio.h> -#define VBDEBUG(format, args...) printf(format, ## args) -#else #define VBDEBUG(format, args...) \ printk(BIOS_INFO, "%s():%d: " format, __func__, __LINE__, ## args) -#endif #define RETURN_ON_FAILURE(tpm_cmd) do { \ uint32_t result_; \ -- To view, visit https://review.coreboot.org/c/coreboot/+/43213 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie01d65f80caf32a8318d5109ad48321661c5a87b Gerrit-Change-Number: 43213 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: security/tpm/tss/tcg-1.2/tss.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43212 ) Change subject: security/tpm/tss/tcg-1.2/tss.c: Drop dead code ...................................................................... security/tpm/tss/tcg-1.2/tss.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: Ifda2bbd87cd8ef5ec8e449d2c4d303be37b4d7c7 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/security/tpm/tss/tcg-1.2/tss.c 1 file changed, 0 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/43212/1 diff --git a/src/security/tpm/tss/tcg-1.2/tss.c b/src/security/tpm/tss/tcg-1.2/tss.c index 4434ca6..30cd1cc 100644 --- a/src/security/tpm/tss/tcg-1.2/tss.c +++ b/src/security/tpm/tss/tcg-1.2/tss.c @@ -21,13 +21,8 @@ #include "tss_internal.h" #include "tss_commands.h" -#ifdef FOR_TEST -#include <stdio.h> -#define VBDEBUG(format, args...) printf(format, ## args) -#else #include <console/console.h> #define VBDEBUG(format, args...) printk(BIOS_DEBUG, format, ## args) -#endif static int tpm_send_receive(const uint8_t *request, uint32_t request_length, -- To view, visit https://review.coreboot.org/c/coreboot/+/43212 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ifda2bbd87cd8ef5ec8e449d2c4d303be37b4d7c7 Gerrit-Change-Number: 43212 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: soc/samsung/exynos5250/fb.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43215 ) Change subject: soc/samsung/exynos5250/fb.c: Drop dead code ...................................................................... soc/samsung/exynos5250/fb.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I4772680875b20308e57da073bbcdc4597aeed893 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/samsung/exynos5250/fb.c 1 file changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/43215/1 diff --git a/src/soc/samsung/exynos5250/fb.c b/src/soc/samsung/exynos5250/fb.c index 0292d76..98a4c66 100644 --- a/src/soc/samsung/exynos5250/fb.c +++ b/src/soc/samsung/exynos5250/fb.c @@ -140,14 +140,6 @@ write32(&exynos_fimd->dpclkcon, 1 << 1); } -#ifdef UNUSED_CODE -void exynos_fimd_disable(void) -{ - write32(&exynos_fimd->wincon0, 0); - clrbits32(&exynos_fimd->shadowcon, CHANNEL0_EN); -} -#endif - /* * Configure DP in slave mode and wait for video stream. * -- To view, visit https://review.coreboot.org/c/coreboot/+/43215 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I4772680875b20308e57da073bbcdc4597aeed893 Gerrit-Change-Number: 43215 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-MessageType: newchange

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Change in coreboot[master]: crossgcc: Allow GCC to get asan shadow offset at runtime
by Paul Menzel (Code Review) 09 Jul '20

09 Jul '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42794 ) Change subject: crossgcc: Allow GCC to get asan shadow offset at runtime ...................................................................... Patch Set 11: (2 comments) https://review.coreboot.org/c/coreboot/+/42794/11//COMMIT_MSG Commit Message: https://review.coreboot.org/c/coreboot/+/42794/11//COMMIT_MSG@15 PS11, Line 15: Please add more details, why GCC needs to be patched for coreboot, but apparently not for the Linux kernel, which also has KASAN support. Is this also necessary in newer GCC versions, or do those already support the use case? https://review.coreboot.org/c/coreboot/+/42794/11/util/crossgcc/patches/gcc… File util/crossgcc/patches/gcc-8.3.0_asan_shadow_offset_callback.patch: https://review.coreboot.org/c/coreboot/+/42794/11/util/crossgcc/patches/gcc… PS11, Line 1: diff -urN gcc-8.3.0.orig/gcc/asan.c gcc-8.3.0/gcc/asan.c Please add a patch file created with `git format-patch -1`, which contains a commit message. -- To view, visit https://review.coreboot.org/c/coreboot/+/42794 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I401631938532a406a6d41e77c6c9716b6b2bf48d Gerrit-Change-Number: 42794 Gerrit-PatchSet: 11 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Comment-Date: Thu, 09 Jul 2020 21:24:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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Change in coreboot[master]: volteer: enable VBOOT_EC_EFS
by Caveh Jalali (Code Review) 09 Jul '20

09 Jul '20

Caveh Jalali has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/43044 ) Change subject: volteer: enable VBOOT_EC_EFS ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/43044 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie71bb169242b2511b4a4102d46a6981d72d07806 Gerrit-Change-Number: 43044 Gerrit-PatchSet: 1 Gerrit-Owner: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Daisuke Nojiri <dnojiri(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Tim Wawrzynczak <twawrzynczak(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-MessageType: abandon

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Change in coreboot[master]: sb/intel/bd82x6x/pcie.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43216 ) Change subject: sb/intel/bd82x6x/pcie.c: Drop dead code ...................................................................... sb/intel/bd82x6x/pcie.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: Icd6b3226814f48c4cdd2c2f879c66cb6847a14e9 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/bd82x6x/pcie.c 1 file changed, 0 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/43216/1 diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index c381d33..2eff162 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -219,18 +219,6 @@ pci_update_config16(dev, PCI_BRIDGE_CONTROL, ~PCI_BRIDGE_CTL_PARITY, PCI_BRIDGE_CTL_NO_ISA); -#ifdef EVEN_MORE_DEBUG - u32 reg32; - reg32 = pci_read_config32(dev, 0x20); - printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x24); - printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x28); - printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x2c); - printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); -#endif - /* Clear errors in status registers. FIXME: Do something? */ reg16 = pci_read_config16(dev, 0x06); //reg16 |= 0xf900; -- To view, visit https://review.coreboot.org/c/coreboot/+/43216 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Icd6b3226814f48c4cdd2c2f879c66cb6847a14e9 Gerrit-Change-Number: 43216 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: lib: Add ASan support to ramstage on x86 arch
by Paul Menzel (Code Review) 09 Jul '20

09 Jul '20

Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42496 ) Change subject: lib: Add ASan support to ramstage on x86 arch ...................................................................... Patch Set 18: Code-Review+1 I rebased the series on master to be able to build it on ppc64le, rebuilt crossgcc, built an image for the ASRock E350M1 with KASAN enable, and it booted without errors. (I would have expected problems with AGESA, but maybe Coverity and the other static analyzers found all the bug already.) Great job! It’d be great if you rebased your series on origin/master. -- To view, visit https://review.coreboot.org/c/coreboot/+/42496 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ica06bd2be78fcfc79fa888721ed920d4e8248f3b Gerrit-Change-Number: 42496 Gerrit-PatchSet: 18 Gerrit-Owner: Harshit Sharma <harshitsharmajs(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Comment-Date: Thu, 09 Jul 2020 21:22:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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Change in coreboot[master]: sb/intel/i82801gx/pcie.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43218 ) Change subject: sb/intel/i82801gx/pcie.c: Drop dead code ...................................................................... sb/intel/i82801gx/pcie.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I0296cb4265c5b68ee9e11b140763b7d50d1da7ea Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/i82801gx/pcie.c 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/43218/1 diff --git a/src/southbridge/intel/i82801gx/pcie.c b/src/southbridge/intel/i82801gx/pcie.c index dcad322..6c0ca5d 100644 --- a/src/southbridge/intel/i82801gx/pcie.c +++ b/src/southbridge/intel/i82801gx/pcie.c @@ -84,17 +84,6 @@ reg16 |= (1 << 6); pci_write_config16(dev, 0x50, reg16); -#ifdef EVEN_MORE_DEBUG - reg32 = pci_read_config32(dev, 0x20); - printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x24); - printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x28); - printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x2c); - printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); -#endif - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, 0x06); //reg16 |= 0xf900; -- To view, visit https://review.coreboot.org/c/coreboot/+/43218 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I0296cb4265c5b68ee9e11b140763b7d50d1da7ea Gerrit-Change-Number: 43218 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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Change in coreboot[master]: sb/intel/lynxpoint/pcie.c: Drop dead code
by Angel Pons (Code Review) 09 Jul '20

09 Jul '20

Angel Pons has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/43217 ) Change subject: sb/intel/lynxpoint/pcie.c: Drop dead code ...................................................................... sb/intel/lynxpoint/pcie.c: Drop dead code This code is not even being build-tested. Drop it before it grows moss. Change-Id: I2fff78231d6dfbed56bb885aa23d5cd2a745325e Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/southbridge/intel/lynxpoint/pcie.c 1 file changed, 0 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/43217/1 diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index d957e8d..883dfc7 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -670,17 +670,6 @@ reg16 |= PCI_BRIDGE_CTL_NO_ISA; pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); -#ifdef EVEN_MORE_DEBUG - reg32 = pci_read_config32(dev, 0x20); - printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x24); - printk(BIOS_SPEW, " PMBL = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x28); - printk(BIOS_SPEW, " PMBU32 = 0x%08x\n", reg32); - reg32 = pci_read_config32(dev, 0x2c); - printk(BIOS_SPEW, " PMLU32 = 0x%08x\n", reg32); -#endif - /* Clear errors in status registers */ reg16 = pci_read_config16(dev, 0x06); pci_write_config16(dev, 0x06, reg16); -- To view, visit https://review.coreboot.org/c/coreboot/+/43217 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I2fff78231d6dfbed56bb885aa23d5cd2a745325e Gerrit-Change-Number: 43217 Gerrit-PatchSet: 1 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-MessageType: newchange

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coreboot-gerrit July 2020